86 static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)  in ahci_sunxi_phy_init()  argument
92 	writel(0, reg_base + AHCI_RWCR);  in ahci_sunxi_phy_init()
95 	sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));  in ahci_sunxi_phy_init()
96 	sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,  in ahci_sunxi_phy_init()
99 	sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,  in ahci_sunxi_phy_init()
102 	sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));  in ahci_sunxi_phy_init()
103 	sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));  in ahci_sunxi_phy_init()
104 	sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,  in ahci_sunxi_phy_init()
106 	sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,  in ahci_sunxi_phy_init()
110 	sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));  in ahci_sunxi_phy_init()
114 		reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);  in ahci_sunxi_phy_init()
125 	sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));  in ahci_sunxi_phy_init()
129 		reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);  in ahci_sunxi_phy_init()
142 	writel(0x7, reg_base + AHCI_RWCR);  in ahci_sunxi_phy_init()