Lines Matching +full:power +full:- +full:gate
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/jz4770-cgu.h>
47 #define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled()
86 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
155 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
163 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
171 CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1,
174 .gate = { CGU_REG_CLKGR1, 7 },
180 CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
188 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
191 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
197 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
208 .div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 },
209 .gate = { CGU_REG_MSC0CDR, 31 },
215 .div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 },
216 .gate = { CGU_REG_MSC1CDR, 31 },
222 .div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 },
223 .gate = { CGU_REG_MSC2CDR, 31 },
229 .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
230 .gate = { CGU_REG_CLKGR0, 26 },
236 .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
237 .gate = { CGU_REG_CLKGR0, 24 },
241 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 },
243 .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
244 .gate = { CGU_REG_CLKGR1, 9 },
250 .div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 },
251 .gate = { CGU_REG_CLKGR0, 1 },
257 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
258 .gate = { CGU_REG_CLKGR0, 28 },
264 .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
265 .gate = { CGU_REG_CLKGR0, 22 },
272 .parents = { JZ4770_CLK_EXT, -1,
275 .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1 },
279 .parents = { JZ4770_CLK_EXT, -1,
282 .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1 },
286 .parents = { JZ4770_CLK_EXT, -1,
289 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
290 .gate = { CGU_REG_CLKGR1, 13 },
294 .parents = { JZ4770_CLK_EXT, -1,
297 .div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
298 .gate = { CGU_REG_CLKGR0, 2 },
301 /* Gate-only clocks */
306 .gate = { CGU_REG_CLKGR0, 4 },
311 .gate = { CGU_REG_CLKGR0, 19 },
316 .gate = { CGU_REG_CLKGR0, 20 },
321 .gate = { CGU_REG_CLKGR1, 8 },
326 .gate = { CGU_REG_CLKGR1, 10 },
331 .gate = { CGU_REG_CLKGR0, 21 },
336 .gate = { CGU_REG_CLKGR0, 5 },
341 .gate = { CGU_REG_CLKGR0, 6 },
346 .gate = { CGU_REG_CLKGR1, 15 },
351 .gate = { CGU_REG_CLKGR0, 15 },
356 .gate = { CGU_REG_CLKGR0, 16 },
361 .gate = { CGU_REG_CLKGR0, 17 },
366 .gate = { CGU_REG_CLKGR0, 18 },
371 .gate = { CGU_REG_CLKGR0, 29 },
376 .gate = { CGU_REG_CLKGR0, 14 },
381 .gate = { CGU_REG_CLKGR0, 8 },
386 .gate = { CGU_REG_CLKGR1, 14 },
391 .gate = { CGU_REG_LCR, 30, false, 150 },
396 .gate = { CGU_REG_CLKGR0, 3 },
401 .gate = { CGU_REG_CLKGR0, 11 },
406 .gate = { CGU_REG_CLKGR0, 12 },
411 .gate = { CGU_REG_OPCR, 7, true, 50 },
418 .parents = { JZ4770_CLK_UHC, -1, -1, -1 },
454 CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);