Lines Matching +full:4 +full:- +full:ch
1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
40 * 16B 32B 32B-F 48B R-Car Gen2
41 * -----------------------------------------------------------------------------
42 * Channels 2 1/4 1 6 2/8
47 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
51 * Channels are indexed from 0 to N-1 in the documentation. The channel index
56 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
60 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
61 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
149 #define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
150 #define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
151 #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
152 #define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
154 #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
240 #define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */
242 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) in sh_cmt_read_cmstr() argument
244 if (ch->iostart) in sh_cmt_read_cmstr()
245 return ch->cmt->info->read_control(ch->iostart, 0); in sh_cmt_read_cmstr()
247 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); in sh_cmt_read_cmstr()
250 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmstr() argument
252 u32 old_value = sh_cmt_read_cmstr(ch); in sh_cmt_write_cmstr()
255 if (ch->iostart) { in sh_cmt_write_cmstr()
256 ch->cmt->info->write_control(ch->iostart, 0, value); in sh_cmt_write_cmstr()
257 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmstr()
259 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); in sh_cmt_write_cmstr()
260 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmstr()
265 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) in sh_cmt_read_cmcsr() argument
267 return ch->cmt->info->read_control(ch->ioctrl, CMCSR); in sh_cmt_read_cmcsr()
270 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmcsr() argument
272 u32 old_value = sh_cmt_read_cmcsr(ch); in sh_cmt_write_cmcsr()
275 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); in sh_cmt_write_cmcsr()
276 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmcsr()
280 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) in sh_cmt_read_cmcnt() argument
282 return ch->cmt->info->read_count(ch->ioctrl, CMCNT); in sh_cmt_read_cmcnt()
285 static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmcnt() argument
288 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2); in sh_cmt_write_cmcnt()
291 if (ch->cmt->info->model > SH_CMT_16BIT) { in sh_cmt_write_cmcnt()
294 1, cmcnt_delay, false, ch); in sh_cmt_write_cmcnt()
299 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); in sh_cmt_write_cmcnt()
304 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmcor() argument
306 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR); in sh_cmt_write_cmcor()
309 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); in sh_cmt_write_cmcor()
310 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmcor()
314 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) in sh_cmt_get_counter() argument
319 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
324 v1 = sh_cmt_read_cmcnt(ch); in sh_cmt_get_counter()
325 v2 = sh_cmt_read_cmcnt(ch); in sh_cmt_get_counter()
326 v3 = sh_cmt_read_cmcnt(ch); in sh_cmt_get_counter()
327 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
335 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) in sh_cmt_start_stop_ch() argument
341 raw_spin_lock_irqsave(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
342 value = sh_cmt_read_cmstr(ch); in sh_cmt_start_stop_ch()
345 value |= 1 << ch->timer_bit; in sh_cmt_start_stop_ch()
347 value &= ~(1 << ch->timer_bit); in sh_cmt_start_stop_ch()
349 sh_cmt_write_cmstr(ch, value); in sh_cmt_start_stop_ch()
350 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
353 static int sh_cmt_enable(struct sh_cmt_channel *ch) in sh_cmt_enable() argument
357 pm_runtime_get_sync(&ch->cmt->pdev->dev); in sh_cmt_enable()
358 dev_pm_syscore_device(&ch->cmt->pdev->dev, true); in sh_cmt_enable()
361 ret = clk_enable(ch->cmt->clk); in sh_cmt_enable()
363 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", in sh_cmt_enable()
364 ch->index); in sh_cmt_enable()
369 sh_cmt_start_stop_ch(ch, 0); in sh_cmt_enable()
372 if (ch->cmt->info->width == 16) { in sh_cmt_enable()
373 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | in sh_cmt_enable()
376 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | in sh_cmt_enable()
382 sh_cmt_write_cmcor(ch, 0xffffffff); in sh_cmt_enable()
383 ret = sh_cmt_write_cmcnt(ch, 0); in sh_cmt_enable()
385 if (ret || sh_cmt_read_cmcnt(ch)) { in sh_cmt_enable()
386 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", in sh_cmt_enable()
387 ch->index); in sh_cmt_enable()
388 ret = -ETIMEDOUT; in sh_cmt_enable()
393 sh_cmt_start_stop_ch(ch, 1); in sh_cmt_enable()
397 clk_disable(ch->cmt->clk); in sh_cmt_enable()
403 static void sh_cmt_disable(struct sh_cmt_channel *ch) in sh_cmt_disable() argument
406 sh_cmt_start_stop_ch(ch, 0); in sh_cmt_disable()
409 sh_cmt_write_cmcsr(ch, 0); in sh_cmt_disable()
412 clk_disable(ch->cmt->clk); in sh_cmt_disable()
414 dev_pm_syscore_device(&ch->cmt->pdev->dev, false); in sh_cmt_disable()
415 pm_runtime_put(&ch->cmt->pdev->dev); in sh_cmt_disable()
423 #define FLAG_IRQCONTEXT (1 << 4)
425 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, in sh_cmt_clock_event_program_verify() argument
428 u32 value = ch->next_match_value; in sh_cmt_clock_event_program_verify()
434 now = sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clock_event_program_verify()
435 ch->flags |= FLAG_REPROGRAM; /* force reprogram */ in sh_cmt_clock_event_program_verify()
439 * -> let the interrupt handler reprogram the timer. in sh_cmt_clock_event_program_verify()
440 * -> interrupt number two handles the event. in sh_cmt_clock_event_program_verify()
442 ch->flags |= FLAG_SKIPEVENT; in sh_cmt_clock_event_program_verify()
454 if (new_match > ch->max_match_value) in sh_cmt_clock_event_program_verify()
455 new_match = ch->max_match_value; in sh_cmt_clock_event_program_verify()
457 sh_cmt_write_cmcor(ch, new_match); in sh_cmt_clock_event_program_verify()
459 now = sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clock_event_program_verify()
460 if (has_wrapped && (new_match > ch->match_value)) { in sh_cmt_clock_event_program_verify()
464 * -> first interrupt reprograms the timer. in sh_cmt_clock_event_program_verify()
465 * -> interrupt number two handles the event. in sh_cmt_clock_event_program_verify()
467 ch->flags |= FLAG_SKIPEVENT; in sh_cmt_clock_event_program_verify()
475 * -> save programmed match value. in sh_cmt_clock_event_program_verify()
476 * -> let isr handle the event. in sh_cmt_clock_event_program_verify()
478 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
486 * -> save programmed match value. in sh_cmt_clock_event_program_verify()
487 * -> let isr handle the event. in sh_cmt_clock_event_program_verify()
489 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
497 * -> increase delay and retry. in sh_cmt_clock_event_program_verify()
505 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", in sh_cmt_clock_event_program_verify()
506 ch->index); in sh_cmt_clock_event_program_verify()
511 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) in __sh_cmt_set_next() argument
513 if (delta > ch->max_match_value) in __sh_cmt_set_next()
514 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", in __sh_cmt_set_next()
515 ch->index); in __sh_cmt_set_next()
517 ch->next_match_value = delta; in __sh_cmt_set_next()
518 sh_cmt_clock_event_program_verify(ch, 0); in __sh_cmt_set_next()
521 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) in sh_cmt_set_next() argument
525 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_set_next()
526 __sh_cmt_set_next(ch, delta); in sh_cmt_set_next()
527 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_set_next()
532 struct sh_cmt_channel *ch = dev_id; in sh_cmt_interrupt() local
535 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & in sh_cmt_interrupt()
536 ch->cmt->info->clear_bits); in sh_cmt_interrupt()
542 if (ch->flags & FLAG_CLOCKSOURCE) in sh_cmt_interrupt()
543 ch->total_cycles += ch->match_value + 1; in sh_cmt_interrupt()
545 if (!(ch->flags & FLAG_REPROGRAM)) in sh_cmt_interrupt()
546 ch->next_match_value = ch->max_match_value; in sh_cmt_interrupt()
548 ch->flags |= FLAG_IRQCONTEXT; in sh_cmt_interrupt()
550 if (ch->flags & FLAG_CLOCKEVENT) { in sh_cmt_interrupt()
551 if (!(ch->flags & FLAG_SKIPEVENT)) { in sh_cmt_interrupt()
552 if (clockevent_state_oneshot(&ch->ced)) { in sh_cmt_interrupt()
553 ch->next_match_value = ch->max_match_value; in sh_cmt_interrupt()
554 ch->flags |= FLAG_REPROGRAM; in sh_cmt_interrupt()
557 ch->ced.event_handler(&ch->ced); in sh_cmt_interrupt()
561 ch->flags &= ~FLAG_SKIPEVENT; in sh_cmt_interrupt()
563 if (ch->flags & FLAG_REPROGRAM) { in sh_cmt_interrupt()
564 ch->flags &= ~FLAG_REPROGRAM; in sh_cmt_interrupt()
565 sh_cmt_clock_event_program_verify(ch, 1); in sh_cmt_interrupt()
567 if (ch->flags & FLAG_CLOCKEVENT) in sh_cmt_interrupt()
568 if ((clockevent_state_shutdown(&ch->ced)) in sh_cmt_interrupt()
569 || (ch->match_value == ch->next_match_value)) in sh_cmt_interrupt()
570 ch->flags &= ~FLAG_REPROGRAM; in sh_cmt_interrupt()
573 ch->flags &= ~FLAG_IRQCONTEXT; in sh_cmt_interrupt()
578 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) in sh_cmt_start() argument
583 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_start()
585 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) in sh_cmt_start()
586 ret = sh_cmt_enable(ch); in sh_cmt_start()
590 ch->flags |= flag; in sh_cmt_start()
593 if (ch->cmt->num_channels == 1 && in sh_cmt_start()
594 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) in sh_cmt_start()
595 __sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_start()
597 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_start()
602 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) in sh_cmt_stop() argument
607 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_stop()
609 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); in sh_cmt_stop()
610 ch->flags &= ~flag; in sh_cmt_stop()
612 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) in sh_cmt_stop()
613 sh_cmt_disable(ch); in sh_cmt_stop()
616 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) in sh_cmt_stop()
617 __sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_stop()
619 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_stop()
629 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_read() local
632 if (ch->cmt->num_channels == 1) { in sh_cmt_clocksource_read()
637 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_clocksource_read()
638 value = ch->total_cycles; in sh_cmt_clocksource_read()
639 raw = sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clocksource_read()
642 raw += ch->match_value + 1; in sh_cmt_clocksource_read()
643 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_clocksource_read()
648 return sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clocksource_read()
654 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_enable() local
656 WARN_ON(ch->cs_enabled); in sh_cmt_clocksource_enable()
658 ch->total_cycles = 0; in sh_cmt_clocksource_enable()
660 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_enable()
662 ch->cs_enabled = true; in sh_cmt_clocksource_enable()
669 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_disable() local
671 WARN_ON(!ch->cs_enabled); in sh_cmt_clocksource_disable()
673 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_disable()
674 ch->cs_enabled = false; in sh_cmt_clocksource_disable()
679 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_suspend() local
681 if (!ch->cs_enabled) in sh_cmt_clocksource_suspend()
684 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_suspend()
685 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); in sh_cmt_clocksource_suspend()
690 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_resume() local
692 if (!ch->cs_enabled) in sh_cmt_clocksource_resume()
695 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); in sh_cmt_clocksource_resume()
696 sh_cmt_start(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_resume()
699 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, in sh_cmt_register_clocksource() argument
702 struct clocksource *cs = &ch->cs; in sh_cmt_register_clocksource()
704 cs->name = name; in sh_cmt_register_clocksource()
705 cs->rating = 125; in sh_cmt_register_clocksource()
706 cs->read = sh_cmt_clocksource_read; in sh_cmt_register_clocksource()
707 cs->enable = sh_cmt_clocksource_enable; in sh_cmt_register_clocksource()
708 cs->disable = sh_cmt_clocksource_disable; in sh_cmt_register_clocksource()
709 cs->suspend = sh_cmt_clocksource_suspend; in sh_cmt_register_clocksource()
710 cs->resume = sh_cmt_clocksource_resume; in sh_cmt_register_clocksource()
711 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); in sh_cmt_register_clocksource()
712 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; in sh_cmt_register_clocksource()
714 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", in sh_cmt_register_clocksource()
715 ch->index); in sh_cmt_register_clocksource()
717 clocksource_register_hz(cs, ch->cmt->rate); in sh_cmt_register_clocksource()
726 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) in sh_cmt_clock_event_start() argument
728 sh_cmt_start(ch, FLAG_CLOCKEVENT); in sh_cmt_clock_event_start()
731 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); in sh_cmt_clock_event_start()
733 sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_clock_event_start()
738 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_shutdown() local
740 sh_cmt_stop(ch, FLAG_CLOCKEVENT); in sh_cmt_clock_event_shutdown()
747 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_set_state() local
751 sh_cmt_stop(ch, FLAG_CLOCKEVENT); in sh_cmt_clock_event_set_state()
753 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", in sh_cmt_clock_event_set_state()
754 ch->index, periodic ? "periodic" : "oneshot"); in sh_cmt_clock_event_set_state()
755 sh_cmt_clock_event_start(ch, periodic); in sh_cmt_clock_event_set_state()
772 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_next() local
775 if (likely(ch->flags & FLAG_IRQCONTEXT)) in sh_cmt_clock_event_next()
776 ch->next_match_value = delta - 1; in sh_cmt_clock_event_next()
778 sh_cmt_set_next(ch, delta - 1); in sh_cmt_clock_event_next()
785 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_suspend() local
787 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); in sh_cmt_clock_event_suspend()
788 clk_unprepare(ch->cmt->clk); in sh_cmt_clock_event_suspend()
793 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_resume() local
795 clk_prepare(ch->cmt->clk); in sh_cmt_clock_event_resume()
796 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); in sh_cmt_clock_event_resume()
799 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, in sh_cmt_register_clockevent() argument
802 struct clock_event_device *ced = &ch->ced; in sh_cmt_register_clockevent()
806 irq = platform_get_irq(ch->cmt->pdev, ch->index); in sh_cmt_register_clockevent()
812 dev_name(&ch->cmt->pdev->dev), ch); in sh_cmt_register_clockevent()
814 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", in sh_cmt_register_clockevent()
815 ch->index, irq); in sh_cmt_register_clockevent()
819 ced->name = name; in sh_cmt_register_clockevent()
820 ced->features = CLOCK_EVT_FEAT_PERIODIC; in sh_cmt_register_clockevent()
821 ced->features |= CLOCK_EVT_FEAT_ONESHOT; in sh_cmt_register_clockevent()
822 ced->rating = 125; in sh_cmt_register_clockevent()
823 ced->cpumask = cpu_possible_mask; in sh_cmt_register_clockevent()
824 ced->set_next_event = sh_cmt_clock_event_next; in sh_cmt_register_clockevent()
825 ced->set_state_shutdown = sh_cmt_clock_event_shutdown; in sh_cmt_register_clockevent()
826 ced->set_state_periodic = sh_cmt_clock_event_set_periodic; in sh_cmt_register_clockevent()
827 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; in sh_cmt_register_clockevent()
828 ced->suspend = sh_cmt_clock_event_suspend; in sh_cmt_register_clockevent()
829 ced->resume = sh_cmt_clock_event_resume; in sh_cmt_register_clockevent()
832 ced->shift = 32; in sh_cmt_register_clockevent()
833 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); in sh_cmt_register_clockevent()
834 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); in sh_cmt_register_clockevent()
835 ced->max_delta_ticks = ch->max_match_value; in sh_cmt_register_clockevent()
836 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); in sh_cmt_register_clockevent()
837 ced->min_delta_ticks = 0x1f; in sh_cmt_register_clockevent()
839 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", in sh_cmt_register_clockevent()
840 ch->index); in sh_cmt_register_clockevent()
846 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, in sh_cmt_register() argument
852 ch->cmt->has_clockevent = true; in sh_cmt_register()
853 ret = sh_cmt_register_clockevent(ch, name); in sh_cmt_register()
859 ch->cmt->has_clocksource = true; in sh_cmt_register()
860 sh_cmt_register_clocksource(ch, name); in sh_cmt_register()
866 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, in sh_cmt_setup_channel() argument
877 ch->cmt = cmt; in sh_cmt_setup_channel()
878 ch->index = index; in sh_cmt_setup_channel()
879 ch->hwidx = hwidx; in sh_cmt_setup_channel()
880 ch->timer_bit = hwidx; in sh_cmt_setup_channel()
884 * timers with a per-channel start/stop register, compute its address in sh_cmt_setup_channel()
887 switch (cmt->info->model) { in sh_cmt_setup_channel()
889 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; in sh_cmt_setup_channel()
893 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; in sh_cmt_setup_channel()
897 ch->iostart = cmt->mapbase + ch->hwidx * 0x100; in sh_cmt_setup_channel()
898 ch->ioctrl = ch->iostart + 0x10; in sh_cmt_setup_channel()
899 ch->timer_bit = 0; in sh_cmt_setup_channel()
902 value = ioread32(cmt->mapbase + CMCLKE); in sh_cmt_setup_channel()
904 iowrite32(value, cmt->mapbase + CMCLKE); in sh_cmt_setup_channel()
908 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) in sh_cmt_setup_channel()
909 ch->max_match_value = ~0; in sh_cmt_setup_channel()
911 ch->max_match_value = (1 << cmt->info->width) - 1; in sh_cmt_setup_channel()
913 ch->match_value = ch->max_match_value; in sh_cmt_setup_channel()
914 raw_spin_lock_init(&ch->lock); in sh_cmt_setup_channel()
916 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), in sh_cmt_setup_channel()
919 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", in sh_cmt_setup_channel()
920 ch->index); in sh_cmt_setup_channel()
923 ch->cs_enabled = false; in sh_cmt_setup_channel()
932 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); in sh_cmt_map_memory()
934 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); in sh_cmt_map_memory()
935 return -ENXIO; in sh_cmt_map_memory()
938 cmt->mapbase = ioremap(mem->start, resource_size(mem)); in sh_cmt_map_memory()
939 if (cmt->mapbase == NULL) { in sh_cmt_map_memory()
940 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); in sh_cmt_map_memory()
941 return -ENXIO; in sh_cmt_map_memory()
948 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
949 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
957 .compatible = "renesas,cmt-48",
962 .compatible = "renesas,cmt-48-gen2",
966 .compatible = "renesas,r8a7740-cmt1",
970 .compatible = "renesas,sh73a0-cmt1",
974 .compatible = "renesas,rcar-gen2-cmt0",
978 .compatible = "renesas,rcar-gen2-cmt1",
982 .compatible = "renesas,rcar-gen3-cmt0",
986 .compatible = "renesas,rcar-gen3-cmt1",
999 cmt->pdev = pdev; in sh_cmt_setup()
1000 raw_spin_lock_init(&cmt->lock); in sh_cmt_setup()
1002 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { in sh_cmt_setup()
1003 cmt->info = of_device_get_match_data(&pdev->dev); in sh_cmt_setup()
1004 cmt->hw_channels = cmt->info->channels_mask; in sh_cmt_setup()
1005 } else if (pdev->dev.platform_data) { in sh_cmt_setup()
1006 struct sh_timer_config *cfg = pdev->dev.platform_data; in sh_cmt_setup()
1007 const struct platform_device_id *id = pdev->id_entry; in sh_cmt_setup()
1009 cmt->info = (const struct sh_cmt_info *)id->driver_data; in sh_cmt_setup()
1010 cmt->hw_channels = cfg->channels_mask; in sh_cmt_setup()
1012 dev_err(&cmt->pdev->dev, "missing platform data\n"); in sh_cmt_setup()
1013 return -ENXIO; in sh_cmt_setup()
1017 cmt->clk = clk_get(&cmt->pdev->dev, "fck"); in sh_cmt_setup()
1018 if (IS_ERR(cmt->clk)) { in sh_cmt_setup()
1019 dev_err(&cmt->pdev->dev, "cannot get clock\n"); in sh_cmt_setup()
1020 return PTR_ERR(cmt->clk); in sh_cmt_setup()
1023 ret = clk_prepare(cmt->clk); in sh_cmt_setup()
1028 ret = clk_enable(cmt->clk); in sh_cmt_setup()
1032 rate = clk_get_rate(cmt->clk); in sh_cmt_setup()
1034 ret = -EINVAL; in sh_cmt_setup()
1039 if (cmt->info->model >= SH_CMT_48BIT) in sh_cmt_setup()
1040 cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate); in sh_cmt_setup()
1041 cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8); in sh_cmt_setup()
1049 cmt->num_channels = hweight8(cmt->hw_channels); in sh_cmt_setup()
1050 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), in sh_cmt_setup()
1052 if (cmt->channels == NULL) { in sh_cmt_setup()
1053 ret = -ENOMEM; in sh_cmt_setup()
1061 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { in sh_cmt_setup()
1062 unsigned int hwidx = ffs(mask) - 1; in sh_cmt_setup()
1063 bool clocksource = i == 1 || cmt->num_channels == 1; in sh_cmt_setup()
1066 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, in sh_cmt_setup()
1074 clk_disable(cmt->clk); in sh_cmt_setup()
1081 kfree(cmt->channels); in sh_cmt_setup()
1082 iounmap(cmt->mapbase); in sh_cmt_setup()
1084 clk_disable(cmt->clk); in sh_cmt_setup()
1086 clk_unprepare(cmt->clk); in sh_cmt_setup()
1088 clk_put(cmt->clk); in sh_cmt_setup()
1098 pm_runtime_set_active(&pdev->dev); in sh_cmt_probe()
1099 pm_runtime_enable(&pdev->dev); in sh_cmt_probe()
1103 dev_info(&pdev->dev, "kept as earlytimer\n"); in sh_cmt_probe()
1109 return -ENOMEM; in sh_cmt_probe()
1114 pm_runtime_idle(&pdev->dev); in sh_cmt_probe()
1121 if (cmt->has_clockevent || cmt->has_clocksource) in sh_cmt_probe()
1122 pm_runtime_irq_safe(&pdev->dev); in sh_cmt_probe()
1124 pm_runtime_idle(&pdev->dev); in sh_cmt_probe()
1131 return -EBUSY; /* cannot unregister clockevent and clocksource */ in sh_cmt_remove()