74 	void __iomem *base_addr;  member
115 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
117 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
119 	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);  in ttc_set_interval()
127 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
144 	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);  in ttc_clock_event_interrupt()
160 	return (u64)readl_relaxed(timer->base_addr +  in __ttc_clocksource_read()
198 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_shutdown()
200 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_shutdown()
220 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_resume()
222 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_resume()
265 			readl_relaxed(ttccs->ttc.base_addr +  in ttc_rate_change_clocksource_cb()
291 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
301 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
311 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
349 	ttccs->ttc.base_addr = base;  in ttc_setup_clocksource()
361 	writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);  in ttc_setup_clocksource()
363 		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_setup_clocksource()
365 		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_setup_clocksource()
432 	ttcce->ttc.base_addr = base;  in ttc_setup_clockevent()
449 	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_setup_clockevent()
451 		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_setup_clockevent()
452 	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);  in ttc_setup_clockevent()