Lines Matching refs:tdc
177 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
241 static inline void tdc_write(struct tegra_dma_channel *tdc, in tdc_write() argument
244 writel(val, tdc->chan_addr + reg); in tdc_write()
247 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg) in tdc_read() argument
249 return readl(tdc->chan_addr + reg); in tdc_read()
263 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc) in tdc2dev() argument
265 return &tdc->dma_chan.dev->device; in tdc2dev()
271 static struct tegra_dma_desc *tegra_dma_desc_get(struct tegra_dma_channel *tdc) in tegra_dma_desc_get() argument
276 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_desc_get()
279 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { in tegra_dma_desc_get()
282 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_get()
288 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_get()
295 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan); in tegra_dma_desc_get()
302 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc, in tegra_dma_desc_put() argument
307 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_desc_put()
309 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req); in tegra_dma_desc_put()
310 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in tegra_dma_desc_put()
311 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_put()
315 tegra_dma_sg_req_get(struct tegra_dma_channel *tdc) in tegra_dma_sg_req_get() argument
320 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_sg_req_get()
321 if (!list_empty(&tdc->free_sg_req)) { in tegra_dma_sg_req_get()
322 sg_req = list_first_entry(&tdc->free_sg_req, typeof(*sg_req), in tegra_dma_sg_req_get()
325 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_sg_req_get()
328 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_sg_req_get()
338 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_slave_config() local
340 if (!list_empty(&tdc->pending_sg_req)) { in tegra_dma_slave_config()
341 dev_err(tdc2dev(tdc), "Configuration not allowed\n"); in tegra_dma_slave_config()
345 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); in tegra_dma_slave_config()
346 if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID && in tegra_dma_slave_config()
350 tdc->slave_id = sconfig->slave_id; in tegra_dma_slave_config()
352 tdc->config_init = true; in tegra_dma_slave_config()
357 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc, in tegra_dma_global_pause() argument
360 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_global_pause()
364 if (tdc->tdma->global_pause_count == 0) { in tegra_dma_global_pause()
370 tdc->tdma->global_pause_count++; in tegra_dma_global_pause()
375 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc) in tegra_dma_global_resume() argument
377 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_global_resume()
381 if (WARN_ON(tdc->tdma->global_pause_count == 0)) in tegra_dma_global_resume()
384 if (--tdc->tdma->global_pause_count == 0) in tegra_dma_global_resume()
392 static void tegra_dma_pause(struct tegra_dma_channel *tdc, in tegra_dma_pause() argument
395 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_pause()
398 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, in tegra_dma_pause()
403 tegra_dma_global_pause(tdc, wait_for_burst_complete); in tegra_dma_pause()
407 static void tegra_dma_resume(struct tegra_dma_channel *tdc) in tegra_dma_resume() argument
409 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_resume()
412 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0); in tegra_dma_resume()
414 tegra_dma_global_resume(tdc); in tegra_dma_resume()
417 static void tegra_dma_stop(struct tegra_dma_channel *tdc) in tegra_dma_stop() argument
422 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR); in tegra_dma_stop()
424 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); in tegra_dma_stop()
428 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); in tegra_dma_stop()
431 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_stop()
433 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); in tegra_dma_stop()
434 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status); in tegra_dma_stop()
436 tdc->busy = false; in tegra_dma_stop()
439 static void tegra_dma_start(struct tegra_dma_channel *tdc, in tegra_dma_start() argument
444 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
445 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq); in tegra_dma_start()
446 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr); in tegra_dma_start()
447 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq); in tegra_dma_start()
448 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr); in tegra_dma_start()
449 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_start()
450 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_start()
453 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, in tegra_dma_start()
457 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc, in tegra_dma_configure_for_next() argument
473 tegra_dma_pause(tdc, false); in tegra_dma_configure_for_next()
474 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_configure_for_next()
481 dev_err(tdc2dev(tdc), in tegra_dma_configure_for_next()
483 tegra_dma_resume(tdc); in tegra_dma_configure_for_next()
488 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr); in tegra_dma_configure_for_next()
489 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr); in tegra_dma_configure_for_next()
490 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_configure_for_next()
491 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, in tegra_dma_configure_for_next()
493 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, in tegra_dma_configure_for_next()
498 tegra_dma_resume(tdc); in tegra_dma_configure_for_next()
501 static void tdc_start_head_req(struct tegra_dma_channel *tdc) in tdc_start_head_req() argument
505 sg_req = list_first_entry(&tdc->pending_sg_req, typeof(*sg_req), node); in tdc_start_head_req()
506 tegra_dma_start(tdc, sg_req); in tdc_start_head_req()
509 tdc->busy = true; in tdc_start_head_req()
512 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc) in tdc_configure_next_head_desc() argument
516 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node); in tdc_configure_next_head_desc()
517 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) { in tdc_configure_next_head_desc()
520 tegra_dma_configure_for_next(tdc, hnsgreq); in tdc_configure_next_head_desc()
525 get_current_xferred_count(struct tegra_dma_channel *tdc, in get_current_xferred_count() argument
532 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc) in tegra_dma_abort_all() argument
537 while (!list_empty(&tdc->pending_sg_req)) { in tegra_dma_abort_all()
538 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), in tegra_dma_abort_all()
540 list_move_tail(&sgreq->node, &tdc->free_sg_req); in tegra_dma_abort_all()
544 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in tegra_dma_abort_all()
549 &tdc->cb_desc); in tegra_dma_abort_all()
553 tdc->isr_handler = NULL; in tegra_dma_abort_all()
556 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc, in handle_continuous_head_request() argument
566 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node); in handle_continuous_head_request()
568 tegra_dma_stop(tdc); in handle_continuous_head_request()
569 pm_runtime_put(tdc->tdma->dev); in handle_continuous_head_request()
570 dev_err(tdc2dev(tdc), "DMA transfer underflow, aborting DMA\n"); in handle_continuous_head_request()
571 tegra_dma_abort_all(tdc); in handle_continuous_head_request()
577 tdc_configure_next_head_desc(tdc); in handle_continuous_head_request()
582 static void handle_once_dma_done(struct tegra_dma_channel *tdc, in handle_once_dma_done() argument
588 tdc->busy = false; in handle_once_dma_done()
589 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node); in handle_once_dma_done()
598 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); in handle_once_dma_done()
600 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in handle_once_dma_done()
602 list_add_tail(&sgreq->node, &tdc->free_sg_req); in handle_once_dma_done()
608 if (list_empty(&tdc->pending_sg_req)) { in handle_once_dma_done()
609 pm_runtime_put(tdc->tdma->dev); in handle_once_dma_done()
613 tdc_start_head_req(tdc); in handle_once_dma_done()
616 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc, in handle_cont_sngl_cycle_dma_done() argument
623 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node); in handle_cont_sngl_cycle_dma_done()
632 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); in handle_cont_sngl_cycle_dma_done()
638 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) { in handle_cont_sngl_cycle_dma_done()
639 list_move_tail(&sgreq->node, &tdc->pending_sg_req); in handle_cont_sngl_cycle_dma_done()
641 st = handle_continuous_head_request(tdc, to_terminate); in handle_cont_sngl_cycle_dma_done()
649 struct tegra_dma_channel *tdc = from_tasklet(tdc, t, tasklet); in tegra_dma_tasklet() local
655 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tasklet()
656 while (!list_empty(&tdc->cb_desc)) { in tegra_dma_tasklet()
657 dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc), in tegra_dma_tasklet()
663 trace_tegra_dma_complete_cb(&tdc->dma_chan, cb_count, in tegra_dma_tasklet()
665 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tasklet()
668 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tasklet()
670 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tasklet()
675 struct tegra_dma_channel *tdc = dev_id; in tegra_dma_isr() local
678 spin_lock(&tdc->lock); in tegra_dma_isr()
680 trace_tegra_dma_isr(&tdc->dma_chan, irq); in tegra_dma_isr()
681 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_isr()
683 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status); in tegra_dma_isr()
684 tdc->isr_handler(tdc, false); in tegra_dma_isr()
685 tasklet_schedule(&tdc->tasklet); in tegra_dma_isr()
686 wake_up_all(&tdc->wq); in tegra_dma_isr()
687 spin_unlock(&tdc->lock); in tegra_dma_isr()
691 spin_unlock(&tdc->lock); in tegra_dma_isr()
692 dev_info(tdc2dev(tdc), "Interrupt already served status 0x%08x\n", in tegra_dma_isr()
701 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan); in tegra_dma_tx_submit() local
705 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tx_submit()
708 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req); in tegra_dma_tx_submit()
709 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tx_submit()
716 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_issue_pending() local
720 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_issue_pending()
721 if (list_empty(&tdc->pending_sg_req)) { in tegra_dma_issue_pending()
722 dev_err(tdc2dev(tdc), "No DMA request\n"); in tegra_dma_issue_pending()
725 if (!tdc->busy) { in tegra_dma_issue_pending()
726 err = pm_runtime_resume_and_get(tdc->tdma->dev); in tegra_dma_issue_pending()
728 dev_err(tdc2dev(tdc), "Failed to enable DMA\n"); in tegra_dma_issue_pending()
732 tdc_start_head_req(tdc); in tegra_dma_issue_pending()
735 if (tdc->cyclic) { in tegra_dma_issue_pending()
741 tdc_configure_next_head_desc(tdc); in tegra_dma_issue_pending()
745 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_issue_pending()
750 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_terminate_all() local
757 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_terminate_all()
759 if (!tdc->busy) in tegra_dma_terminate_all()
763 tegra_dma_pause(tdc, true); in tegra_dma_terminate_all()
765 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_terminate_all()
767 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__); in tegra_dma_terminate_all()
768 tdc->isr_handler(tdc, true); in tegra_dma_terminate_all()
769 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_terminate_all()
771 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_terminate_all()
772 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER); in tegra_dma_terminate_all()
776 was_busy = tdc->busy; in tegra_dma_terminate_all()
777 tegra_dma_stop(tdc); in tegra_dma_terminate_all()
779 if (!list_empty(&tdc->pending_sg_req) && was_busy) { in tegra_dma_terminate_all()
780 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), in tegra_dma_terminate_all()
783 get_current_xferred_count(tdc, sgreq, wcount); in tegra_dma_terminate_all()
785 tegra_dma_resume(tdc); in tegra_dma_terminate_all()
787 pm_runtime_put(tdc->tdma->dev); in tegra_dma_terminate_all()
788 wake_up_all(&tdc->wq); in tegra_dma_terminate_all()
791 tegra_dma_abort_all(tdc); in tegra_dma_terminate_all()
793 while (!list_empty(&tdc->cb_desc)) { in tegra_dma_terminate_all()
794 dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc), in tegra_dma_terminate_all()
799 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_terminate_all()
804 static bool tegra_dma_eoc_interrupt_deasserted(struct tegra_dma_channel *tdc) in tegra_dma_eoc_interrupt_deasserted() argument
809 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_eoc_interrupt_deasserted()
810 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_eoc_interrupt_deasserted()
811 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_eoc_interrupt_deasserted()
818 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_synchronize() local
821 err = pm_runtime_resume_and_get(tdc->tdma->dev); in tegra_dma_synchronize()
823 dev_err(tdc2dev(tdc), "Failed to synchronize DMA: %d\n", err); in tegra_dma_synchronize()
832 wait_event(tdc->wq, tegra_dma_eoc_interrupt_deasserted(tdc)); in tegra_dma_synchronize()
834 tasklet_kill(&tdc->tasklet); in tegra_dma_synchronize()
836 pm_runtime_put(tdc->tdma->dev); in tegra_dma_synchronize()
839 static unsigned int tegra_dma_sg_bytes_xferred(struct tegra_dma_channel *tdc, in tegra_dma_sg_bytes_xferred() argument
844 if (!list_is_first(&sg_req->node, &tdc->pending_sg_req)) in tegra_dma_sg_bytes_xferred()
847 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_sg_bytes_xferred()
848 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER); in tegra_dma_sg_bytes_xferred()
850 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_sg_bytes_xferred()
852 if (!tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_sg_bytes_xferred()
858 wcount = get_current_xferred_count(tdc, sg_req, wcount); in tegra_dma_sg_bytes_xferred()
902 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_tx_status() local
914 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tx_status()
917 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { in tegra_dma_tx_status()
925 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) { in tegra_dma_tx_status()
928 bytes = tegra_dma_sg_bytes_xferred(tdc, sg_req); in tegra_dma_tx_status()
934 dev_dbg(tdc2dev(tdc), "cookie %d not found\n", cookie); in tegra_dma_tx_status()
945 trace_tegra_dma_tx_status(&tdc->dma_chan, cookie, txstate); in tegra_dma_tx_status()
946 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tx_status()
951 static inline unsigned int get_bus_width(struct tegra_dma_channel *tdc, in get_bus_width() argument
964 dev_warn(tdc2dev(tdc), in get_bus_width()
970 static inline unsigned int get_burst_size(struct tegra_dma_channel *tdc, in get_burst_size() argument
1001 static int get_transfer_param(struct tegra_dma_channel *tdc, in get_transfer_param() argument
1011 *apb_addr = tdc->dma_sconfig.dst_addr; in get_transfer_param()
1012 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); in get_transfer_param()
1013 *burst_size = tdc->dma_sconfig.dst_maxburst; in get_transfer_param()
1014 *slave_bw = tdc->dma_sconfig.dst_addr_width; in get_transfer_param()
1019 *apb_addr = tdc->dma_sconfig.src_addr; in get_transfer_param()
1020 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); in get_transfer_param()
1021 *burst_size = tdc->dma_sconfig.src_maxburst; in get_transfer_param()
1022 *slave_bw = tdc->dma_sconfig.src_addr_width; in get_transfer_param()
1027 dev_err(tdc2dev(tdc), "DMA direction is not supported\n"); in get_transfer_param()
1034 static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc, in tegra_dma_prep_wcount() argument
1040 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_prep_wcount()
1054 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_slave_sg() local
1064 if (!tdc->config_init) { in tegra_dma_prep_slave_sg()
1065 dev_err(tdc2dev(tdc), "DMA channel is not configured\n"); in tegra_dma_prep_slave_sg()
1069 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len); in tegra_dma_prep_slave_sg()
1073 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr, in tegra_dma_prep_slave_sg()
1086 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) { in tegra_dma_prep_slave_sg()
1088 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; in tegra_dma_prep_slave_sg()
1100 dma_desc = tegra_dma_desc_get(tdc); in tegra_dma_prep_slave_sg()
1102 dev_err(tdc2dev(tdc), "DMA descriptors not available\n"); in tegra_dma_prep_slave_sg()
1120 len > tdc->tdma->chip_data->max_dma_count) { in tegra_dma_prep_slave_sg()
1121 dev_err(tdc2dev(tdc), in tegra_dma_prep_slave_sg()
1123 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_slave_sg()
1127 sg_req = tegra_dma_sg_req_get(tdc); in tegra_dma_prep_slave_sg()
1129 dev_err(tdc2dev(tdc), "DMA sg-req not available\n"); in tegra_dma_prep_slave_sg()
1130 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_slave_sg()
1134 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len); in tegra_dma_prep_slave_sg()
1140 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len); in tegra_dma_prep_slave_sg()
1158 if (!tdc->isr_handler) { in tegra_dma_prep_slave_sg()
1159 tdc->isr_handler = handle_once_dma_done; in tegra_dma_prep_slave_sg()
1160 tdc->cyclic = false; in tegra_dma_prep_slave_sg()
1162 if (tdc->cyclic) { in tegra_dma_prep_slave_sg()
1163 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n"); in tegra_dma_prep_slave_sg()
1164 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_slave_sg()
1179 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_cyclic() local
1189 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n"); in tegra_dma_prep_dma_cyclic()
1193 if (!tdc->config_init) { in tegra_dma_prep_dma_cyclic()
1194 dev_err(tdc2dev(tdc), "DMA slave is not configured\n"); in tegra_dma_prep_dma_cyclic()
1204 if (tdc->busy) { in tegra_dma_prep_dma_cyclic()
1205 dev_err(tdc2dev(tdc), "Request not allowed when DMA running\n"); in tegra_dma_prep_dma_cyclic()
1214 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n"); in tegra_dma_prep_dma_cyclic()
1220 len > tdc->tdma->chip_data->max_dma_count) { in tegra_dma_prep_dma_cyclic()
1221 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n"); in tegra_dma_prep_dma_cyclic()
1225 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr, in tegra_dma_prep_dma_cyclic()
1234 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) { in tegra_dma_prep_dma_cyclic()
1236 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; in tegra_dma_prep_dma_cyclic()
1248 dma_desc = tegra_dma_desc_get(tdc); in tegra_dma_prep_dma_cyclic()
1250 dev_err(tdc2dev(tdc), "not enough descriptors available\n"); in tegra_dma_prep_dma_cyclic()
1264 sg_req = tegra_dma_sg_req_get(tdc); in tegra_dma_prep_dma_cyclic()
1266 dev_err(tdc2dev(tdc), "DMA sg-req not available\n"); in tegra_dma_prep_dma_cyclic()
1267 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_dma_cyclic()
1271 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len); in tegra_dma_prep_dma_cyclic()
1275 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len); in tegra_dma_prep_dma_cyclic()
1295 if (!tdc->isr_handler) { in tegra_dma_prep_dma_cyclic()
1296 tdc->isr_handler = handle_cont_sngl_cycle_dma_done; in tegra_dma_prep_dma_cyclic()
1297 tdc->cyclic = true; in tegra_dma_prep_dma_cyclic()
1299 if (!tdc->cyclic) { in tegra_dma_prep_dma_cyclic()
1300 dev_err(tdc2dev(tdc), "DMA configuration conflict\n"); in tegra_dma_prep_dma_cyclic()
1301 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_dma_cyclic()
1311 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_alloc_chan_resources() local
1313 dma_cookie_init(&tdc->dma_chan); in tegra_dma_alloc_chan_resources()
1320 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_free_chan_resources() local
1329 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); in tegra_dma_free_chan_resources()
1332 tasklet_kill(&tdc->tasklet); in tegra_dma_free_chan_resources()
1334 list_splice_init(&tdc->pending_sg_req, &sg_req_list); in tegra_dma_free_chan_resources()
1335 list_splice_init(&tdc->free_sg_req, &sg_req_list); in tegra_dma_free_chan_resources()
1336 list_splice_init(&tdc->free_dma_desc, &dma_desc_list); in tegra_dma_free_chan_resources()
1337 INIT_LIST_HEAD(&tdc->cb_desc); in tegra_dma_free_chan_resources()
1338 tdc->config_init = false; in tegra_dma_free_chan_resources()
1339 tdc->isr_handler = NULL; in tegra_dma_free_chan_resources()
1354 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID; in tegra_dma_free_chan_resources()
1361 struct tegra_dma_channel *tdc; in tegra_dma_of_xlate() local
1373 tdc = to_tegra_dma_chan(chan); in tegra_dma_of_xlate()
1374 tdc->slave_id = dma_spec->args[0]; in tegra_dma_of_xlate()
1495 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe() local
1498 tdc->chan_addr = tdma->base_addr + in tegra_dma_probe()
1508 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i); in tegra_dma_probe()
1510 tdc->name, tdc); in tegra_dma_probe()
1518 tdc->dma_chan.device = &tdma->dma_dev; in tegra_dma_probe()
1519 dma_cookie_init(&tdc->dma_chan); in tegra_dma_probe()
1520 list_add_tail(&tdc->dma_chan.device_node, in tegra_dma_probe()
1522 tdc->tdma = tdma; in tegra_dma_probe()
1523 tdc->id = i; in tegra_dma_probe()
1524 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID; in tegra_dma_probe()
1526 tasklet_setup(&tdc->tasklet, tegra_dma_tasklet); in tegra_dma_probe()
1527 spin_lock_init(&tdc->lock); in tegra_dma_probe()
1528 init_waitqueue_head(&tdc->wq); in tegra_dma_probe()
1530 INIT_LIST_HEAD(&tdc->pending_sg_req); in tegra_dma_probe()
1531 INIT_LIST_HEAD(&tdc->free_sg_req); in tegra_dma_probe()
1532 INIT_LIST_HEAD(&tdc->free_dma_desc); in tegra_dma_probe()
1533 INIT_LIST_HEAD(&tdc->cb_desc); in tegra_dma_probe()
1632 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_dev_suspend() local
1634 tasklet_kill(&tdc->tasklet); in tegra_dma_dev_suspend()
1636 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_dev_suspend()
1637 busy = tdc->busy; in tegra_dma_dev_suspend()
1638 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_dev_suspend()