Lines Matching refs:pvt
89 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
93 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
94 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
96 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
113 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
116 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
129 if (dct_ganging_enabled(pvt)) in amd64_read_dct_pci_cfg()
141 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
142 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
153 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
170 static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval) in __f17h_set_scrubval() argument
179 pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF); in __f17h_set_scrubval()
180 pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1); in __f17h_set_scrubval()
182 pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1); in __f17h_set_scrubval()
189 static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) in __set_scrub_rate() argument
217 if (pvt->umc) { in __set_scrub_rate()
218 __f17h_set_scrubval(pvt, scrubval); in __set_scrub_rate()
219 } else if (pvt->fam == 0x15 && pvt->model == 0x60) { in __set_scrub_rate()
220 f15h_select_dct(pvt, 0); in __set_scrub_rate()
221 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
222 f15h_select_dct(pvt, 1); in __set_scrub_rate()
223 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
225 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
236 struct amd64_pvt *pvt = mci->pvt_info; in set_scrub_rate() local
239 if (pvt->fam == 0xf) in set_scrub_rate()
242 if (pvt->fam == 0x15) { in set_scrub_rate()
244 if (pvt->model < 0x10) in set_scrub_rate()
245 f15h_select_dct(pvt, 0); in set_scrub_rate()
247 if (pvt->model == 0x60) in set_scrub_rate()
250 return __set_scrub_rate(pvt, bw, min_scrubrate); in set_scrub_rate()
255 struct amd64_pvt *pvt = mci->pvt_info; in get_scrub_rate() local
259 if (pvt->umc) { in get_scrub_rate()
260 amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval); in get_scrub_rate()
262 amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval); in get_scrub_rate()
268 } else if (pvt->fam == 0x15) { in get_scrub_rate()
270 if (pvt->model < 0x10) in get_scrub_rate()
271 f15h_select_dct(pvt, 0); in get_scrub_rate()
273 if (pvt->model == 0x60) in get_scrub_rate()
274 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); in get_scrub_rate()
276 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
278 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
296 static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid) in base_limit_match() argument
308 return ((addr >= get_dram_base(pvt, nid)) && in base_limit_match()
309 (addr <= get_dram_limit(pvt, nid))); in base_limit_match()
321 struct amd64_pvt *pvt; in find_mc_by_sys_addr() local
329 pvt = mci->pvt_info; in find_mc_by_sys_addr()
336 intlv_en = dram_intlv_en(pvt, 0); in find_mc_by_sys_addr()
340 if (base_limit_match(pvt, sys_addr, node_id)) in find_mc_by_sys_addr()
356 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) in find_mc_by_sys_addr()
364 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) { in find_mc_by_sys_addr()
385 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, in get_cs_base_and_mask() argument
391 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in get_cs_base_and_mask()
392 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
393 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
402 } else if (pvt->fam == 0x16 || in get_cs_base_and_mask()
403 (pvt->fam == 0x15 && pvt->model >= 0x30)) { in get_cs_base_and_mask()
404 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
405 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
420 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
421 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
424 if (pvt->fam == 0x15) in get_cs_base_and_mask()
441 #define for_each_chip_select(i, dct, pvt) \ argument
442 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
444 #define chip_select_base(i, dct, pvt) \ argument
445 pvt->csels[dct].csbases[i]
447 #define for_each_chip_select_mask(i, dct, pvt) \ argument
448 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
459 struct amd64_pvt *pvt; in input_addr_to_csrow() local
463 pvt = mci->pvt_info; in input_addr_to_csrow()
465 for_each_chip_select(csrow, 0, pvt) { in input_addr_to_csrow()
466 if (!csrow_enabled(csrow, 0, pvt)) in input_addr_to_csrow()
469 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); in input_addr_to_csrow()
476 pvt->mc_node_id); in input_addr_to_csrow()
482 (unsigned long)input_addr, pvt->mc_node_id); in input_addr_to_csrow()
506 struct amd64_pvt *pvt = mci->pvt_info; in amd64_get_dram_hole_info() local
509 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { in amd64_get_dram_hole_info()
511 pvt->ext_model, pvt->mc_node_id); in amd64_get_dram_hole_info()
516 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { in amd64_get_dram_hole_info()
521 if (!dhar_valid(pvt)) { in amd64_get_dram_hole_info()
523 pvt->mc_node_id); in amd64_get_dram_hole_info()
545 *hole_base = dhar_base(pvt); in amd64_get_dram_hole_info()
548 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) in amd64_get_dram_hole_info()
549 : k8_dhar_offset(pvt); in amd64_get_dram_hole_info()
552 pvt->mc_node_id, (unsigned long)*hole_base, in amd64_get_dram_hole_info()
590 struct amd64_pvt *pvt = mci->pvt_info; in sys_addr_to_dram_addr() local
594 dram_base = get_dram_base(pvt, pvt->mc_node_id); in sys_addr_to_dram_addr()
646 struct amd64_pvt *pvt; in dram_addr_to_input_addr() local
650 pvt = mci->pvt_info; in dram_addr_to_input_addr()
656 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); in dram_addr_to_input_addr()
718 static unsigned long determine_edac_cap(struct amd64_pvt *pvt) in determine_edac_cap() argument
723 if (pvt->umc) { in determine_edac_cap()
727 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in determine_edac_cap()
733 if (pvt->umc[i].umc_cfg & BIT(12)) in determine_edac_cap()
740 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) in determine_edac_cap()
744 if (pvt->dclr0 & BIT(bit)) in determine_edac_cap()
753 static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) in debug_dump_dramcfg_low() argument
757 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
758 u32 dcsm = pvt->csels[chan].csmasks[0]; in debug_dump_dramcfg_low()
774 if (pvt->fam == 0x10) in debug_dump_dramcfg_low()
794 static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) in f17_get_cs_mode() argument
799 if (csrow_enabled(2 * dimm, ctrl, pvt)) in f17_get_cs_mode()
802 if (csrow_enabled(2 * dimm + 1, ctrl, pvt)) in f17_get_cs_mode()
806 if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt)) in f17_get_cs_mode()
814 for_each_chip_select(base, ctrl, pvt) in f17_get_cs_mode()
815 count += csrow_enabled(base, ctrl, pvt); in f17_get_cs_mode()
818 pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) { in f17_get_cs_mode()
826 static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl) in debug_display_dimm_sizes_df() argument
836 cs_mode = f17_get_cs_mode(dimm, ctrl, pvt); in debug_display_dimm_sizes_df()
838 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0); in debug_display_dimm_sizes_df()
839 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1); in debug_display_dimm_sizes_df()
847 static void __dump_misc_regs_df(struct amd64_pvt *pvt) in __dump_misc_regs_df() argument
854 umc = &pvt->umc[i]; in __dump_misc_regs_df()
861 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp); in __dump_misc_regs_df()
864 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp); in __dump_misc_regs_df()
878 if (pvt->dram_type == MEM_LRDDR4) { in __dump_misc_regs_df()
879 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp); in __dump_misc_regs_df()
884 debug_display_dimm_sizes_df(pvt, i); in __dump_misc_regs_df()
888 pvt->dhar, dhar_base(pvt)); in __dump_misc_regs_df()
892 static void __dump_misc_regs(struct amd64_pvt *pvt) in __dump_misc_regs() argument
894 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); in __dump_misc_regs()
897 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); in __dump_misc_regs()
900 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", in __dump_misc_regs()
901 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); in __dump_misc_regs()
903 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in __dump_misc_regs()
905 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); in __dump_misc_regs()
908 pvt->dhar, dhar_base(pvt), in __dump_misc_regs()
909 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) in __dump_misc_regs()
910 : f10_dhar_offset(pvt)); in __dump_misc_regs()
912 debug_display_dimm_sizes(pvt, 0); in __dump_misc_regs()
915 if (pvt->fam == 0xf) in __dump_misc_regs()
918 debug_display_dimm_sizes(pvt, 1); in __dump_misc_regs()
921 if (!dct_ganging_enabled(pvt)) in __dump_misc_regs()
922 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); in __dump_misc_regs()
926 static void dump_misc_regs(struct amd64_pvt *pvt) in dump_misc_regs() argument
928 if (pvt->umc) in dump_misc_regs()
929 __dump_misc_regs_df(pvt); in dump_misc_regs()
931 __dump_misc_regs(pvt); in dump_misc_regs()
933 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); in dump_misc_regs()
935 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); in dump_misc_regs()
941 static void prep_chip_selects(struct amd64_pvt *pvt) in prep_chip_selects() argument
943 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in prep_chip_selects()
944 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
945 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; in prep_chip_selects()
946 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { in prep_chip_selects()
947 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; in prep_chip_selects()
948 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; in prep_chip_selects()
949 } else if (pvt->fam >= 0x17) { in prep_chip_selects()
953 pvt->csels[umc].b_cnt = 4; in prep_chip_selects()
954 pvt->csels[umc].m_cnt = 2; in prep_chip_selects()
958 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
959 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; in prep_chip_selects()
963 static void read_umc_base_mask(struct amd64_pvt *pvt) in read_umc_base_mask() argument
977 for_each_chip_select(cs, umc, pvt) { in read_umc_base_mask()
978 base = &pvt->csels[umc].csbases[cs]; in read_umc_base_mask()
979 base_sec = &pvt->csels[umc].csbases_sec[cs]; in read_umc_base_mask()
984 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) in read_umc_base_mask()
988 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec)) in read_umc_base_mask()
996 for_each_chip_select_mask(cs, umc, pvt) { in read_umc_base_mask()
997 mask = &pvt->csels[umc].csmasks[cs]; in read_umc_base_mask()
998 mask_sec = &pvt->csels[umc].csmasks_sec[cs]; in read_umc_base_mask()
1003 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) in read_umc_base_mask()
1007 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec)) in read_umc_base_mask()
1017 static void read_dct_base_mask(struct amd64_pvt *pvt) in read_dct_base_mask() argument
1021 prep_chip_selects(pvt); in read_dct_base_mask()
1023 if (pvt->umc) in read_dct_base_mask()
1024 return read_umc_base_mask(pvt); in read_dct_base_mask()
1026 for_each_chip_select(cs, 0, pvt) { in read_dct_base_mask()
1029 u32 *base0 = &pvt->csels[0].csbases[cs]; in read_dct_base_mask()
1030 u32 *base1 = &pvt->csels[1].csbases[cs]; in read_dct_base_mask()
1032 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0)) in read_dct_base_mask()
1036 if (pvt->fam == 0xf) in read_dct_base_mask()
1039 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1)) in read_dct_base_mask()
1041 cs, *base1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
1045 for_each_chip_select_mask(cs, 0, pvt) { in read_dct_base_mask()
1048 u32 *mask0 = &pvt->csels[0].csmasks[cs]; in read_dct_base_mask()
1049 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in read_dct_base_mask()
1051 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0)) in read_dct_base_mask()
1055 if (pvt->fam == 0xf) in read_dct_base_mask()
1058 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) in read_dct_base_mask()
1060 cs, *mask1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
1065 static void determine_memory_type(struct amd64_pvt *pvt) in determine_memory_type() argument
1069 if (pvt->umc) { in determine_memory_type()
1070 if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) in determine_memory_type()
1071 pvt->dram_type = MEM_LRDDR4; in determine_memory_type()
1072 else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) in determine_memory_type()
1073 pvt->dram_type = MEM_RDDR4; in determine_memory_type()
1075 pvt->dram_type = MEM_DDR4; in determine_memory_type()
1079 switch (pvt->fam) { in determine_memory_type()
1081 if (pvt->ext_model >= K8_REV_F) in determine_memory_type()
1084 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in determine_memory_type()
1088 if (pvt->dchr0 & DDR3_MODE) in determine_memory_type()
1091 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in determine_memory_type()
1095 if (pvt->model < 0x60) in determine_memory_type()
1107 amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl); in determine_memory_type()
1108 dcsm = pvt->csels[0].csmasks[0]; in determine_memory_type()
1111 pvt->dram_type = MEM_DDR4; in determine_memory_type()
1112 else if (pvt->dclr0 & BIT(16)) in determine_memory_type()
1113 pvt->dram_type = MEM_DDR3; in determine_memory_type()
1115 pvt->dram_type = MEM_LRDDR3; in determine_memory_type()
1117 pvt->dram_type = MEM_RDDR3; in determine_memory_type()
1125 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); in determine_memory_type()
1126 pvt->dram_type = MEM_EMPTY; in determine_memory_type()
1131 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in determine_memory_type()
1135 static int k8_early_channel_count(struct amd64_pvt *pvt) in k8_early_channel_count() argument
1139 if (pvt->ext_model >= K8_REV_F) in k8_early_channel_count()
1141 flag = pvt->dclr0 & WIDTH_128; in k8_early_channel_count()
1144 flag = pvt->dclr0 & REVE_WIDTH_128; in k8_early_channel_count()
1147 pvt->dclr1 = 0; in k8_early_channel_count()
1153 static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) in get_error_address() argument
1165 pvt = mci->pvt_info; in get_error_address()
1167 if (pvt->fam == 0xf) { in get_error_address()
1177 if (pvt->fam == 0x15) { in get_error_address()
1186 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); in get_error_address()
1201 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); in get_error_address()
1234 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) in read_dram_base_limit_regs() argument
1242 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); in read_dram_base_limit_regs()
1243 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); in read_dram_base_limit_regs()
1245 if (pvt->fam == 0xf) in read_dram_base_limit_regs()
1248 if (!dram_rw(pvt, range)) in read_dram_base_limit_regs()
1251 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); in read_dram_base_limit_regs()
1252 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); in read_dram_base_limit_regs()
1255 if (pvt->fam != 0x15) in read_dram_base_limit_regs()
1258 nb = node_to_amd_nb(dram_dst_node(pvt, range)); in read_dram_base_limit_regs()
1262 if (pvt->model == 0x60) in read_dram_base_limit_regs()
1264 else if (pvt->model == 0x30) in read_dram_base_limit_regs()
1275 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); in read_dram_base_limit_regs()
1278 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; in read_dram_base_limit_regs()
1280 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); in read_dram_base_limit_regs()
1283 pvt->ranges[range].lim.hi |= llim >> 13; in read_dram_base_limit_regs()
1291 struct amd64_pvt *pvt = mci->pvt_info; in k8_map_sysaddr_to_csrow() local
1315 if (pvt->nbcfg & NBCFG_CHIPKILL) { in k8_map_sysaddr_to_csrow()
1356 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in k8_dbam_to_chip_select() argument
1359 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1361 if (pvt->ext_model >= K8_REV_F) { in k8_dbam_to_chip_select()
1365 else if (pvt->ext_model >= K8_REV_D) { in k8_dbam_to_chip_select()
1411 static int f1x_early_channel_count(struct amd64_pvt *pvt) in f1x_early_channel_count() argument
1416 if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128)) in f1x_early_channel_count()
1435 u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); in f1x_early_channel_count()
1453 static int f17_early_channel_count(struct amd64_pvt *pvt) in f17_early_channel_count() argument
1459 channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT); in f17_early_channel_count()
1523 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f10_dbam_to_chip_select() argument
1526 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1530 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) in f10_dbam_to_chip_select()
1539 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_dbam_to_chip_select() argument
1548 static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_m60h_dbam_to_chip_select() argument
1552 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
1556 if (pvt->dram_type == MEM_DDR4) { in f15_m60h_dbam_to_chip_select()
1561 } else if (pvt->dram_type == MEM_LRDDR3) { in f15_m60h_dbam_to_chip_select()
1581 static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f16_dbam_to_chip_select() argument
1593 static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in f17_addr_mask_to_cs_size() argument
1621 addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm]; in f17_addr_mask_to_cs_size()
1623 addr_mask_orig = pvt->csels[umc].csmasks[dimm]; in f17_addr_mask_to_cs_size()
1654 static void read_dram_ctl_register(struct amd64_pvt *pvt) in read_dram_ctl_register() argument
1657 if (pvt->fam == 0xf) in read_dram_ctl_register()
1660 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()
1662 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()
1665 (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); in read_dram_ctl_register()
1667 if (!dct_ganging_enabled(pvt)) in read_dram_ctl_register()
1669 (dct_high_range_enabled(pvt) ? "yes" : "no")); in read_dram_ctl_register()
1672 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
1673 (dct_memory_cleared(pvt) ? "yes" : "no")); in read_dram_ctl_register()
1677 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
1678 dct_sel_interleave_addr(pvt)); in read_dram_ctl_register()
1681 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); in read_dram_ctl_register()
1688 static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f15_m30h_determine_channel() argument
1702 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_determine_channel()
1719 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f1x_determine_channel() argument
1722 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
1724 if (dct_ganging_enabled(pvt)) in f1x_determine_channel()
1733 if (dct_interleave_enabled(pvt)) { in f1x_determine_channel()
1734 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f1x_determine_channel()
1756 if (dct_high_range_enabled(pvt)) in f1x_determine_channel()
1763 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, in f1x_get_norm_dct_addr() argument
1768 u64 dram_base = get_dram_base(pvt, range); in f1x_get_norm_dct_addr()
1769 u64 hole_off = f10_dhar_offset(pvt); in f1x_get_norm_dct_addr()
1770 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; in f1x_get_norm_dct_addr()
1785 dct_sel_base_addr < dhar_base(pvt)) && in f1x_get_norm_dct_addr()
1786 dhar_valid(pvt) && in f1x_get_norm_dct_addr()
1801 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) in f1x_get_norm_dct_addr()
1814 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) in f10_process_possible_spare() argument
1818 if (online_spare_swap_done(pvt, dct) && in f10_process_possible_spare()
1819 csrow == online_spare_bad_dramcs(pvt, dct)) { in f10_process_possible_spare()
1821 for_each_chip_select(tmp_cs, dct, pvt) { in f10_process_possible_spare()
1822 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { in f10_process_possible_spare()
1842 struct amd64_pvt *pvt; in f1x_lookup_addr_in_dct() local
1851 pvt = mci->pvt_info; in f1x_lookup_addr_in_dct()
1855 for_each_chip_select(csrow, dct, pvt) { in f1x_lookup_addr_in_dct()
1856 if (!csrow_enabled(csrow, dct, pvt)) in f1x_lookup_addr_in_dct()
1859 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
1870 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in f1x_lookup_addr_in_dct()
1874 cs_found = f10_process_possible_spare(pvt, dct, csrow); in f1x_lookup_addr_in_dct()
1888 static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) in f1x_swap_interleaved_region() argument
1892 if (pvt->fam == 0x10) { in f1x_swap_interleaved_region()
1894 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) in f1x_swap_interleaved_region()
1898 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); in f1x_swap_interleaved_region()
1918 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f1x_match_to_this_node() argument
1927 u8 node_id = dram_dst_node(pvt, range); in f1x_match_to_this_node()
1928 u8 intlv_en = dram_intlv_en(pvt, range); in f1x_match_to_this_node()
1929 u32 intlv_sel = dram_intlv_sel(pvt, range); in f1x_match_to_this_node()
1932 range, sys_addr, get_dram_limit(pvt, range)); in f1x_match_to_this_node()
1934 if (dhar_valid(pvt) && in f1x_match_to_this_node()
1935 dhar_base(pvt) <= sys_addr && in f1x_match_to_this_node()
1945 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); in f1x_match_to_this_node()
1947 dct_sel_base = dct_sel_baseaddr(pvt); in f1x_match_to_this_node()
1953 if (dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
1954 !dct_ganging_enabled(pvt) && in f1x_match_to_this_node()
1958 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); in f1x_match_to_this_node()
1960 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, in f1x_match_to_this_node()
1969 if (dct_interleave_enabled(pvt) && in f1x_match_to_this_node()
1970 !dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
1971 !dct_ganging_enabled(pvt)) { in f1x_match_to_this_node()
1973 if (dct_sel_interleave_addr(pvt) != 1) { in f1x_match_to_this_node()
1974 if (dct_sel_interleave_addr(pvt) == 0x3) in f1x_match_to_this_node()
1998 static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f15_m30h_match_to_this_node() argument
2008 u64 dhar_offset = f10_dhar_offset(pvt); in f15_m30h_match_to_this_node()
2009 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_match_to_this_node()
2010 u8 node_id = dram_dst_node(pvt, range); in f15_m30h_match_to_this_node()
2011 u8 intlv_en = dram_intlv_en(pvt, range); in f15_m30h_match_to_this_node()
2013 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); in f15_m30h_match_to_this_node()
2014 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); in f15_m30h_match_to_this_node()
2020 range, sys_addr, get_dram_limit(pvt, range)); in f15_m30h_match_to_this_node()
2022 if (!(get_dram_base(pvt, range) <= sys_addr) && in f15_m30h_match_to_this_node()
2023 !(get_dram_limit(pvt, range) >= sys_addr)) in f15_m30h_match_to_this_node()
2026 if (dhar_valid(pvt) && in f15_m30h_match_to_this_node()
2027 dhar_base(pvt) <= sys_addr && in f15_m30h_match_to_this_node()
2035 dct_base = (u64) dct_sel_baseaddr(pvt); in f15_m30h_match_to_this_node()
2049 if (pvt->model >= 0x60) in f15_m30h_match_to_this_node()
2050 channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en); in f15_m30h_match_to_this_node()
2052 channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en, in f15_m30h_match_to_this_node()
2092 amd64_read_pci_cfg(pvt->F1, in f15_m30h_match_to_this_node()
2098 f15h_select_dct(pvt, channel); in f15_m30h_match_to_this_node()
2120 static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, in f1x_translate_sysaddr_to_cs() argument
2128 if (!dram_rw(pvt, range)) in f1x_translate_sysaddr_to_cs()
2131 if (pvt->fam == 0x15 && pvt->model >= 0x30) in f1x_translate_sysaddr_to_cs()
2132 cs_found = f15_m30h_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
2136 else if ((get_dram_base(pvt, range) <= sys_addr) && in f1x_translate_sysaddr_to_cs()
2137 (get_dram_limit(pvt, range) >= sys_addr)) { in f1x_translate_sysaddr_to_cs()
2138 cs_found = f1x_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
2157 struct amd64_pvt *pvt = mci->pvt_info; in f1x_map_sysaddr_to_csrow() local
2161 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); in f1x_map_sysaddr_to_csrow()
2172 if (dct_ganging_enabled(pvt)) in f1x_map_sysaddr_to_csrow()
2180 static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) in debug_display_dimm_sizes() argument
2183 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in debug_display_dimm_sizes()
2184 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; in debug_display_dimm_sizes()
2186 if (pvt->fam == 0xf) { in debug_display_dimm_sizes()
2188 if (pvt->ext_model < K8_REV_F) in debug_display_dimm_sizes()
2194 if (pvt->fam == 0x10) { in debug_display_dimm_sizes()
2195 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 in debug_display_dimm_sizes()
2196 : pvt->dbam0; in debug_display_dimm_sizes()
2197 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? in debug_display_dimm_sizes()
2198 pvt->csels[1].csbases : in debug_display_dimm_sizes()
2199 pvt->csels[0].csbases; in debug_display_dimm_sizes()
2201 dbam = pvt->dbam0; in debug_display_dimm_sizes()
2202 dcsb = pvt->csels[1].csbases; in debug_display_dimm_sizes()
2220 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2226 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2521 struct amd64_pvt *pvt = mci->pvt_info; in get_channel_from_ecc_syndrome() local
2524 if (pvt->ecc_sym_sz == 8) in get_channel_from_ecc_syndrome()
2527 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2528 else if (pvt->ecc_sym_sz == 4) in get_channel_from_ecc_syndrome()
2531 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2533 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2537 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2590 struct amd64_pvt *pvt; in decode_bus_error() local
2601 pvt = mci->pvt_info; in decode_bus_error()
2613 sys_addr = get_error_address(pvt, m); in decode_bus_error()
2618 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); in decode_bus_error()
2641 struct amd64_pvt *pvt; in decode_umc_error() local
2649 pvt = mci->pvt_info; in decode_umc_error()
2674 if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) { in decode_umc_error()
2691 reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2) in reserve_mc_sibling_devs() argument
2693 if (pvt->umc) { in reserve_mc_sibling_devs()
2694 pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2695 if (!pvt->F0) { in reserve_mc_sibling_devs()
2700 pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2701 if (!pvt->F6) { in reserve_mc_sibling_devs()
2702 pci_dev_put(pvt->F0); in reserve_mc_sibling_devs()
2703 pvt->F0 = NULL; in reserve_mc_sibling_devs()
2710 pci_ctl_dev = &pvt->F0->dev; in reserve_mc_sibling_devs()
2712 edac_dbg(1, "F0: %s\n", pci_name(pvt->F0)); in reserve_mc_sibling_devs()
2713 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2714 edac_dbg(1, "F6: %s\n", pci_name(pvt->F6)); in reserve_mc_sibling_devs()
2720 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2721 if (!pvt->F1) { in reserve_mc_sibling_devs()
2727 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2728 if (!pvt->F2) { in reserve_mc_sibling_devs()
2729 pci_dev_put(pvt->F1); in reserve_mc_sibling_devs()
2730 pvt->F1 = NULL; in reserve_mc_sibling_devs()
2737 pci_ctl_dev = &pvt->F2->dev; in reserve_mc_sibling_devs()
2739 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); in reserve_mc_sibling_devs()
2740 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); in reserve_mc_sibling_devs()
2741 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2746 static void free_mc_sibling_devs(struct amd64_pvt *pvt) in free_mc_sibling_devs() argument
2748 if (pvt->umc) { in free_mc_sibling_devs()
2749 pci_dev_put(pvt->F0); in free_mc_sibling_devs()
2750 pci_dev_put(pvt->F6); in free_mc_sibling_devs()
2752 pci_dev_put(pvt->F1); in free_mc_sibling_devs()
2753 pci_dev_put(pvt->F2); in free_mc_sibling_devs()
2757 static void determine_ecc_sym_sz(struct amd64_pvt *pvt) in determine_ecc_sym_sz() argument
2759 pvt->ecc_sym_sz = 4; in determine_ecc_sym_sz()
2761 if (pvt->umc) { in determine_ecc_sym_sz()
2766 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in determine_ecc_sym_sz()
2767 if (pvt->umc[i].ecc_ctrl & BIT(9)) { in determine_ecc_sym_sz()
2768 pvt->ecc_sym_sz = 16; in determine_ecc_sym_sz()
2770 } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { in determine_ecc_sym_sz()
2771 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
2776 } else if (pvt->fam >= 0x10) { in determine_ecc_sym_sz()
2779 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); in determine_ecc_sym_sz()
2781 if (pvt->fam != 0x16) in determine_ecc_sym_sz()
2782 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); in determine_ecc_sym_sz()
2785 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) in determine_ecc_sym_sz()
2786 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
2793 static void __read_mc_regs_df(struct amd64_pvt *pvt) in __read_mc_regs_df() argument
2795 u8 nid = pvt->mc_node_id; in __read_mc_regs_df()
2803 umc = &pvt->umc[i]; in __read_mc_regs_df()
2817 static void read_mc_regs(struct amd64_pvt *pvt) in read_mc_regs() argument
2826 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); in read_mc_regs()
2827 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); in read_mc_regs()
2832 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); in read_mc_regs()
2833 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); in read_mc_regs()
2838 if (pvt->umc) { in read_mc_regs()
2839 __read_mc_regs_df(pvt); in read_mc_regs()
2840 amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar); in read_mc_regs()
2845 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); in read_mc_regs()
2847 read_dram_ctl_register(pvt); in read_mc_regs()
2853 read_dram_base_limit_regs(pvt, range); in read_mc_regs()
2855 rw = dram_rw(pvt, range); in read_mc_regs()
2861 get_dram_base(pvt, range), in read_mc_regs()
2862 get_dram_limit(pvt, range)); in read_mc_regs()
2865 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", in read_mc_regs()
2868 dram_intlv_sel(pvt, range), in read_mc_regs()
2869 dram_dst_node(pvt, range)); in read_mc_regs()
2872 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); in read_mc_regs()
2873 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); in read_mc_regs()
2875 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); in read_mc_regs()
2877 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); in read_mc_regs()
2878 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); in read_mc_regs()
2880 if (!dct_ganging_enabled(pvt)) { in read_mc_regs()
2881 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); in read_mc_regs()
2882 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); in read_mc_regs()
2886 read_dct_base_mask(pvt); in read_mc_regs()
2888 determine_memory_type(pvt); in read_mc_regs()
2889 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); in read_mc_regs()
2891 determine_ecc_sym_sz(pvt); in read_mc_regs()
2928 static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) in get_csrow_nr_pages() argument
2930 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in get_csrow_nr_pages()
2934 if (!pvt->umc) { in get_csrow_nr_pages()
2938 cs_mode = f17_get_cs_mode(csrow_nr >> 1, dct, pvt); in get_csrow_nr_pages()
2941 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in get_csrow_nr_pages()
2953 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows_df() local
2974 for_each_chip_select(cs, umc, pvt) { in init_csrows_df()
2975 if (!csrow_enabled(cs, umc, pvt)) in init_csrows_df()
2982 pvt->mc_node_id, cs); in init_csrows_df()
2984 dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs); in init_csrows_df()
2985 dimm->mtype = pvt->dram_type; in init_csrows_df()
3001 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows() local
3009 if (pvt->umc) in init_csrows()
3012 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); in init_csrows()
3014 pvt->nbcfg = val; in init_csrows()
3017 pvt->mc_node_id, val, in init_csrows()
3023 for_each_chip_select(i, 0, pvt) { in init_csrows()
3024 bool row_dct0 = !!csrow_enabled(i, 0, pvt); in init_csrows()
3027 if (pvt->fam != 0xf) in init_csrows()
3028 row_dct1 = !!csrow_enabled(i, 1, pvt); in init_csrows()
3037 pvt->mc_node_id, i); in init_csrows()
3040 nr_pages = get_csrow_nr_pages(pvt, 0, i); in init_csrows()
3045 if (pvt->fam != 0xf && row_dct1) { in init_csrows()
3046 int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i); in init_csrows()
3055 if (pvt->nbcfg & NBCFG_ECC_ENABLE) { in init_csrows()
3056 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) in init_csrows()
3061 for (j = 0; j < pvt->channel_count; j++) { in init_csrows()
3063 dimm->mtype = pvt->dram_type; in init_csrows()
3232 static bool ecc_enabled(struct amd64_pvt *pvt) in ecc_enabled() argument
3234 u16 nid = pvt->mc_node_id; in ecc_enabled()
3244 umc = &pvt->umc[i]; in ecc_enabled()
3265 amd64_read_pci_cfg(pvt->F3, NBCFG, &value); in ecc_enabled()
3285 f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) in f17h_determine_edac_ctl_cap() argument
3290 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in f17h_determine_edac_ctl_cap()
3291 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); in f17h_determine_edac_ctl_cap()
3292 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); in f17h_determine_edac_ctl_cap()
3294 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); in f17h_determine_edac_ctl_cap()
3295 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); in f17h_determine_edac_ctl_cap()
3317 struct amd64_pvt *pvt = mci->pvt_info; in setup_mci_misc_attrs() local
3322 if (pvt->umc) { in setup_mci_misc_attrs()
3323 f17h_determine_edac_ctl_cap(mci, pvt); in setup_mci_misc_attrs()
3325 if (pvt->nbcap & NBCAP_SECDED) in setup_mci_misc_attrs()
3328 if (pvt->nbcap & NBCAP_CHIPKILL) in setup_mci_misc_attrs()
3332 mci->edac_cap = determine_edac_cap(pvt); in setup_mci_misc_attrs()
3335 mci->dev_name = pci_name(pvt->F3); in setup_mci_misc_attrs()
3346 static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) in per_family_init() argument
3348 pvt->ext_model = boot_cpu_data.x86_model >> 4; in per_family_init()
3349 pvt->stepping = boot_cpu_data.x86_stepping; in per_family_init()
3350 pvt->model = boot_cpu_data.x86_model; in per_family_init()
3351 pvt->fam = boot_cpu_data.x86; in per_family_init()
3353 switch (pvt->fam) { in per_family_init()
3356 pvt->ops = &family_types[K8_CPUS].ops; in per_family_init()
3361 pvt->ops = &family_types[F10_CPUS].ops; in per_family_init()
3365 if (pvt->model == 0x30) { in per_family_init()
3367 pvt->ops = &family_types[F15_M30H_CPUS].ops; in per_family_init()
3369 } else if (pvt->model == 0x60) { in per_family_init()
3371 pvt->ops = &family_types[F15_M60H_CPUS].ops; in per_family_init()
3374 } else if (pvt->model == 0x13) { in per_family_init()
3378 pvt->ops = &family_types[F15_CPUS].ops; in per_family_init()
3383 if (pvt->model == 0x30) { in per_family_init()
3385 pvt->ops = &family_types[F16_M30H_CPUS].ops; in per_family_init()
3389 pvt->ops = &family_types[F16_CPUS].ops; in per_family_init()
3393 if (pvt->model >= 0x10 && pvt->model <= 0x2f) { in per_family_init()
3395 pvt->ops = &family_types[F17_M10H_CPUS].ops; in per_family_init()
3397 } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { in per_family_init()
3399 pvt->ops = &family_types[F17_M30H_CPUS].ops; in per_family_init()
3401 } else if (pvt->model >= 0x60 && pvt->model <= 0x6f) { in per_family_init()
3403 pvt->ops = &family_types[F17_M60H_CPUS].ops; in per_family_init()
3405 } else if (pvt->model >= 0x70 && pvt->model <= 0x7f) { in per_family_init()
3407 pvt->ops = &family_types[F17_M70H_CPUS].ops; in per_family_init()
3413 pvt->ops = &family_types[F17_CPUS].ops; in per_family_init()
3415 if (pvt->fam == 0x18) in per_family_init()
3420 if (pvt->model >= 0x20 && pvt->model <= 0x2f) { in per_family_init()
3422 pvt->ops = &family_types[F17_M70H_CPUS].ops; in per_family_init()
3427 pvt->ops = &family_types[F19_CPUS].ops; in per_family_init()
3437 (pvt->fam == 0xf ? in per_family_init()
3438 (pvt->ext_model >= K8_REV_F ? "revF or later " in per_family_init()
3440 : ""), pvt->mc_node_id); in per_family_init()
3454 static int hw_info_get(struct amd64_pvt *pvt) in hw_info_get() argument
3459 if (pvt->fam >= 0x17) { in hw_info_get()
3460 pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in hw_info_get()
3461 if (!pvt->umc) in hw_info_get()
3471 ret = reserve_mc_sibling_devs(pvt, pci_id1, pci_id2); in hw_info_get()
3475 read_mc_regs(pvt); in hw_info_get()
3480 static void hw_info_put(struct amd64_pvt *pvt) in hw_info_put() argument
3482 if (pvt->F0 || pvt->F1) in hw_info_put()
3483 free_mc_sibling_devs(pvt); in hw_info_put()
3485 kfree(pvt->umc); in hw_info_put()
3488 static int init_one_instance(struct amd64_pvt *pvt) in init_one_instance() argument
3499 pvt->channel_count = pvt->ops->early_channel_count(pvt); in init_one_instance()
3500 if (pvt->channel_count < 0) in init_one_instance()
3505 layers[0].size = pvt->csels[0].b_cnt; in init_one_instance()
3517 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); in init_one_instance()
3521 mci->pvt_info = pvt; in init_one_instance()
3522 mci->pdev = &pvt->F3->dev; in init_one_instance()
3539 static bool instance_has_memory(struct amd64_pvt *pvt) in instance_has_memory() argument
3545 for_each_chip_select(cs, dct, pvt) in instance_has_memory()
3546 cs_enabled |= csrow_enabled(cs, dct, pvt); in instance_has_memory()
3555 struct amd64_pvt *pvt = NULL; in probe_one_instance() local
3566 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); in probe_one_instance()
3567 if (!pvt) in probe_one_instance()
3570 pvt->mc_node_id = nid; in probe_one_instance()
3571 pvt->F3 = F3; in probe_one_instance()
3574 fam_type = per_family_init(pvt); in probe_one_instance()
3578 ret = hw_info_get(pvt); in probe_one_instance()
3583 if (!instance_has_memory(pvt)) { in probe_one_instance()
3588 if (!ecc_enabled(pvt)) { in probe_one_instance()
3604 ret = init_one_instance(pvt); in probe_one_instance()
3614 dump_misc_regs(pvt); in probe_one_instance()
3619 hw_info_put(pvt); in probe_one_instance()
3620 kfree(pvt); in probe_one_instance()
3635 struct amd64_pvt *pvt; in remove_one_instance() local
3642 pvt = mci->pvt_info; in remove_one_instance()
3652 hw_info_put(pvt); in remove_one_instance()
3653 kfree(pvt); in remove_one_instance()