Lines Matching refs:offset
140 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_eic_update() argument
145 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_update()
153 tmp |= BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update()
155 tmp &= ~BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update()
161 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) in sprd_eic_read() argument
165 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_read()
167 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); in sprd_eic_read()
170 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset) in sprd_eic_request() argument
172 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1); in sprd_eic_request()
176 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset) in sprd_eic_free() argument
178 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0); in sprd_eic_free()
181 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset) in sprd_eic_get() argument
187 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA); in sprd_eic_get()
189 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA); in sprd_eic_get()
191 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA); in sprd_eic_get()
197 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset) in sprd_eic_direction_input() argument
203 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value) in sprd_eic_set() argument
208 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset, in sprd_eic_set_debounce() argument
213 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_set_debounce()
214 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4; in sprd_eic_set_debounce()
223 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset, in sprd_eic_set_config() argument
230 return sprd_eic_set_debounce(chip, offset, arg); in sprd_eic_set_config()
239 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_mask() local
243 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0); in sprd_eic_irq_mask()
244 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0); in sprd_eic_irq_mask()
247 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0); in sprd_eic_irq_mask()
250 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0); in sprd_eic_irq_mask()
253 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0); in sprd_eic_irq_mask()
264 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_unmask() local
268 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1); in sprd_eic_irq_unmask()
269 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1); in sprd_eic_irq_unmask()
272 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1); in sprd_eic_irq_unmask()
275 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1); in sprd_eic_irq_unmask()
278 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1); in sprd_eic_irq_unmask()
289 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_ack() local
293 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); in sprd_eic_irq_ack()
296 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); in sprd_eic_irq_ack()
299 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_ack()
302 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_ack()
313 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_set_type() local
320 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); in sprd_eic_irq_set_type()
323 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); in sprd_eic_irq_set_type()
328 state = sprd_eic_get(chip, offset); in sprd_eic_irq_set_type()
330 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
333 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
345 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); in sprd_eic_irq_set_type()
348 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); in sprd_eic_irq_set_type()
353 state = sprd_eic_get(chip, offset); in sprd_eic_irq_set_type()
355 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
358 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
370 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
371 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); in sprd_eic_irq_set_type()
372 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); in sprd_eic_irq_set_type()
376 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
377 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); in sprd_eic_irq_set_type()
378 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); in sprd_eic_irq_set_type()
382 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); in sprd_eic_irq_set_type()
383 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1); in sprd_eic_irq_set_type()
387 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
388 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); in sprd_eic_irq_set_type()
389 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); in sprd_eic_irq_set_type()
393 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); in sprd_eic_irq_set_type()
395 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); in sprd_eic_irq_set_type()
405 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
406 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); in sprd_eic_irq_set_type()
407 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); in sprd_eic_irq_set_type()
411 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
412 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); in sprd_eic_irq_set_type()
413 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); in sprd_eic_irq_set_type()
417 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); in sprd_eic_irq_set_type()
418 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1); in sprd_eic_irq_set_type()
422 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
423 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); in sprd_eic_irq_set_type()
424 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); in sprd_eic_irq_set_type()
428 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
429 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); in sprd_eic_irq_set_type()
430 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); in sprd_eic_irq_set_type()
446 unsigned int offset) in sprd_eic_toggle_trigger() argument
463 state = sprd_eic_get(chip, offset); in sprd_eic_toggle_trigger()
469 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); in sprd_eic_toggle_trigger()
471 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); in sprd_eic_toggle_trigger()
475 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); in sprd_eic_toggle_trigger()
477 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); in sprd_eic_toggle_trigger()
484 post_state = sprd_eic_get(chip, offset); in sprd_eic_toggle_trigger()
533 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n; in sprd_eic_handle_one_type() local
535 girq = irq_find_mapping(chip->irq.domain, offset); in sprd_eic_handle_one_type()
538 sprd_eic_toggle_trigger(chip, girq, offset); in sprd_eic_handle_one_type()