Lines Matching refs:rg
67 mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val) in mtk_gpio_w32() argument
69 struct gpio_chip *gc = &rg->chip; in mtk_gpio_w32()
72 offset = (rg->bank * GPIO_BANK_STRIDE) + offset; in mtk_gpio_w32()
77 mtk_gpio_r32(struct mtk_gc *rg, u32 offset) in mtk_gpio_r32() argument
79 struct gpio_chip *gc = &rg->chip; in mtk_gpio_r32()
82 offset = (rg->bank * GPIO_BANK_STRIDE) + offset; in mtk_gpio_r32()
90 struct mtk_gc *rg = to_mediatek_gpio(gc); in mediatek_gpio_irq_handler() local
95 pending = mtk_gpio_r32(rg, GPIO_REG_STAT); in mediatek_gpio_irq_handler()
101 mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); in mediatek_gpio_irq_handler()
112 struct mtk_gc *rg = to_mediatek_gpio(gc); in mediatek_gpio_irq_unmask() local
117 spin_lock_irqsave(&rg->lock, flags); in mediatek_gpio_irq_unmask()
118 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); in mediatek_gpio_irq_unmask()
119 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); in mediatek_gpio_irq_unmask()
120 high = mtk_gpio_r32(rg, GPIO_REG_HLVL); in mediatek_gpio_irq_unmask()
121 low = mtk_gpio_r32(rg, GPIO_REG_LLVL); in mediatek_gpio_irq_unmask()
122 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising)); in mediatek_gpio_irq_unmask()
123 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling)); in mediatek_gpio_irq_unmask()
124 mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel)); in mediatek_gpio_irq_unmask()
125 mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel)); in mediatek_gpio_irq_unmask()
126 spin_unlock_irqrestore(&rg->lock, flags); in mediatek_gpio_irq_unmask()
133 struct mtk_gc *rg = to_mediatek_gpio(gc); in mediatek_gpio_irq_mask() local
138 spin_lock_irqsave(&rg->lock, flags); in mediatek_gpio_irq_mask()
139 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); in mediatek_gpio_irq_mask()
140 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); in mediatek_gpio_irq_mask()
141 high = mtk_gpio_r32(rg, GPIO_REG_HLVL); in mediatek_gpio_irq_mask()
142 low = mtk_gpio_r32(rg, GPIO_REG_LLVL); in mediatek_gpio_irq_mask()
143 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin)); in mediatek_gpio_irq_mask()
144 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin)); in mediatek_gpio_irq_mask()
145 mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin)); in mediatek_gpio_irq_mask()
146 mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin)); in mediatek_gpio_irq_mask()
147 spin_unlock_irqrestore(&rg->lock, flags); in mediatek_gpio_irq_mask()
154 struct mtk_gc *rg = to_mediatek_gpio(gc); in mediatek_gpio_irq_type() local
159 if ((rg->rising | rg->falling | in mediatek_gpio_irq_type()
160 rg->hlevel | rg->llevel) & mask) in mediatek_gpio_irq_type()
166 rg->rising &= ~mask; in mediatek_gpio_irq_type()
167 rg->falling &= ~mask; in mediatek_gpio_irq_type()
168 rg->hlevel &= ~mask; in mediatek_gpio_irq_type()
169 rg->llevel &= ~mask; in mediatek_gpio_irq_type()
173 rg->rising |= mask; in mediatek_gpio_irq_type()
174 rg->falling |= mask; in mediatek_gpio_irq_type()
177 rg->rising |= mask; in mediatek_gpio_irq_type()
180 rg->falling |= mask; in mediatek_gpio_irq_type()
183 rg->hlevel |= mask; in mediatek_gpio_irq_type()
186 rg->llevel |= mask; in mediatek_gpio_irq_type()
198 struct mtk_gc *rg = to_mediatek_gpio(chip); in mediatek_gpio_xlate() local
200 if (rg->bank != gpio / MTK_BANK_WIDTH) in mediatek_gpio_xlate()
214 struct mtk_gc *rg; in mediatek_gpio_bank_probe() local
218 rg = &mtk->gc_map[bank]; in mediatek_gpio_bank_probe()
219 memset(rg, 0, sizeof(*rg)); in mediatek_gpio_bank_probe()
221 spin_lock_init(&rg->lock); in mediatek_gpio_bank_probe()
222 rg->chip.of_node = node; in mediatek_gpio_bank_probe()
223 rg->bank = bank; in mediatek_gpio_bank_probe()
225 dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE); in mediatek_gpio_bank_probe()
226 set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE); in mediatek_gpio_bank_probe()
227 ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); in mediatek_gpio_bank_probe()
228 diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); in mediatek_gpio_bank_probe()
230 ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL, in mediatek_gpio_bank_probe()
237 rg->chip.of_gpio_n_cells = 2; in mediatek_gpio_bank_probe()
238 rg->chip.of_xlate = mediatek_gpio_xlate; in mediatek_gpio_bank_probe()
239 rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", in mediatek_gpio_bank_probe()
241 if (!rg->chip.label) in mediatek_gpio_bank_probe()
244 rg->irq_chip.name = dev_name(dev); in mediatek_gpio_bank_probe()
245 rg->irq_chip.parent_device = dev; in mediatek_gpio_bank_probe()
246 rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask; in mediatek_gpio_bank_probe()
247 rg->irq_chip.irq_mask = mediatek_gpio_irq_mask; in mediatek_gpio_bank_probe()
248 rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask; in mediatek_gpio_bank_probe()
249 rg->irq_chip.irq_set_type = mediatek_gpio_irq_type; in mediatek_gpio_bank_probe()
260 rg->chip.label, &rg->chip); in mediatek_gpio_bank_probe()
268 girq = &rg->chip.irq; in mediatek_gpio_bank_probe()
269 girq->chip = &rg->irq_chip; in mediatek_gpio_bank_probe()
278 ret = devm_gpiochip_add_data(dev, &rg->chip, mtk); in mediatek_gpio_bank_probe()
281 rg->chip.ngpio, ret); in mediatek_gpio_bank_probe()
286 mtk_gpio_w32(rg, GPIO_REG_POL, 0); in mediatek_gpio_bank_probe()
288 dev_info(dev, "registering %d gpios\n", rg->chip.ngpio); in mediatek_gpio_bank_probe()