Lines Matching +full:msi +full:- +full:base +full:- +full:spi
1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/msi.h>
28 #include "../pci-bridge-emul.h"
44 /* PIO registers base address and register offsets */
136 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
161 /* LMI registers base address and register offsets */
274 void __iomem *base; member
301 writel(val, pcie->base + reg); in advk_writel()
306 return readl(pcie->base + reg); in advk_readl()
321 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
329 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
343 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_training()
366 return -ETIMEDOUT; in advk_pcie_wait_for_link()
382 if (!pcie->reset_gpio) in advk_pcie_issue_perst()
386 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); in advk_pcie_issue_perst()
387 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_issue_perst()
389 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in advk_pcie_issue_perst()
394 struct device *dev = &pcie->pdev->dev; in advk_pcie_train_link()
400 * 'max-link-speed' which also forces maximal link speed. in advk_pcie_train_link()
404 if (pcie->link_gen == 3) in advk_pcie_train_link()
406 else if (pcie->link_gen == 2) in advk_pcie_train_link()
419 if (pcie->link_gen == 3) in advk_pcie_train_link()
421 else if (pcie->link_gen == 2) in advk_pcie_train_link()
434 * during link training when they are in some non-initial state. in advk_pcie_train_link()
443 * Base Specification, REV. 4.0 PCI Express, February 19 2014, 6.6.1 in advk_pcie_train_link()
493 * Reference clock differential signal off-chip and disable in advk_pcie_setup_hw()
494 * receiving off-chip differential signal. in advk_pcie_setup_hw()
516 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround in advk_pcie_setup_hw()
530 * and is reported as Type 0. In range 0x10 - 0x34 it has totally in advk_pcie_setup_hw()
575 /* Enable MSI */ in advk_pcie_setup_hw()
596 /* Enable summary interrupt for GIC SPI source */ in advk_pcie_setup_hw()
632 * Configure PCIe address windows for non-memory or in advk_pcie_setup_hw()
633 * non-transparent access as by default PCIe uses in advk_pcie_setup_hw()
636 for (i = 0; i < pcie->wins_count; i++) in advk_pcie_setup_hw()
638 pcie->wins[i].match, pcie->wins[i].remap, in advk_pcie_setup_hw()
639 pcie->wins[i].mask, pcie->wins[i].actions); in advk_pcie_setup_hw()
642 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) in advk_pcie_setup_hw()
650 struct device *dev = &pcie->pdev->dev; in advk_pcie_check_pio_status()
679 ret = -EFAULT; in advk_pcie_check_pio_status()
691 ret = -EOPNOTSUPP; in advk_pcie_check_pio_status()
701 * read-data value of 0001h for the Vendor ID field and in advk_pcie_check_pio_status()
714 * must re-issue the Configuration Request as a new Request. in advk_pcie_check_pio_status()
717 * the Root Complex must re-issue the Configuration Request as in advk_pcie_check_pio_status()
725 * So return -EAGAIN and caller (pci-aardvark.c driver) will in advk_pcie_check_pio_status()
726 * re-issue request again up to the PIO_RETRY_CNT retries. in advk_pcie_check_pio_status()
729 ret = -EAGAIN; in advk_pcie_check_pio_status()
733 ret = -ECANCELED; in advk_pcie_check_pio_status()
737 ret = -EINVAL; in advk_pcie_check_pio_status()
745 str_posted = "Non-posted"; in advk_pcie_check_pio_status()
757 struct device *dev = &pcie->pdev->dev; in advk_pcie_wait_pio()
771 return -ETIMEDOUT; in advk_pcie_wait_pio()
778 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_read()
791 __le32 *cfgspace = (__le32 *)&bridge->conf; in advk_pci_bridge_emul_base_conf_read()
810 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_write()
837 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_read()
848 *value |= le16_to_cpu(bridge->pcie_conf.rootctl) & PCI_EXP_RTCTL_CRSSVE; in advk_pci_bridge_emul_pcie_conf_read()
900 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_write()
941 * Initialize the configuration space of the PCI-to-PCI bridge
946 struct pci_bridge_emul *bridge = &pcie->bridge; in advk_sw_pci_bridge_init()
948 bridge->conf.vendor = in advk_sw_pci_bridge_init()
950 bridge->conf.device = in advk_sw_pci_bridge_init()
952 bridge->conf.class_revision = in advk_sw_pci_bridge_init()
956 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
957 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
960 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
961 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
963 /* Support interrupt A for MSI feature */ in advk_sw_pci_bridge_init()
964 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; in advk_sw_pci_bridge_init()
967 bridge->pcie_conf.cap = cpu_to_le16(2); in advk_sw_pci_bridge_init()
970 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); in advk_sw_pci_bridge_init()
972 bridge->has_pcie = true; in advk_sw_pci_bridge_init()
973 bridge->data = pcie; in advk_sw_pci_bridge_init()
974 bridge->ops = &advk_pci_bridge_emul_ops; in advk_sw_pci_bridge_init()
986 * If the link goes down after we check for link-up, nothing bad in advk_pcie_valid_device()
997 struct device *dev = &pcie->pdev->dev; in advk_pcie_pio_is_running()
1003 * SError Interrupt on CPU0, code 0xbf000002 -- SError in advk_pcie_pio_is_running()
1004 * Kernel panic - not syncing: Asynchronous SError Interrupt in advk_pcie_pio_is_running()
1013 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: in advk_pcie_pio_is_running()
1014 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 in advk_pcie_pio_is_running()
1027 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_rd_conf()
1039 return pci_bridge_emul_conf_read(&pcie->bridge, where, in advk_pcie_rd_conf()
1048 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & in advk_pcie_rd_conf()
1057 if (pci_is_root_bus(bus->parent)) in advk_pcie_rd_conf()
1064 reg = PCIE_CONF_ADDR(bus->number, devfn, where); in advk_pcie_rd_conf()
1085 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); in advk_pcie_rd_conf()
1115 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_wr_conf()
1126 return pci_bridge_emul_conf_write(&pcie->bridge, where, in advk_pcie_wr_conf()
1138 if (pci_is_root_bus(bus->parent)) in advk_pcie_wr_conf()
1145 reg = PCIE_CONF_ADDR(bus->number, devfn, where); in advk_pcie_wr_conf()
1152 data_strobe = GENMASK(size - 1, 0) << offset; in advk_pcie_wr_conf()
1173 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); in advk_pcie_wr_conf()
1187 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); in advk_msi_irq_compose_msi_msg()
1189 msg->address_lo = lower_32_bits(msi_msg); in advk_msi_irq_compose_msi_msg()
1190 msg->address_hi = upper_32_bits(msi_msg); in advk_msi_irq_compose_msi_msg()
1191 msg->data = data->hwirq; in advk_msi_irq_compose_msi_msg()
1197 return -EINVAL; in advk_msi_set_affinity()
1204 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_alloc()
1207 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1208 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, in advk_msi_irq_domain_alloc()
1210 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1212 return -ENOSPC; in advk_msi_irq_domain_alloc()
1216 &pcie->msi_bottom_irq_chip, in advk_msi_irq_domain_alloc()
1217 domain->host_data, handle_simple_irq, in advk_msi_irq_domain_alloc()
1227 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_free()
1229 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1230 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); in advk_msi_irq_domain_free()
1231 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1241 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_mask()
1246 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1250 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1255 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_unmask()
1260 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1264 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1270 struct advk_pcie *pcie = h->host_data; in advk_pcie_irq_map()
1274 irq_set_chip_and_handler(virq, &pcie->irq_chip, in advk_pcie_irq_map()
1288 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_msi_irq_domain()
1289 struct device_node *node = dev->of_node; in advk_pcie_init_msi_irq_domain()
1294 mutex_init(&pcie->msi_used_lock); in advk_pcie_init_msi_irq_domain()
1296 bottom_ic = &pcie->msi_bottom_irq_chip; in advk_pcie_init_msi_irq_domain()
1298 bottom_ic->name = "MSI"; in advk_pcie_init_msi_irq_domain()
1299 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; in advk_pcie_init_msi_irq_domain()
1300 bottom_ic->irq_set_affinity = advk_msi_set_affinity; in advk_pcie_init_msi_irq_domain()
1302 msi_ic = &pcie->msi_irq_chip; in advk_pcie_init_msi_irq_domain()
1303 msi_ic->name = "advk-MSI"; in advk_pcie_init_msi_irq_domain()
1305 msi_di = &pcie->msi_domain_info; in advk_pcie_init_msi_irq_domain()
1306 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | in advk_pcie_init_msi_irq_domain()
1308 msi_di->chip = msi_ic; in advk_pcie_init_msi_irq_domain()
1310 msi_msg_phys = virt_to_phys(&pcie->msi_msg); in advk_pcie_init_msi_irq_domain()
1317 pcie->msi_inner_domain = in advk_pcie_init_msi_irq_domain()
1320 if (!pcie->msi_inner_domain) in advk_pcie_init_msi_irq_domain()
1321 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1323 pcie->msi_domain = in advk_pcie_init_msi_irq_domain()
1325 msi_di, pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1326 if (!pcie->msi_domain) { in advk_pcie_init_msi_irq_domain()
1327 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1328 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1336 irq_domain_remove(pcie->msi_domain); in advk_pcie_remove_msi_irq_domain()
1337 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_remove_msi_irq_domain()
1342 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_irq_domain()
1343 struct device_node *node = dev->of_node; in advk_pcie_init_irq_domain()
1348 raw_spin_lock_init(&pcie->irq_lock); in advk_pcie_init_irq_domain()
1353 return -ENODEV; in advk_pcie_init_irq_domain()
1356 irq_chip = &pcie->irq_chip; in advk_pcie_init_irq_domain()
1358 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", in advk_pcie_init_irq_domain()
1360 if (!irq_chip->name) { in advk_pcie_init_irq_domain()
1361 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1365 irq_chip->irq_mask = advk_pcie_irq_mask; in advk_pcie_init_irq_domain()
1366 irq_chip->irq_mask_ack = advk_pcie_irq_mask; in advk_pcie_init_irq_domain()
1367 irq_chip->irq_unmask = advk_pcie_irq_unmask; in advk_pcie_init_irq_domain()
1369 pcie->irq_domain = in advk_pcie_init_irq_domain()
1372 if (!pcie->irq_domain) { in advk_pcie_init_irq_domain()
1374 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1385 irq_domain_remove(pcie->irq_domain); in advk_pcie_remove_irq_domain()
1402 virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx); in advk_pcie_handle_msi()
1424 /* Process MSI interrupts */ in advk_pcie_handle_int()
1436 virq = irq_find_mapping(pcie->irq_domain, i); in advk_pcie_handle_int()
1460 phy_power_off(pcie->phy); in advk_pcie_disable_phy()
1461 phy_exit(pcie->phy); in advk_pcie_disable_phy()
1468 if (!pcie->phy) in advk_pcie_enable_phy()
1471 ret = phy_init(pcie->phy); in advk_pcie_enable_phy()
1475 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); in advk_pcie_enable_phy()
1477 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1481 ret = phy_power_on(pcie->phy); in advk_pcie_enable_phy()
1482 if (ret == -EOPNOTSUPP) { in advk_pcie_enable_phy()
1483 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); in advk_pcie_enable_phy()
1485 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1494 struct device *dev = &pcie->pdev->dev; in advk_pcie_setup_phy()
1495 struct device_node *node = dev->of_node; in advk_pcie_setup_phy()
1498 pcie->phy = devm_of_phy_get(dev, node, NULL); in advk_pcie_setup_phy()
1499 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) in advk_pcie_setup_phy()
1500 return PTR_ERR(pcie->phy); in advk_pcie_setup_phy()
1503 if (IS_ERR(pcie->phy)) { in advk_pcie_setup_phy()
1504 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); in advk_pcie_setup_phy()
1505 pcie->phy = NULL; in advk_pcie_setup_phy()
1518 struct device *dev = &pdev->dev; in advk_pcie_probe()
1526 return -ENOMEM; in advk_pcie_probe()
1529 pcie->pdev = pdev; in advk_pcie_probe()
1532 resource_list_for_each_entry(entry, &bridge->windows) { in advk_pcie_probe()
1533 resource_size_t start = entry->res->start; in advk_pcie_probe()
1534 resource_size_t size = resource_size(entry->res); in advk_pcie_probe()
1535 unsigned long type = resource_type(entry->res); in advk_pcie_probe()
1554 entry->offset == 0) in advk_pcie_probe()
1558 * The n-th PCIe window is configured by tuple (match, remap, mask) in advk_pcie_probe()
1566 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { in advk_pcie_probe()
1568 win_size = (1ULL << (fls64(size)-1)) | in advk_pcie_probe()
1575 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", in advk_pcie_probe()
1576 pcie->wins_count, (unsigned long long)start, in advk_pcie_probe()
1580 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; in advk_pcie_probe()
1581 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); in advk_pcie_probe()
1583 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; in advk_pcie_probe()
1584 pcie->wins[pcie->wins_count].match = start; in advk_pcie_probe()
1586 pcie->wins[pcie->wins_count].remap = start - entry->offset; in advk_pcie_probe()
1587 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); in advk_pcie_probe()
1589 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) in advk_pcie_probe()
1593 size -= win_size; in advk_pcie_probe()
1594 pcie->wins_count++; in advk_pcie_probe()
1598 dev_err(&pcie->pdev->dev, in advk_pcie_probe()
1599 "Invalid PCIe region [0x%llx-0x%llx]\n", in advk_pcie_probe()
1600 (unsigned long long)entry->res->start, in advk_pcie_probe()
1601 (unsigned long long)entry->res->end + 1); in advk_pcie_probe()
1602 return -EINVAL; in advk_pcie_probe()
1606 pcie->base = devm_platform_ioremap_resource(pdev, 0); in advk_pcie_probe()
1607 if (IS_ERR(pcie->base)) in advk_pcie_probe()
1608 return PTR_ERR(pcie->base); in advk_pcie_probe()
1615 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", in advk_pcie_probe()
1622 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, in advk_pcie_probe()
1623 "reset-gpios", 0, in advk_pcie_probe()
1625 "pcie1-reset"); in advk_pcie_probe()
1626 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); in advk_pcie_probe()
1628 if (ret == -ENOENT) { in advk_pcie_probe()
1629 pcie->reset_gpio = NULL; in advk_pcie_probe()
1631 if (ret != -EPROBE_DEFER) in advk_pcie_probe()
1632 dev_err(dev, "Failed to get reset-gpio: %i\n", in advk_pcie_probe()
1638 ret = of_pci_get_max_link_speed(dev->of_node); in advk_pcie_probe()
1640 pcie->link_gen = 3; in advk_pcie_probe()
1642 pcie->link_gen = ret; in advk_pcie_probe()
1669 bridge->sysdata = pcie; in advk_pcie_probe()
1670 bridge->ops = &advk_pcie_ops; in advk_pcie_probe()
1689 pci_stop_root_bus(bridge->bus); in advk_pcie_remove()
1690 pci_remove_root_bus(bridge->bus); in advk_pcie_remove()
1704 { .compatible = "marvell,armada-3700-pcie", },
1711 .name = "advk-pcie",