77 	void __iomem *reg_base;  member
107 	val = readl(wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
109 	writel(val, wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
112 	val = readl(wcss->reg_base + Q6SS_XO_CBCR);  in q6v5_wcss_reset()
114 	writel(val, wcss->reg_base + Q6SS_XO_CBCR);  in q6v5_wcss_reset()
117 	ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,  in q6v5_wcss_reset()
126 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
128 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
133 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
136 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
138 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
142 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
145 	val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);  in q6v5_wcss_reset()
148 		writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);  in q6v5_wcss_reset()
154 		val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);  in q6v5_wcss_reset()
158 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
160 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
164 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
167 	val = readl(wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
169 	writel(val, wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
172 	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);  in q6v5_wcss_reset()
174 	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);  in q6v5_wcss_reset()
177 	val = readl(wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
179 	writel(val, wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
219 	writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);  in q6v5_wcss_start()
330 	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);  in q6v5_q6_powerdown()
332 	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);  in q6v5_q6_powerdown()
335 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
337 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
341 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
345 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
349 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
353 		val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);  in q6v5_q6_powerdown()
355 		writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);  in q6v5_q6_powerdown()
360 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
362 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
366 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
370 	ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS,  in q6v5_q6_powerdown()
482 	wcss->reg_base = devm_ioremap_resource(&pdev->dev, res);  in q6v5_wcss_init_mmio()
483 	if (IS_ERR(wcss->reg_base))  in q6v5_wcss_init_mmio()
484 		return PTR_ERR(wcss->reg_base);  in q6v5_wcss_init_mmio()