Lines Matching refs:reg_base
93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
94 __be32 __iomem *mode = ®_base->mode; in fsl_spi_change_mode()
272 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
277 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
281 mpc8xxx_spi_write_reg(®_base->transmit, word); in fsl_spi_cpu_bufs()
290 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_bufs() local
295 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
328 mpc8xxx_spi_write_reg(®_base->mask, 0); in fsl_spi_bufs()
437 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_setup() local
455 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
458 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); in fsl_spi_setup()
496 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_irq() local
500 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); in fsl_spi_cpu_irq()
509 mpc8xxx_spi_read_reg(®_base->event)) & in fsl_spi_cpu_irq()
514 mpc8xxx_spi_write_reg(®_base->event, events); in fsl_spi_cpu_irq()
520 mpc8xxx_spi_write_reg(®_base->transmit, word); in fsl_spi_cpu_irq()
531 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_irq() local
534 events = mpc8xxx_spi_read_reg(®_base->event); in fsl_spi_irq()
551 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_cs_control() local
558 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); in fsl_spi_grlib_cs_control()
560 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); in fsl_spi_grlib_cs_control()
569 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_probe() local
573 capabilities = mpc8xxx_spi_read_reg(®_base->cap); in fsl_spi_grlib_probe()
583 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); in fsl_spi_grlib_probe()
595 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_probe() local
622 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); in fsl_spi_probe()
623 if (IS_ERR(mpc8xxx_spi->reg_base)) { in fsl_spi_probe()
624 ret = PTR_ERR(mpc8xxx_spi->reg_base); in fsl_spi_probe()
656 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_probe()
659 mpc8xxx_spi_write_reg(®_base->mode, 0); in fsl_spi_probe()
660 mpc8xxx_spi_write_reg(®_base->mask, 0); in fsl_spi_probe()
661 mpc8xxx_spi_write_reg(®_base->command, 0); in fsl_spi_probe()
662 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); in fsl_spi_probe()
673 mpc8xxx_spi_write_reg(®_base->mode, regval); in fsl_spi_probe()
679 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, in fsl_spi_probe()