906                                  ADDR_COMPUTE_SURFACE_INFO_OUTPUT *csio, struct radeon_surf *surf)  in gfx6_surface_settings()  argument
908    surf->surf_alignment_log2 = util_logbase2(csio->baseAlign);  in gfx6_surface_settings()
909    surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;  in gfx6_surface_settings()
913    if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {  in gfx6_surface_settings()
914       surf->u.legacy.bankw = csio->pTileInfo->bankWidth;  in gfx6_surface_settings()
915       surf->u.legacy.bankh = csio->pTileInfo->bankHeight;  in gfx6_surface_settings()
916       surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;  in gfx6_surface_settings()
917       surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;  in gfx6_surface_settings()
918       surf->u.legacy.num_banks = csio->pTileInfo->banks;  in gfx6_surface_settings()
919       surf->u.legacy.macro_tile_index = csio->macroModeIndex;  in gfx6_surface_settings()
937       AddrBaseSwizzleIn.tileIndex = csio->tileIndex;  in gfx6_surface_settings()
938       AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;  in gfx6_surface_settings()
939       AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;  in gfx6_surface_settings()
940       AddrBaseSwizzleIn.tileMode = csio->tileMode;  in gfx6_surface_settings()