Lines Matching refs:image
124 const struct radv_image *image) in radv_image_use_fast_clear_for_image_early() argument
129 if (image->info.samples <= 1 && image->info.width * image->info.height <= 512 * 512) { in radv_image_use_fast_clear_for_image_early()
138 return !!(image->vk.usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT); in radv_image_use_fast_clear_for_image_early()
143 const struct radv_image *image) in radv_image_use_fast_clear_for_image() argument
148 return radv_image_use_fast_clear_for_image_early(device, image) && in radv_image_use_fast_clear_for_image()
149 (image->exclusive || in radv_image_use_fast_clear_for_image()
154 radv_image_use_dcc_image_stores(device, image)); in radv_image_use_fast_clear_for_image()
228 radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *image, in radv_use_dcc_for_image_early() argument
239 if (image->shareable && image->vk.tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) in radv_use_dcc_for_image_early()
264 if (!radv_image_use_fast_clear_for_image_early(device, image) && in radv_use_dcc_for_image_early()
265 image->vk.tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) in radv_use_dcc_for_image_early()
288 radv_use_dcc_for_image_late(struct radv_device *device, struct radv_image *image) in radv_use_dcc_for_image_late() argument
290 if (!radv_image_has_dcc(image)) in radv_use_dcc_for_image_late()
293 if (image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) in radv_use_dcc_for_image_late()
296 if (!radv_image_use_fast_clear_for_image(device, image)) in radv_use_dcc_for_image_late()
301 if ((image->vk.usage & VK_IMAGE_USAGE_STORAGE_BIT) && in radv_use_dcc_for_image_late()
302 !radv_image_use_dcc_image_stores(device, image)) in radv_use_dcc_for_image_late()
319 radv_image_use_dcc_image_stores(const struct radv_device *device, const struct radv_image *image) in radv_image_use_dcc_image_stores() argument
322 &image->planes[0].surface); in radv_image_use_dcc_image_stores()
330 radv_image_use_dcc_predication(const struct radv_device *device, const struct radv_image *image) in radv_image_use_dcc_predication() argument
332 return radv_image_has_dcc(image) && !radv_image_use_dcc_image_stores(device, image); in radv_image_use_dcc_predication()
336 radv_use_fmask_for_image(const struct radv_device *device, const struct radv_image *image) in radv_use_fmask_for_image() argument
338 return image->info.samples > 1 && ((image->vk.usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) || in radv_use_fmask_for_image()
343 radv_use_htile_for_image(const struct radv_device *device, const struct radv_image *image) in radv_use_htile_for_image() argument
350 image->info.array_size == 1 && device->physical_device->rad_info.gfx_level >= GFX10; in radv_use_htile_for_image()
354 image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT && image->info.levels > 1) in radv_use_htile_for_image()
359 image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT && image->info.levels > 1) in radv_use_htile_for_image()
365 if (image->info.width * image->info.height < 8 * 8 && in radv_use_htile_for_image()
370 return (image->info.levels == 1 || use_htile_for_mips) && !image->shareable; in radv_use_htile_for_image()
374 radv_use_tc_compat_cmask_for_image(struct radv_device *device, struct radv_image *image) in radv_use_tc_compat_cmask_for_image() argument
384 if ((image->vk.usage & VK_IMAGE_USAGE_STORAGE_BIT) && in radv_use_tc_compat_cmask_for_image()
391 if (!(image->vk.usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT | in radv_use_tc_compat_cmask_for_image()
396 if (!radv_image_has_fmask(image)) in radv_use_tc_compat_cmask_for_image()
451 radv_patch_image_dimensions(struct radv_device *device, struct radv_image *image, in radv_patch_image_dimensions() argument
455 unsigned width = image->info.width; in radv_patch_image_dimensions()
456 unsigned height = image->info.height; in radv_patch_image_dimensions()
478 if (image->info.width == width && image->info.height == height) in radv_patch_image_dimensions()
481 if (width < image->info.width || height < image->info.height) { in radv_patch_image_dimensions()
487 image->info.width, image->info.height, width, height); in radv_patch_image_dimensions()
495 image->info.width, image->info.height, width, height); in radv_patch_image_dimensions()
503 image->info.width, image->info.height, width, height); in radv_patch_image_dimensions()
512 radv_patch_image_from_extra_info(struct radv_device *device, struct radv_image *image, in radv_patch_image_from_extra_info() argument
516 VkResult result = radv_patch_image_dimensions(device, image, create_info, image_info); in radv_patch_image_from_extra_info()
520 for (unsigned plane = 0; plane < image->plane_count; ++plane) { in radv_patch_image_from_extra_info()
522 radv_patch_surface_from_metadata(device, &image->planes[plane].surface, in radv_patch_image_from_extra_info()
527 image->planes[plane].surface.flags |= RADEON_SURF_SCANOUT; in radv_patch_image_from_extra_info()
529 image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC; in radv_patch_image_from_extra_info()
531 image->info.surf_index = NULL; in radv_patch_image_from_extra_info()
536 image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC; in radv_patch_image_from_extra_info()
568 radv_image_get_plane_format(const struct radv_physical_device *pdev, const struct radv_image *image, in radv_image_get_plane_format() argument
572 vk_format_description(image->vk.format)->layout == UTIL_FORMAT_LAYOUT_ETC) { in radv_image_get_plane_format()
574 return image->vk.format; in radv_image_get_plane_format()
575 return etc2_emulation_format(image->vk.format); in radv_image_get_plane_format()
577 return vk_format_get_plane_format(image->vk.format, plane); in radv_image_get_plane_format()
581 radv_get_surface_flags(struct radv_device *device, struct radv_image *image, unsigned plane_id, in radv_get_surface_flags() argument
586 VkFormat format = radv_image_get_plane_format(device->physical_device, image, plane_id); in radv_get_surface_flags()
621 if (radv_use_htile_for_image(device, image) && in radv_get_surface_flags()
638 if (!radv_use_dcc_for_image_early(device, image, pCreateInfo, image_format, in radv_get_surface_flags()
639 &image->dcc_sign_reinterpret)) in radv_get_surface_flags()
642 if (!radv_use_fmask_for_image(device, image)) in radv_get_surface_flags()
767 si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *image, in si_set_mutable_tex_desc_fields() argument
773 struct radv_image_plane *plane = &image->planes[plane_id]; in si_set_mutable_tex_desc_fields()
774 …struct radv_image_binding *binding = image->disjoint ? &image->bindings[plane_id] : &image->bindin… in si_set_mutable_tex_desc_fields()
796 if (!disable_compression && radv_dcc_enabled(image, first_level)) { in si_set_mutable_tex_desc_fields()
804 } else if (!disable_compression && radv_image_is_tc_compat_htile(image)) { in si_set_mutable_tex_desc_fields()
835 if (radv_dcc_enabled(image, first_level) && is_storage_image && enable_write_compression) in si_set_mutable_tex_desc_fields()
954 gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *image, in gfx10_make_texture_descriptor() argument
972 if (image->vk.format == VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK && in gfx10_make_texture_descriptor()
975 } else if (image->vk.format == VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK && in gfx10_make_texture_descriptor()
985 assert(image->vk.image_type == VK_IMAGE_TYPE_3D); in gfx10_make_texture_descriptor()
988 … type = radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, image->info.samples, in gfx10_make_texture_descriptor()
994 depth = image->info.array_size; in gfx10_make_texture_descriptor()
997 depth = image->info.array_size; in gfx10_make_texture_descriptor()
999 depth = image->info.array_size / 6; in gfx10_make_texture_descriptor()
1011 S_00A00C_BASE_LEVEL(image->info.samples > 1 ? 0 : first_level) | in gfx10_make_texture_descriptor()
1012 S_00A00C_LAST_LEVEL(image->info.samples > 1 ? util_logbase2(image->info.samples) in gfx10_make_texture_descriptor()
1038 image->info.samples > 1 ? util_logbase2(image->info.samples) : image->info.levels - 1; in gfx10_make_texture_descriptor()
1046 if (radv_dcc_enabled(image, first_level)) { in gfx10_make_texture_descriptor()
1049 image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size) | in gfx10_make_texture_descriptor()
1053 if (radv_image_get_iterate256(device, image)) { in gfx10_make_texture_descriptor()
1059 if (radv_image_has_fmask(image)) { in gfx10_make_texture_descriptor()
1060 uint64_t gpu_address = radv_buffer_get_va(image->bindings[0].bo); in gfx10_make_texture_descriptor()
1064 assert(image->plane_count == 1); in gfx10_make_texture_descriptor()
1066 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.fmask_offset; in gfx10_make_texture_descriptor()
1068 switch (image->info.samples) { in gfx10_make_texture_descriptor()
1082 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle; in gfx10_make_texture_descriptor()
1090 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode) | in gfx10_make_texture_descriptor()
1092 … radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, 0, false, false)); in gfx10_make_texture_descriptor()
1098 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1099 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset; in gfx10_make_texture_descriptor()
1114 si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, in si_make_texture_descriptor() argument
1132 if (image->vk.format == VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK && in si_make_texture_descriptor()
1135 } else if (image->vk.format == VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK && in si_make_texture_descriptor()
1156 radv_image_is_tc_compat_htile(image)) { in si_make_texture_descriptor()
1157 if (image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT) in si_make_texture_descriptor()
1159 else if (image->vk.format == VK_FORMAT_D16_UNORM_S8_UINT) in si_make_texture_descriptor()
1165 assert(image->vk.image_type == VK_IMAGE_TYPE_3D); in si_make_texture_descriptor()
1168 … type = radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, image->info.samples, in si_make_texture_descriptor()
1174 depth = image->info.array_size; in si_make_texture_descriptor()
1177 depth = image->info.array_size; in si_make_texture_descriptor()
1179 depth = image->info.array_size / 6; in si_make_texture_descriptor()
1190 S_008F1C_BASE_LEVEL(image->info.samples > 1 ? 0 : first_level) | in si_make_texture_descriptor()
1191 S_008F1C_LAST_LEVEL(image->info.samples > 1 ? util_logbase2(image->info.samples) in si_make_texture_descriptor()
1211 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ? util_logbase2(image->info.samples) in si_make_texture_descriptor()
1212 : image->info.levels - 1); in si_make_texture_descriptor()
1214 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1); in si_make_texture_descriptor()
1218 if (!(image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER) && in si_make_texture_descriptor()
1219 image->planes[0].surface.meta_offset) { in si_make_texture_descriptor()
1226 if (device->physical_device->rad_info.gfx_level <= GFX7 && image->info.samples <= 1) { in si_make_texture_descriptor()
1237 if (radv_image_has_fmask(image)) { in si_make_texture_descriptor()
1239 uint64_t gpu_address = radv_buffer_get_va(image->bindings[0].bo); in si_make_texture_descriptor()
1242 assert(image->plane_count == 1); in si_make_texture_descriptor()
1244 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.fmask_offset; in si_make_texture_descriptor()
1248 switch (image->info.samples) { in si_make_texture_descriptor()
1262 switch (image->info.samples) { in si_make_texture_descriptor()
1280 fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle; in si_make_texture_descriptor()
1288 … radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, 0, false, false)); in si_make_texture_descriptor()
1295 … fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode); in si_make_texture_descriptor()
1297 S_008F20_PITCH(image->planes[0].surface.u.gfx9.color.fmask_epitch); in si_make_texture_descriptor()
1300 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1301 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset; in si_make_texture_descriptor()
1309 S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.color.fmask.tiling_index); in si_make_texture_descriptor()
1312 S_008F20_PITCH(image->planes[0].surface.u.legacy.color.fmask.pitch_in_pixels - 1); in si_make_texture_descriptor()
1315 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1316 va = gpu_address + image->bindings[0].offset + image->planes[0].surface.cmask_offset; in si_make_texture_descriptor()
1328 radv_make_texture_descriptor(struct radv_device *device, struct radv_image *image, in radv_make_texture_descriptor() argument
1336 gfx10_make_texture_descriptor(device, image, is_storage_image, view_type, vk_format, mapping, in radv_make_texture_descriptor()
1340 si_make_texture_descriptor(device, image, is_storage_image, view_type, vk_format, mapping, in radv_make_texture_descriptor()
1347 radv_query_opaque_metadata(struct radv_device *device, struct radv_image *image, in radv_query_opaque_metadata() argument
1353 assert(image->plane_count == 1); in radv_query_opaque_metadata()
1355 radv_make_texture_descriptor(device, image, false, (VkImageViewType)image->vk.image_type, in radv_query_opaque_metadata()
1356 image->vk.format, &fixedmapping, 0, image->info.levels - 1, 0, in radv_query_opaque_metadata()
1357 image->info.array_size - 1, image->info.width, image->info.height, in radv_query_opaque_metadata()
1358 image->info.depth, 0.0f, desc, NULL, 0); in radv_query_opaque_metadata()
1360 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, in radv_query_opaque_metadata()
1361 0, image->planes[0].surface.blk_w, false, false, false, false, in radv_query_opaque_metadata()
1364 ac_surface_get_umd_metadata(&device->physical_device->rad_info, &image->planes[0].surface, in radv_query_opaque_metadata()
1365 image->info.levels, desc, &md->size_metadata, md->metadata); in radv_query_opaque_metadata()
1369 radv_init_metadata(struct radv_device *device, struct radv_image *image, in radv_init_metadata() argument
1372 struct radeon_surf *surface = &image->planes[0].surface; in radv_init_metadata()
1378 image->bindings[0].offset + in radv_init_metadata()
1404 radv_query_opaque_metadata(device, image, metadata); in radv_init_metadata()
1408 radv_image_override_offset_stride(struct radv_device *device, struct radv_image *image, in radv_image_override_offset_stride() argument
1411 ac_surface_override_offset_stride(&device->physical_device->rad_info, &image->planes[0].surface, in radv_image_override_offset_stride()
1412 image->info.levels, offset, stride); in radv_image_override_offset_stride()
1417 const struct radv_image *image, struct radeon_surf *surf) in radv_image_alloc_single_sample_cmask() argument
1419 if (!surf->cmask_size || surf->cmask_offset || surf->bpe > 8 || image->info.levels > 1 || in radv_image_alloc_single_sample_cmask()
1420 image->info.depth > 1 || radv_image_has_dcc(image) || in radv_image_alloc_single_sample_cmask()
1421 !radv_image_use_fast_clear_for_image(device, image) || in radv_image_alloc_single_sample_cmask()
1422 (image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)) in radv_image_alloc_single_sample_cmask()
1425 assert(image->info.storage_samples == 1); in radv_image_alloc_single_sample_cmask()
1433 radv_image_alloc_values(const struct radv_device *device, struct radv_image *image) in radv_image_alloc_values() argument
1436 if (image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) in radv_image_alloc_values()
1439 …if (radv_image_has_cmask(image) || (radv_image_has_dcc(image) && !image->support_comp_to_single)) { in radv_image_alloc_values()
1440 image->fce_pred_offset = image->size; in radv_image_alloc_values()
1441 image->size += 8 * image->info.levels; in radv_image_alloc_values()
1444 if (radv_image_use_dcc_predication(device, image)) { in radv_image_alloc_values()
1445 image->dcc_pred_offset = image->size; in radv_image_alloc_values()
1446 image->size += 8 * image->info.levels; in radv_image_alloc_values()
1449 if ((radv_image_has_dcc(image) && !image->support_comp_to_single) || in radv_image_alloc_values()
1450 radv_image_has_cmask(image) || radv_image_has_htile(image)) { in radv_image_alloc_values()
1451 image->clear_value_offset = image->size; in radv_image_alloc_values()
1452 image->size += 8 * image->info.levels; in radv_image_alloc_values()
1455 if (radv_image_is_tc_compat_htile(image) && in radv_image_alloc_values()
1461 image->tc_compat_zrange_offset = image->size; in radv_image_alloc_values()
1462 image->size += image->info.levels * 4; in radv_image_alloc_values()
1470 radv_image_is_pipe_misaligned(const struct radv_device *device, const struct radv_image *image) in radv_image_is_pipe_misaligned() argument
1473 int log2_samples = util_logbase2(image->info.samples); in radv_image_is_pipe_misaligned()
1477 for (unsigned i = 0; i < image->plane_count; ++i) { in radv_image_is_pipe_misaligned()
1478 VkFormat fmt = radv_image_get_plane_format(device->physical_device, image, i); in radv_image_is_pipe_misaligned()
1485 if (vk_format_has_depth(image->vk.format) && image->info.array_size >= 8) { in radv_image_is_pipe_misaligned()
1495 if (vk_format_has_depth(image->vk.format)) { in radv_image_is_pipe_misaligned()
1496 if (radv_image_is_tc_compat_htile(image) && overlap) { in radv_image_is_pipe_misaligned()
1507 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
1518 radv_image_is_l2_coherent(const struct radv_device *device, const struct radv_image *image) in radv_image_is_l2_coherent() argument
1522 !radv_image_is_pipe_misaligned(device, image); in radv_image_is_l2_coherent()
1524 if (image->info.samples == 1 && in radv_image_is_l2_coherent()
1525 (image->vk.usage & in radv_image_is_l2_coherent()
1527 !vk_format_has_stencil(image->vk.format)) { in radv_image_is_l2_coherent()
1543 radv_image_can_fast_clear(const struct radv_device *device, const struct radv_image *image) in radv_image_can_fast_clear() argument
1548 if (vk_format_is_color(image->vk.format)) { in radv_image_can_fast_clear()
1549 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image)) in radv_image_can_fast_clear()
1553 if (!radv_image_has_dcc(image) && device->physical_device->rad_info.family == CHIP_STONEY) in radv_image_can_fast_clear()
1556 if (!radv_image_has_htile(image)) in radv_image_can_fast_clear()
1561 if (image->vk.image_type == VK_IMAGE_TYPE_3D) in radv_image_can_fast_clear()
1571 radv_image_use_comp_to_single(const struct radv_device *device, const struct radv_image *image) in radv_image_use_comp_to_single() argument
1578 if (!radv_image_can_fast_clear(device, image)) in radv_image_use_comp_to_single()
1582 if (!radv_image_has_dcc(image)) in radv_image_use_comp_to_single()
1586 unsigned bytes_per_pixel = vk_format_get_blocksize(image->vk.format); in radv_image_use_comp_to_single()
1602 radv_image_reset_layout(const struct radv_physical_device *pdev, struct radv_image *image) in radv_image_reset_layout() argument
1604 image->size = 0; in radv_image_reset_layout()
1605 image->alignment = 1; in radv_image_reset_layout()
1607 image->tc_compatible_cmask = 0; in radv_image_reset_layout()
1608 image->fce_pred_offset = image->dcc_pred_offset = 0; in radv_image_reset_layout()
1609 image->clear_value_offset = image->tc_compat_zrange_offset = 0; in radv_image_reset_layout()
1611 unsigned plane_count = radv_get_internal_plane_count(pdev, image->vk.format); in radv_image_reset_layout()
1613 VkFormat format = radv_image_get_plane_format(pdev, image, i); in radv_image_reset_layout()
1617 uint64_t flags = image->planes[i].surface.flags; in radv_image_reset_layout()
1618 uint64_t modifier = image->planes[i].surface.modifier; in radv_image_reset_layout()
1619 memset(image->planes + i, 0, sizeof(image->planes[i])); in radv_image_reset_layout()
1621 image->planes[i].surface.flags = flags; in radv_image_reset_layout()
1622 image->planes[i].surface.modifier = modifier; in radv_image_reset_layout()
1623 image->planes[i].surface.blk_w = vk_format_get_blockwidth(format); in radv_image_reset_layout()
1624 image->planes[i].surface.blk_h = vk_format_get_blockheight(format); in radv_image_reset_layout()
1625 image->planes[i].surface.bpe = vk_format_get_blocksize(format); in radv_image_reset_layout()
1628 if (image->planes[i].surface.bpe == 3) { in radv_image_reset_layout()
1629 image->planes[i].surface.bpe = 4; in radv_image_reset_layout()
1637 struct radv_image *image) in radv_image_create_layout() argument
1643 struct ac_surf_info image_info = image->info; in radv_image_create_layout()
1644 VkResult result = radv_patch_image_from_extra_info(device, image, &create_info, &image_info); in radv_image_create_layout()
1648 assert(!mod_info || mod_info->drmFormatModifierPlaneCount >= image->plane_count); in radv_image_create_layout()
1650 radv_image_reset_layout(device->physical_device, image); in radv_image_create_layout()
1652 unsigned plane_count = radv_get_internal_plane_count(device->physical_device, image->vk.format); in radv_image_create_layout()
1658 info.width = vk_format_get_plane_width(image->vk.format, plane, info.width); in radv_image_create_layout()
1659 info.height = vk_format_get_plane_height(image->vk.format, plane, info.height); in radv_image_create_layout()
1662 image->planes[plane].surface.flags |= in radv_image_create_layout()
1666 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface); in radv_image_create_layout()
1669 if (!radv_use_dcc_for_image_late(device, image)) in radv_image_create_layout()
1670 ac_surface_zero_dcc_fields(&image->planes[0].surface); in radv_image_create_layout()
1675 &image->planes[plane].surface, image_info.storage_samples, in radv_image_create_layout()
1682 radv_image_alloc_single_sample_cmask(device, image, &image->planes[plane].surface); in radv_image_create_layout()
1685 if (mod_info->pPlaneLayouts[plane].rowPitch % image->planes[plane].surface.bpe || in radv_image_create_layout()
1690 stride = mod_info->pPlaneLayouts[plane].rowPitch / image->planes[plane].surface.bpe; in radv_image_create_layout()
1692 offset = image->disjoint ? 0 : in radv_image_create_layout()
1693 align64(image->size, 1 << image->planes[plane].surface.alignment_log2); in radv_image_create_layout()
1698 &image->planes[plane].surface, image->info.levels, in radv_image_create_layout()
1704 unsigned mem_planes = ac_surface_get_nplanes(&image->planes[plane].surface); in radv_image_create_layout()
1710 &image->planes[plane].surface, i, in radv_image_create_layout()
1716 image->size = MAX2(image->size, offset + image->planes[plane].surface.total_size); in radv_image_create_layout()
1717 image->alignment = MAX2(image->alignment, 1 << image->planes[plane].surface.alignment_log2); in radv_image_create_layout()
1719 image->planes[plane].format = in radv_image_create_layout()
1720 radv_image_get_plane_format(device->physical_device, image, plane); in radv_image_create_layout()
1723 image->tc_compatible_cmask = in radv_image_create_layout()
1724 radv_image_has_cmask(image) && radv_use_tc_compat_cmask_for_image(device, image); in radv_image_create_layout()
1726 image->l2_coherent = radv_image_is_l2_coherent(device, image); in radv_image_create_layout()
1728 image->support_comp_to_single = radv_image_use_comp_to_single(device, image); in radv_image_create_layout()
1730 radv_image_alloc_values(device, image); in radv_image_create_layout()
1732 assert(image->planes[0].surface.surf_size); in radv_image_create_layout()
1733 assert(image->planes[0].surface.modifier == DRM_FORMAT_MOD_INVALID || in radv_image_create_layout()
1734 ac_modifier_has_dcc(image->planes[0].surface.modifier) == radv_image_has_dcc(image)); in radv_image_create_layout()
1740 struct radv_image *image) in radv_destroy_image() argument
1742 if ((image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) && image->bindings[0].bo) in radv_destroy_image()
1743 device->ws->buffer_destroy(device->ws, image->bindings[0].bo); in radv_destroy_image()
1745 if (image->owned_memory != VK_NULL_HANDLE) { in radv_destroy_image()
1746 RADV_FROM_HANDLE(radv_device_memory, mem, image->owned_memory); in radv_destroy_image()
1750 vk_image_finish(&image->vk); in radv_destroy_image()
1751 vk_free2(&device->vk.alloc, pAllocator, image); in radv_destroy_image()
1755 radv_image_print_info(struct radv_device *device, struct radv_image *image) in radv_image_print_info() argument
1762 image->size, image->alignment, image->info.width, image->info.height, in radv_image_print_info()
1763 image->info.array_size, image->info.levels); in radv_image_print_info()
1764 for (unsigned i = 0; i < image->plane_count; ++i) { in radv_image_print_info()
1765 const struct radv_image_plane *plane = &image->planes[i]; in radv_image_print_info()
1823 struct radv_image *image = NULL; in radv_image_create() local
1833 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count; in radv_image_create()
1842 image = in radv_image_create()
1844 if (!image) in radv_image_create()
1847 vk_image_init(&device->vk, &image->vk, pCreateInfo); in radv_image_create()
1849 image->info.width = pCreateInfo->extent.width; in radv_image_create()
1850 image->info.height = pCreateInfo->extent.height; in radv_image_create()
1851 image->info.depth = pCreateInfo->extent.depth; in radv_image_create()
1852 image->info.samples = pCreateInfo->samples; in radv_image_create()
1853 image->info.storage_samples = pCreateInfo->samples; in radv_image_create()
1854 image->info.array_size = pCreateInfo->arrayLayers; in radv_image_create()
1855 image->info.levels = pCreateInfo->mipLevels; in radv_image_create()
1856 image->info.num_channels = vk_format_get_nr_components(format); in radv_image_create()
1858 image->plane_count = vk_format_get_plane_count(format); in radv_image_create()
1859 image->disjoint = image->plane_count > 1 && pCreateInfo->flags & VK_IMAGE_CREATE_DISJOINT_BIT; in radv_image_create()
1861 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE; in radv_image_create()
1866 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u; in radv_image_create()
1868 image->queue_family_mask |= 1u << vk_queue_to_radv(device->physical_device, in radv_image_create()
1875 image->shareable = external_info; in radv_image_create()
1876 if (!vk_format_is_depth_or_stencil(format) && !image->shareable && in radv_image_create()
1877 !(image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_ALIASED_BIT) && in radv_image_create()
1879 image->info.surf_index = &device->image_mrt_offset_counter; in radv_image_create()
1888 image->planes[plane].surface.flags = in radv_image_create()
1889 radv_get_surface_flags(device, image, plane, pCreateInfo, format); in radv_image_create()
1890 image->planes[plane].surface.modifier = modifier; in radv_image_create()
1898 *pImage = radv_image_to_handle(image); in radv_image_create()
1899 assert(!(image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)); in radv_image_create()
1903 VkResult result = radv_image_create_layout(device, *create_info, explicit_mod, image); in radv_image_create()
1905 radv_destroy_image(device, alloc, image); in radv_image_create()
1909 if (image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) { in radv_image_create()
1910 image->alignment = MAX2(image->alignment, 4096); in radv_image_create()
1911 image->size = align64(image->size, image->alignment); in radv_image_create()
1912 image->bindings[0].offset = 0; in radv_image_create()
1915 device->ws->buffer_create(device->ws, image->size, image->alignment, 0, in radv_image_create()
1917 &image->bindings[0].bo); in radv_image_create()
1919 radv_destroy_image(device, alloc, image); in radv_image_create()
1925 radv_image_print_info(device, image); in radv_image_create()
1928 *pImage = radv_image_to_handle(image); in radv_image_create()
1941 struct radv_image *image = iview->image; in radv_image_view_make_descriptor() local
1942 struct radv_image_plane *plane = &image->planes[plane_id]; in radv_image_view_make_descriptor()
1962 device, image, is_storage_image, iview->vk.view_type, vk_format, components, hw_level, in radv_image_view_make_descriptor()
1965 vk_format_get_plane_width(image->vk.format, plane_id, iview->extent.width), in radv_image_view_make_descriptor()
1966 vk_format_get_plane_height(image->vk.format, plane_id, iview->extent.height), in radv_image_view_make_descriptor()
1979 bool enable_write_compression = radv_image_use_dcc_image_stores(device, image); in radv_image_view_make_descriptor()
1982 … si_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, iview->vk.base_mip_level, in radv_image_view_make_descriptor()
2006 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask) in radv_get_aspect_format() argument
2010 return image->planes[0].format; in radv_get_aspect_format()
2012 return image->planes[1].format; in radv_get_aspect_format()
2014 return image->planes[2].format; in radv_get_aspect_format()
2016 return vk_format_stencil_only(image->vk.format); in radv_get_aspect_format()
2018 return vk_format_depth_only(image->vk.format); in radv_get_aspect_format()
2020 return vk_format_depth_only(image->vk.format); in radv_get_aspect_format()
2022 return image->vk.format; in radv_get_aspect_format()
2033 struct radv_image *image; in radv_image_view_can_fast_clear() local
2037 image = iview->image; in radv_image_view_can_fast_clear()
2040 if (!radv_image_can_fast_clear(device, image)) in radv_image_view_can_fast_clear()
2044 if (iview->vk.base_array_layer > 0 || iview->vk.layer_count != image->info.array_size) in radv_image_view_can_fast_clear()
2048 if (!radv_image_extent_compare(image, &iview->extent)) in radv_image_view_can_fast_clear()
2060 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image); in radv_image_view_init()
2074 switch (image->vk.image_type) { in radv_image_view_init()
2077 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= in radv_image_view_init()
2078 image->info.array_size); in radv_image_view_init()
2081 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= in radv_image_view_init()
2082 radv_minify(image->info.depth, range->baseMipLevel)); in radv_image_view_init()
2087 iview->image = image; in radv_image_view_init()
2093 iview->vk.format = image->vk.format; in radv_image_view_init()
2094 iview->vk.view_format = image->vk.format; in radv_image_view_init()
2108 if (vk_format_get_plane_count(image->vk.format) > 1 && in radv_image_view_init()
2114 vk_format_description(image->vk.format)->layout == UTIL_FORMAT_LAYOUT_ETC) { in radv_image_view_init()
2127 .width = image->info.width, in radv_image_view_init()
2128 .height = image->info.height, in radv_image_view_init()
2129 .depth = image->info.depth, in radv_image_view_init()
2135 if (iview->vk.format != image->planes[iview->plane_id].format) { in radv_image_view_init()
2138 unsigned img_bw = vk_format_get_blockwidth(image->planes[iview->plane_id].format); in radv_image_view_init()
2139 unsigned img_bh = vk_format_get_blockheight(image->planes[iview->plane_id].format); in radv_image_view_init()
2171 vk_format_is_compressed(image->vk.format) && !vk_format_is_compressed(iview->vk.format)) { in radv_image_view_init()
2176 iview->extent.width = iview->image->planes[0].surface.u.gfx9.base_mip_width; in radv_image_view_init()
2177 iview->extent.height = iview->image->planes[0].surface.u.gfx9.base_mip_height; in radv_image_view_init()
2179 unsigned lvl_width = radv_minify(image->info.width, range->baseMipLevel); in radv_image_view_init()
2180 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel); in radv_image_view_init()
2189 iview->image->planes[0].surface.u.gfx9.base_mip_width); in radv_image_view_init()
2191 iview->image->planes[0].surface.u.gfx9.base_mip_height); in radv_image_view_init()
2219 radv_layout_is_htile_compressed(const struct radv_device *device, const struct radv_image *image, in radv_layout_is_htile_compressed() argument
2227 return radv_image_has_htile(image); in radv_layout_is_htile_compressed()
2229 return radv_image_is_tc_compat_htile(image) || in radv_layout_is_htile_compressed()
2230 (radv_image_has_htile(image) && queue_mask == (1u << RADV_QUEUE_GENERAL)); in radv_layout_is_htile_compressed()
2243 if (radv_image_is_tc_compat_htile(image) && queue_mask & (1u << RADV_QUEUE_GENERAL) && in radv_layout_is_htile_compressed()
2255 if (radv_image_is_tc_compat_htile(image) || in radv_layout_is_htile_compressed()
2256 (radv_image_has_htile(image) && in radv_layout_is_htile_compressed()
2257 !(image->vk.usage & (VK_IMAGE_USAGE_SAMPLED_BIT | in radv_layout_is_htile_compressed()
2268 return radv_image_is_tc_compat_htile(image); in radv_layout_is_htile_compressed()
2273 radv_layout_can_fast_clear(const struct radv_device *device, const struct radv_image *image, in radv_layout_can_fast_clear() argument
2277 if (radv_dcc_enabled(image, level) && in radv_layout_can_fast_clear()
2278 !radv_layout_dcc_compressed(device, image, level, layout, in_render_loop, queue_mask)) in radv_layout_can_fast_clear()
2281 if (!(image->vk.usage & RADV_IMAGE_USAGE_WRITE_BITS)) in radv_layout_can_fast_clear()
2292 return queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_use_comp_to_single(device, image); in radv_layout_can_fast_clear()
2296 radv_layout_dcc_compressed(const struct radv_device *device, const struct radv_image *image, in radv_layout_dcc_compressed() argument
2300 if (!radv_dcc_enabled(image, level)) in radv_layout_dcc_compressed()
2303 if (image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT && in radv_layout_dcc_compressed()
2308 if (!(image->vk.usage & RADV_IMAGE_USAGE_WRITE_BITS)) in radv_layout_dcc_compressed()
2313 (queue_mask & (1u << RADV_QUEUE_COMPUTE)) && !radv_image_use_dcc_image_stores(device, image)) in radv_layout_dcc_compressed()
2327 radv_layout_fmask_compressed(const struct radv_device *device, const struct radv_image *image, in radv_layout_fmask_compressed() argument
2330 if (!radv_image_has_fmask(image)) in radv_layout_fmask_compressed()
2342 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
2346 radv_image_queue_family_mask(const struct radv_image *image, in radv_image_queue_family_mask() argument
2350 if (!image->exclusive) in radv_image_queue_family_mask()
2351 return image->queue_family_mask; in radv_image_queue_family_mask()
2389 RADV_FROM_HANDLE(radv_image, image, _image); in radv_DestroyImage()
2391 if (!image) in radv_DestroyImage()
2394 radv_destroy_image(device, pAllocator, image); in radv_DestroyImage()
2401 RADV_FROM_HANDLE(radv_image, image, _image); in radv_GetImageSubresourceLayout()
2407 if (vk_format_get_plane_count(image->vk.format) > 1) in radv_GetImageSubresourceLayout()
2410 struct radv_image_plane *plane = &image->planes[plane_id]; in radv_GetImageSubresourceLayout()
2413 if (image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) { in radv_GetImageSubresourceLayout()
2432 if (image->vk.format == VK_FORMAT_R32G32B32_UINT || in radv_GetImageSubresourceLayout()
2433 image->vk.format == VK_FORMAT_R32G32B32_SINT || in radv_GetImageSubresourceLayout()
2434 image->vk.format == VK_FORMAT_R32G32B32_SFLOAT) { in radv_GetImageSubresourceLayout()
2451 if (image->vk.image_type == VK_IMAGE_TYPE_3D) in radv_GetImageSubresourceLayout()
2452 pLayout->size *= u_minify(image->info.depth, level); in radv_GetImageSubresourceLayout()
2460 if (image->vk.image_type == VK_IMAGE_TYPE_3D) in radv_GetImageSubresourceLayout()
2461 pLayout->size *= u_minify(image->info.depth, level); in radv_GetImageSubresourceLayout()
2469 RADV_FROM_HANDLE(radv_image, image, _image); in radv_GetImageDrmFormatModifierPropertiesEXT()
2471 pProperties->drmFormatModifier = image->planes[0].surface.modifier; in radv_GetImageDrmFormatModifierPropertiesEXT()
2479 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image); in radv_CreateImageView()
2488 radv_image_view_init(view, device, pCreateInfo, image->vk.create_flags, in radv_CreateImageView()