140             (inst->alu.add.waddr == V3D_QPU_WADDR_TLB ||  in qpu_inst_is_tlb()
141              inst->alu.add.waddr == V3D_QPU_WADDR_TLBU))  in qpu_inst_is_tlb()
145             (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB ||  in qpu_inst_is_tlb()
146              inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU))  in qpu_inst_is_tlb()
173 tmu_write_is_sequence_terminator(uint32_t waddr)  in tmu_write_is_sequence_terminator()  argument
175         switch (waddr) {  in tmu_write_is_sequence_terminator()
189 can_reorder_tmu_write(const struct v3d_device_info *devinfo, uint32_t waddr)  in can_reorder_tmu_write()  argument
194         if (tmu_write_is_sequence_terminator(waddr))  in can_reorder_tmu_write()
197         if (waddr == V3D_QPU_WADDR_TMUD)  in can_reorder_tmu_write()
205                    uint32_t waddr, bool magic)  in process_waddr_deps()  argument
208                 add_write_dep(state, &state->last_rf[waddr], n);  in process_waddr_deps()
209         } else if (v3d_qpu_magic_waddr_is_tmu(state->devinfo, waddr)) {  in process_waddr_deps()
210                 if (can_reorder_tmu_write(state->devinfo, waddr))  in process_waddr_deps()
215                 if (tmu_write_is_sequence_terminator(waddr))  in process_waddr_deps()
217         } else if (v3d_qpu_magic_waddr_is_sfu(waddr)) {  in process_waddr_deps()
220                 switch (waddr) {  in process_waddr_deps()
225                                       &state->last_r[waddr - V3D_QPU_WADDR_R0],  in process_waddr_deps()
264                         fprintf(stderr, "Unknown waddr %d\n", waddr);  in process_waddr_deps()
369                 process_waddr_deps(state, n, inst->alu.add.waddr,  in calculate_deps()
373                 process_waddr_deps(state, n, inst->alu.mul.waddr,  in calculate_deps()
604                         uint32_t waddr) {  in qpu_instruction_uses_rf()  argument
610             inst->raddr_a == waddr)  in qpu_instruction_uses_rf()
614             !inst->sig.small_imm && (inst->raddr_b == waddr))  in qpu_instruction_uses_rf()
722                     v3d_qpu_magic_waddr_is_tsy(inst->alu.add.waddr)) {  in qpu_peripherals()
1278                                   enum v3d_qpu_waddr waddr,  in update_scoreboard_for_magic_waddr()  argument
1281         if (v3d_qpu_magic_waddr_is_sfu(waddr))  in update_scoreboard_for_magic_waddr()
1283         else if (devinfo->ver >= 40 && waddr == V3D_QPU_WADDR_UNIFA)  in update_scoreboard_for_magic_waddr()
1292                 scoreboard->last_stallable_sfu_reg = inst->alu.add.waddr;  in update_scoreboard_for_sfu_stall_waddr()
1310                                                           inst->alu.add.waddr,  in update_scoreboard_for_chosen()
1324                                                           inst->alu.mul.waddr,  in update_scoreboard_for_chosen()
1357                                     enum v3d_qpu_waddr waddr,  in magic_waddr_latency()  argument
1383         if (v3d_qpu_magic_waddr_is_tmu(devinfo, waddr) &&  in magic_waddr_latency()
1389         if (v3d_qpu_magic_waddr_is_sfu(waddr))  in magic_waddr_latency()
1410                                                    before_inst->alu.add.waddr,  in instruction_latency()
1417                                                    before_inst->alu.mul.waddr,  in instruction_latency()
1592             (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) ||  in qpu_inst_before_thrsw_valid_in_delay_slot()
1593              v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) {  in qpu_inst_before_thrsw_valid_in_delay_slot()
2108                     prev->qpu.alu.add.waddr == ldvary_index) {  in fixup_pipelined_ldvary()
2115                     prev->qpu.alu.mul.waddr == ldvary_index) {  in fixup_pipelined_ldvary()