Lines Matching refs:sscreen
107 static bool si_alloc_separate_cmask(struct si_screen *sscreen, struct si_texture *tex) in si_alloc_separate_cmask() argument
109 assert(sscreen->info.gfx_level < GFX11); in si_alloc_separate_cmask()
121 si_aligned_buffer_create(&sscreen->b, PIPE_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT, in si_alloc_separate_cmask()
129 p_atomic_inc(&sscreen->compressed_colortex_counter); in si_alloc_separate_cmask()
170 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format) in vi_alpha_is_on_msb() argument
174 unsigned comp_swap = si_translate_colorswap(sscreen->info.gfx_level, format, false); in vi_alpha_is_on_msb()
178 return (comp_swap == V_028C70_SWAP_ALT_REV) != (sscreen->info.family == CHIP_RAVEN2 || in vi_alpha_is_on_msb()
179 sscreen->info.family == CHIP_RENOIR); in vi_alpha_is_on_msb()
185 static bool gfx8_get_dcc_clear_parameters(struct si_screen *sscreen, enum pipe_format base_format, in gfx8_get_dcc_clear_parameters() argument
214 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, base_format); in gfx8_get_dcc_clear_parameters()
215 bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, surface_format); in gfx8_get_dcc_clear_parameters()
295 static bool gfx11_get_dcc_clear_parameters(struct si_screen *sscreen, enum pipe_format surface_form… in gfx11_get_dcc_clear_parameters() argument
385 if (vi_alpha_is_on_msb(sscreen, surface_format)) { in gfx11_get_dcc_clear_parameters()
494 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_texture *tex) in si_set_optimal_micro_tile_mode() argument
496 if (sscreen->info.gfx_level >= GFX10 || tex->buffer.b.is_shared || in si_set_optimal_micro_tile_mode()
501 assert(sscreen->info.gfx_level >= GFX9 || in si_set_optimal_micro_tile_mode()
505 if (sscreen->info.gfx_level >= GFX9) { in si_set_optimal_micro_tile_mode()
536 } else if (sscreen->info.gfx_level >= GFX7) { in si_set_optimal_micro_tile_mode()
594 p_atomic_inc(&sscreen->dirty_tex_counter); in si_set_optimal_micro_tile_mode()