Lines Matching refs:vec4_instruction
150 vec4_instruction::is_send_from_grf() const in is_send_from_grf()
187 vec4_instruction::has_source_and_destination_hazard() const in has_source_and_destination_hazard()
206 vec4_instruction::size_read(unsigned arg) const in size_read()
237 vec4_instruction::can_do_source_mods(const struct intel_device_info *devinfo) in can_do_source_mods()
252 vec4_instruction::can_do_cmod() in can_do_cmod()
272 vec4_instruction::can_do_writemask(const struct intel_device_info *devinfo) in can_do_writemask()
308 vec4_instruction::can_change_types() const in can_change_types()
327 vec4_instruction::implied_mrf_writes() const in implied_mrf_writes()
405 vec4_instruction *imm_inst[4]; in opt_vector_float()
409 foreach_inst_in_block_safe(vec4_instruction, inst, block) { in opt_vector_float()
448 vec4_instruction *mov = MOV(imm_inst[0]->dst, brw_imm_vf(vf)); in opt_vector_float()
517 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in opt_reduce_swizzle()
590 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in split_uniform_registers()
620 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in opt_algebraic()
723 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst) in is_dep_ctrl_unsafe()
780 vec4_instruction *last_grf_write[BRW_MAX_GRF]; in opt_set_dependency_control()
782 vec4_instruction *last_mrf_write[BRW_MAX_GRF]; in opt_set_dependency_control()
792 foreach_inst_in_block (vec4_instruction, inst, block) { in opt_set_dependency_control()
847 vec4_instruction::can_reswizzle(const struct intel_device_info *devinfo, in can_reswizzle()
899 vec4_instruction::reswizzle(int dst_writemask, int swizzle) in reswizzle()
956 foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) { in opt_register_coalesce()
1013 vec4_instruction *_scan_inst = (vec4_instruction *)inst->prev; in opt_register_coalesce()
1014 foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst, in opt_register_coalesce()
1145 vec4_instruction *scan_inst = _scan_inst; in opt_register_coalesce()
1167 scan_inst = (vec4_instruction *)scan_inst->next; in opt_register_coalesce()
1199 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in eliminate_find_live_channel()
1260 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in split_virtual_grfs()
1286 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in split_virtual_grfs()
1314 const vec4_instruction *inst = (const vec4_instruction *)be_inst; in dump_instruction()
1510 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in setup_attributes()
1613 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in lower_minmax()
1663 vec4_instruction *mov = emit(MOV(dst, ts)); in get_timestamp()
1673 is_align1_df(vec4_instruction *inst) in is_align1_df()
1699 foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) { in fixup_3src_null_dest()
1718 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in convert_to_hw_regs()
1868 unsigned stage, const vec4_instruction *inst) in get_lowered_simd_width()
1928 dst_src_regions_overlap(vec4_instruction *inst) in dst_src_regions_overlap()
1961 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in lower_simd_width()
1990 vec4_instruction *linst = new(mem_ctx) vec4_instruction(*inst); in lower_simd_width()
2002 vec4_instruction *copy = MOV(dst, src_reg(inst->dst)); in lower_simd_width()
2033 vec4_instruction *mov = in lower_simd_width()
2077 is_gfx7_supported_64bit_swizzle(vec4_instruction *inst, unsigned arg) in is_gfx7_supported_64bit_swizzle()
2107 vec4_visitor::is_supported_64bit_region(vec4_instruction *inst, unsigned arg) in is_supported_64bit_region()
2140 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in scalarize_df()
2183 vec4_instruction *scalar_inst = new(mem_ctx) vec4_instruction(*inst); in scalarize_df()
2215 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in lower_64bit_mad_to_mul_add()
2227 vec4_instruction *mul = new(mem_ctx) vec4_instruction(*inst); in lower_64bit_mad_to_mul_add()
2234 vec4_instruction *add = new(mem_ctx) vec4_instruction(*inst); in lower_64bit_mad_to_mul_add()
2267 vec4_instruction *inst, int arg) in apply_logical_swizzle()