Lines Matching refs:vt3
2355 const VRegister& vt3, const MemOperand& src) { in ld1() argument
2357 USE(vt3); in ld1()
2358 DCHECK(AreSameFormat(vt, vt2, vt3)); in ld1()
2359 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld1()
2364 const VRegister& vt3, const VRegister& vt4, in ld1() argument
2367 USE(vt3); in ld1()
2369 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in ld1()
2370 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld1()
2399 const VRegister& vt3, const MemOperand& src) { in ld3() argument
2401 USE(vt3); in ld3()
2402 DCHECK(AreSameFormat(vt, vt2, vt3)); in ld3()
2403 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld3()
2408 const VRegister& vt3, int lane, const MemOperand& src) { in ld3() argument
2410 USE(vt3); in ld3()
2411 DCHECK(AreSameFormat(vt, vt2, vt3)); in ld3()
2412 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld3()
2417 const VRegister& vt3, const MemOperand& src) { in ld3r() argument
2419 USE(vt3); in ld3r()
2420 DCHECK(AreSameFormat(vt, vt2, vt3)); in ld3r()
2421 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld3r()
2426 const VRegister& vt3, const VRegister& vt4, in ld4() argument
2429 USE(vt3); in ld4()
2431 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in ld4()
2432 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld4()
2437 const VRegister& vt3, const VRegister& vt4, int lane, in ld4() argument
2440 USE(vt3); in ld4()
2442 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in ld4()
2443 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld4()
2448 const VRegister& vt3, const VRegister& vt4, in ld4r() argument
2451 USE(vt3); in ld4r()
2453 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in ld4r()
2454 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld4r()
2471 const VRegister& vt3, const MemOperand& src) { in st1() argument
2473 USE(vt3); in st1()
2474 DCHECK(AreSameFormat(vt, vt2, vt3)); in st1()
2475 DCHECK(AreConsecutive(vt, vt2, vt3)); in st1()
2480 const VRegister& vt3, const VRegister& vt4, in st1() argument
2483 USE(vt3); in st1()
2485 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in st1()
2486 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in st1()
2507 const VRegister& vt3, const MemOperand& dst) { in st3() argument
2509 USE(vt3); in st3()
2510 DCHECK(AreSameFormat(vt, vt2, vt3)); in st3()
2511 DCHECK(AreConsecutive(vt, vt2, vt3)); in st3()
2516 const VRegister& vt3, int lane, const MemOperand& dst) { in st3() argument
2518 USE(vt3); in st3()
2519 DCHECK(AreSameFormat(vt, vt2, vt3)); in st3()
2520 DCHECK(AreConsecutive(vt, vt2, vt3)); in st3()
2525 const VRegister& vt3, const VRegister& vt4, in st4() argument
2528 USE(vt3); in st4()
2530 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in st4()
2531 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in st4()
2536 const VRegister& vt3, const VRegister& vt4, int lane, in st4() argument
2539 USE(vt3); in st4()
2541 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in st4()
2542 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in st4()