Lines Matching refs:Bits
153 V_(Rd, 4, 0, Bits) /* Destination register. */ \
154 V_(Rn, 9, 5, Bits) /* First source register. */ \
155 V_(Rm, 20, 16, Bits) /* Second source register. */ \
156 V_(Ra, 14, 10, Bits) /* Third source register. */ \
157 V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \
158 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \
160 V_(Rs, 20, 16, Bits) /* Store-exclusive status */ \
161 V_(PrefetchMode, 4, 0, Bits) \
164 V_(SixtyFourBits, 31, 31, Bits) \
165 V_(FlagsUpdate, 29, 29, Bits) \
169 V_(ImmPCRelLo, 30, 29, Bits) \
172 V_(ShiftDP, 23, 22, Bits) \
173 V_(ImmDPShift, 15, 10, Bits) \
176 V_(ImmAddSub, 21, 10, Bits) \
177 V_(ShiftAddSub, 23, 22, Bits) \
180 V_(ImmExtendShift, 12, 10, Bits) \
181 V_(ExtendMode, 15, 13, Bits) \
184 V_(ImmMoveWide, 20, 5, Bits) \
185 V_(ShiftMoveWide, 22, 21, Bits) \
188 V_(BitN, 22, 22, Bits) \
189 V_(ImmRotate, 21, 16, Bits) \
190 V_(ImmSetBits, 15, 10, Bits) \
191 V_(ImmR, 21, 16, Bits) \
192 V_(ImmS, 15, 10, Bits) \
196 V_(ImmTestBranchBit40, 23, 19, Bits) \
197 V_(ImmTestBranchBit5, 31, 31, Bits) \
200 V_(Condition, 15, 12, Bits) \
201 V_(ConditionBranch, 3, 0, Bits) \
202 V_(Nzcv, 3, 0, Bits) \
203 V_(ImmCondCmp, 20, 16, Bits) \
207 V_(FPType, 23, 22, Bits) \
208 V_(ImmFP, 20, 13, Bits) \
209 V_(FPScale, 15, 10, Bits) \
213 V_(ImmLSUnsigned, 21, 10, Bits) \
215 V_(ImmShiftLS, 12, 12, Bits) \
216 V_(LSOpc, 23, 22, Bits) \
217 V_(LSVector, 26, 26, Bits) \
218 V_(LSSize, 31, 30, Bits) \
221 V_(NEONQ, 30, 30, Bits) \
222 V_(NEONSize, 23, 22, Bits) \
223 V_(NEONLSSize, 11, 10, Bits) \
224 V_(NEONS, 12, 12, Bits) \
225 V_(NEONL, 21, 21, Bits) \
226 V_(NEONM, 20, 20, Bits) \
227 V_(NEONH, 11, 11, Bits) \
228 V_(ImmNEONExt, 14, 11, Bits) \
229 V_(ImmNEON5, 20, 16, Bits) \
230 V_(ImmNEON4, 14, 11, Bits) \
236 V_(ImmException, 20, 5, Bits) \
237 V_(ImmHint, 11, 5, Bits) \
238 V_(ImmBarrierDomain, 11, 10, Bits) \
239 V_(ImmBarrierType, 9, 8, Bits) \
242 V_(ImmSystemRegister, 19, 5, Bits) \
243 V_(SysO0, 19, 19, Bits) \
244 V_(SysOp1, 18, 16, Bits) \
245 V_(SysOp2, 7, 5, Bits) \
246 V_(CRn, 15, 12, Bits) \
247 V_(CRm, 11, 8, Bits) \
250 V_(LoadStoreXLoad, 22, 22, Bits) \
251 V_(LoadStoreXNotExclusive, 23, 23, Bits) \
252 V_(LoadStoreXAcquireRelease, 15, 15, Bits) \
253 V_(LoadStoreXSizeLog2, 31, 30, Bits) \
254 V_(LoadStoreXPair, 21, 21, Bits) \
257 V_(NEONLoad, 22, 22, Bits) \
260 V_(ImmNEONabc, 18, 16, Bits) \
261 V_(ImmNEONdefgh, 9, 5, Bits) \
262 V_(NEONModImmOp, 29, 29, Bits) \
263 V_(NEONCmode, 15, 12, Bits) \
266 V_(ImmNEONImmhImmb, 22, 16, Bits) \
267 V_(ImmNEONImmh, 22, 19, Bits) \
268 V_(ImmNEONImmb, 18, 16, Bits)
272 V_(Flags, 31, 28, Bits, uint32_t) \
273 V_(N, 31, 31, Bits, bool) \
274 V_(Z, 30, 30, Bits, bool) \
275 V_(C, 29, 29, Bits, bool) \
276 V_(V, 28, 28, Bits, bool) \
280 V_(AHP, 26, 26, Bits, bool) \
281 V_(DN, 25, 25, Bits, bool) \
282 V_(FZ, 24, 24, Bits, bool) \
283 V_(RMode, 23, 22, Bits, FPRounding) \