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!`$!`,!0!4!@!!(!(!a!a!!!@!@! !<!<!!!!!"( "!"($"(P"`"!<@iDaTX\aHLKPa a;aba a8<@a48<ahlqpaY a(,0aaa $aaaaNaaaa`d(halpta"ax|a2aadaGa  Ia, 04a <a a  aa $(aaaLPTaa$({,a@D{HaPTXatxp|a\`da/a#a a048aDHLal X(048@dHXPX`hpxh    L h  @<,hT (08T@HP@X`h@px,Dph,0 PH( x!<" 5L(~8DHQXh}xD-=~(V8XZhaxgTaeX(M84HX?hahtXX\ `d x @ OHOS (dev) clang version 15.0.4 (llvm-project 8e906cedd973d1a87eee9403a4c65b0dc70d0941),-./ "%(58:BGOQW\acinsx} &;<Rd-./012?DITY^fkpuz#$%  x)a $(048@,DPH P T XA`p d hyp t4 xl  d!(Y DhH8(pp\ $(0 48!8Q@!D8!H$(8<@LP0T0`dp`t`00 $(,0Al8A@qHlPpAxlGAlAolA n(l0PAX`lhAlAlAl0A8@lHhApxl8A$lAlA ("HAPX`"A"A"An"(A08@`Ahpx h(08HlPX`ppxt| 0|8 @ H P `|hH pd x |<80|X8)p8VP4P@ i% i* aH<d<i  aTT K aH2H7 R ao P P0@  ; ; a9QV bo a  a  a'8>8C a a44 q ahhT8$|* 0(60<B88ek8q@wH}000`00 0 0 |4 xP/X5LDhSl\d(i op8`08h@80$p* 0x6 FL @[pdPj8  `P8t  p8 %H :@d xTt^d8p  8h08,28<IOh8v|888 H  |T$ * 0 A6 @<  W (n t   ,   (( I `$   ) P(: V $n   x(  &        Y. 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0"""8"H"""#__ksymtab__jump_table__patchable_function_entries.plt.init.plt.text.ftrace_trampoline.text.rela.text__ksymtab_strings.rela___ksymtab+get_cpu_type_name.rela__patchable_function_entries.rodata.rela.rodata.bss.rodata.cst16.rodata.str1.1.comment.llvm_addrsig.rela__jump_table.init.text.rela.init.text.exit.text.rela.exit.text__dyndbg.rela__dyndbg__param.rela__param.modinfo.rodata.str4.4.init.data.rela.init.data.data.rela.data.note.Linux.gnu.linkonce.this_module.rela.gnu.linkonce.this_module.note.gnu.build-id.note.gnu.property.note.GNU-stack.symtab.shstrtab.strtabchips.c__kstrtab_get_cpu_type_name$d.1__kstrtabns_get_cpu_type_name__ksymtab_get_cpu_type_name$d.2__kstrtab_get_video_format_name__kstrtabns_get_video_format_name__ksymtab_get_video_format_name$d.3__kstrtab_get_current_vdec_chip__kstrtabns_get_current_vdec_chip__ksymtab_get_current_vdec_chip$d.4__kstrtab_check_efuse_chip__kstrtabns_check_efuse_chip__ksymtab_check_efuse_chip$d.5$x.6cpu_type_name$d.7vformat_type_name$d.8current_chip_info$d.9$d.10$d.11$d.13$d.14$d.15$d.16clkg12.c__kstrtab_vdec1_set_clk$d.1__kstrtabns_vdec1_set_clk__ksymtab_vdec1_set_clk$d.2__kstrtab_hcodec_set_clk__kstrtabns_hcodec_set_clk__ksymtab_hcodec_set_clk$d.3__kstrtab_vdec2_set_clk__kstrtabns_vdec2_set_clk__ksymtab_vdec2_set_clk$d.4__kstrtab_hevc_set_clk__kstrtabns_hevc_set_clk__ksymtab_hevc_set_clk$d.5__kstrtab_vdec_get_clk_source__kstrtabns_vdec_get_clk_source__ksymtab_vdec_get_clk_source$d.6__kstrtab_set_clock_gate__kstrtabns_set_clock_gate__ksymtab_set_clock_gate$d.7$x.8$d.9vdec1_set_clk.__UNIQUE_ID_ddebug309$x.10$d.11$d.12$d.13$d.14hevc_set_clk.__UNIQUE_ID_ddebug313$x.15$d.16$d.17$d.18$x.19vdec_clk_mgrvdec_hevc_clk_mgrvdec_hevc_back_clk_mgrvdec_hcodec_clk_mgrclks_for_formatsmedia_clk_driver$d.20$x.21vdec_clock_getclock_real_clk$d.22vdec_clock_init$d.23vdec_clock_setset_frq_enablevdec_frqvdec_set_clk$d.24vdec_clock_set.__UNIQUE_ID_ddebug317$x.25$d.26vdec_clock_on$d.27vdec_clock_on.__UNIQUE_ID_ddebug321$x.28$d.29vdec_clock_off$d.30vdec_clock_off.__UNIQUE_ID_ddebug322$x.31$d.32$d.33$d.34hevc_clock_init$d.35hevc_clock_sethevc_frq$d.36hevc_clock_set.__UNIQUE_ID_ddebug319$x.37$d.38hevc_clock_on$d.39hevc_clock_on.__UNIQUE_ID_ddebug325$x.40$d.41hevc_clock_off$d.42hevc_clock_off.__UNIQUE_ID_ddebug326$x.43$d.44hevc_back_clock_init$d.45hevc_back_clock_sethevcb_frq$d.46hevc_back_clock_set.__UNIQUE_ID_ddebug318$x.47$d.48hevc_back_clock_on$d.49hevc_back_clock_on.__UNIQUE_ID_ddebug327$x.50$d.51hevc_back_clock_off$d.52hevc_back_clock_off.__UNIQUE_ID_ddebug328$x.53$d.54hcodec_clock_set$d.55hcodec_clock_set.__UNIQUE_ID_ddebug320$x.56$d.57hcodec_clock_on$d.58hcodec_clock_on.__UNIQUE_ID_ddebug323$x.59$d.60hcodec_clock_off$d.61hcodec_clock_off.__UNIQUE_ID_ddebug324$x.62$d.63media_clk_probe$d.64$d.65$d.66$d.68__param_str_set_frq_enable__param_set_frq_enable$d.69__UNIQUE_ID_set_frq_enabletype333$d.70__UNIQUE_ID_set_frq_enable334__param_str_vdec_frq__param_vdec_frq__UNIQUE_ID_vdec_frqtype335__UNIQUE_ID_vdec_frq336__param_str_hevc_frq__param_hevc_frq__UNIQUE_ID_hevc_frqtype337__UNIQUE_ID_hevc_frq338__param_str_hevcb_frq__param_hevcb_frq__UNIQUE_ID_hevcb_frqtype339__UNIQUE_ID_hevcb_frq340__UNIQUE_ID_license341$d.71$d.72$d.73media_clk_dt_match$d.74clk.c__kstrtab_vdec_clock_init$d.1__kstrtabns_vdec_clock_init__ksymtab_vdec_clock_init$d.2__kstrtab_vdec_clock_set__kstrtabns_vdec_clock_set__ksymtab_vdec_clock_set$d.3__kstrtab_vdec_clock_enable__kstrtabns_vdec_clock_enable__ksymtab_vdec_clock_enable$d.4__kstrtab_vdec_clock_hi_enable__kstrtabns_vdec_clock_hi_enable__ksymtab_vdec_clock_hi_enable$d.5__kstrtab_vdec_clock_on__kstrtabns_vdec_clock_on__ksymtab_vdec_clock_on$d.6__kstrtab_vdec_clock_off__kstrtabns_vdec_clock_off__ksymtab_vdec_clock_off$d.7__kstrtab_vdec2_clock_set__kstrtabns_vdec2_clock_set__ksymtab_vdec2_clock_set$d.8__kstrtab_vdec2_clock_enable__kstrtabns_vdec2_clock_enable__ksymtab_vdec2_clock_enable$d.9__kstrtab_vdec2_clock_hi_enable__kstrtabns_vdec2_clock_hi_enable__ksymtab_vdec2_clock_hi_enable$d.10__kstrtab_vdec2_clock_on__kstrtabns_vdec2_clock_on__ksymtab_vdec2_clock_on$d.11__kstrtab_vdec2_clock_off__kstrtabns_vdec2_clock_off__ksymtab_vdec2_clock_off$d.12__kstrtab_hcodec_clock_set__kstrtabns_hcodec_clock_set__ksymtab_hcodec_clock_set$d.13__kstrtab_hcodec_clock_enable__kstrtabns_hcodec_clock_enable__ksymtab_hcodec_clock_enable$d.14__kstrtab_hcodec_clock_hi_enable__kstrtabns_hcodec_clock_hi_enable__ksymtab_hcodec_clock_hi_enable$d.15__kstrtab_hcodec_clock_on__kstrtabns_hcodec_clock_on__ksymtab_hcodec_clock_on$d.16__kstrtab_hcodec_clock_off__kstrtabns_hcodec_clock_off__ksymtab_hcodec_clock_off$d.17__kstrtab_hevc_back_clock_init__kstrtabns_hevc_back_clock_init__ksymtab_hevc_back_clock_init$d.18__kstrtab_hevc_back_clock_set__kstrtabns_hevc_back_clock_set__ksymtab_hevc_back_clock_set$d.19__kstrtab_hevc_back_clock_enable__kstrtabns_hevc_back_clock_enable__ksymtab_hevc_back_clock_enable$d.20__kstrtab_hevc_back_clock_hi_enable__kstrtabns_hevc_back_clock_hi_enable__ksymtab_hevc_back_clock_hi_enable$d.21__kstrtab_hevc_clock_init__kstrtabns_hevc_clock_init__ksymtab_hevc_clock_init$d.22__kstrtab_hevc_clock_set__kstrtabns_hevc_clock_set__ksymtab_hevc_clock_set$d.23__kstrtab_hevc_clock_enable__kstrtabns_hevc_clock_enable__ksymtab_hevc_clock_enable$d.24__kstrtab_hevc_clock_hi_enable__kstrtabns_hevc_clock_hi_enable__ksymtab_hevc_clock_hi_enable$d.25__kstrtab_hevc_back_clock_on__kstrtabns_hevc_back_clock_on__ksymtab_hevc_back_clock_on$d.26__kstrtab_hevc_back_clock_off__kstrtabns_hevc_back_clock_off__ksymtab_hevc_back_clock_off$d.27__kstrtab_hevc_clock_on__kstrtabns_hevc_clock_on__ksymtab_hevc_clock_on$d.28__kstrtab_hevc_clock_off__kstrtabns_hevc_clock_off__ksymtab_hevc_clock_off$d.29__kstrtab_vdec_source_get__kstrtabns_vdec_source_get__ksymtab_vdec_source_get$d.30__kstrtab_vdec_clk_get__kstrtabns_vdec_clk_get__ksymtab_vdec_clk_get$d.31__kstrtab_get_clk_with_source__kstrtabns_get_clk_with_source__ksymtab_get_clk_with_source$d.32__kstrtab_vdec_source_changed_for_clk_set__kstrtabns_vdec_source_changed_for_clk_set__ksymtab_vdec_source_changed_for_clk_set$d.33__kstrtab_register_vdec_clk_mgr__kstrtabns_register_vdec_clk_mgr__ksymtab_register_vdec_clk_mgr$d.34__kstrtab_unregister_vdec_clk_mgr__kstrtabns_unregister_vdec_clk_mgr__ksymtab_unregister_vdec_clk_mgr$d.35__kstrtab_register_vdec_clk_setting__kstrtabns_register_vdec_clk_setting__ksymtab_register_vdec_clk_setting$d.36__kstrtab_unregister_vdec_clk_setting__kstrtabns_unregister_vdec_clk_setting__ksymtab_unregister_vdec_clk_setting$d.37$x.38$d.39$d.40vdec_clock_set.__UNIQUE_ID_ddebug314$x.41$d.42$d.43$d.44$d.45clock_source_wxhxfps_saved$d.46$d.47vdec2_clock_set.__UNIQUE_ID_ddebug320$x.48$d.49$d.50$d.51$d.52$d.53$d.54hcodec_clock_set.__UNIQUE_ID_ddebug326$x.55$d.56$d.57$d.58$d.59$d.60$d.61$d.62hevc_back_clock_set.__UNIQUE_ID_ddebug333$x.63$d.64$d.65$d.66$d.67$d.68hevc_clock_set.__UNIQUE_ID_ddebug338$x.69$d.70$d.71$d.72$d.73$d.74$d.75$d.76$d.77$d.78$d.79$d.80$d.81$d.82$d.83$d.84$d.86$d.87$d.88$d.89amports_gate.c__kstrtab_amports_clock_gate_init$d.1__kstrtabns_amports_clock_gate_init__ksymtab_amports_clock_gate_init$d.2__kstrtab_amports_switch_gate__kstrtabns_amports_switch_gate__ksymtab_amports_switch_gate$d.3$x.4amports_clock_gate_init.__key$d.5amports_gate_clk.__UNIQUE_ID_ddebug314$d.6$x.7$d.8amports_gate_clk.__UNIQUE_ID_ddebug315$x.9$d.10$d.11$d.12$d.13$d.15$d.16decoder_cpu_ver_info.c__kstrtab_get_cpu_major_id$d.1__kstrtabns_get_cpu_major_id__ksymtab_get_cpu_major_id$d.2__kstrtab_is_cpu_tm2_revb__kstrtabns_is_cpu_tm2_revb__ksymtab_is_cpu_tm2_revb$d.3$x.4cpu_ver_idcpu_ver_of_match$d.5$d.6$d.7$d.9$d.10cpu_ver_info$d.11media_clock.mod.c_note_7$d.1__UNIQUE_ID_vermagic263$d.2__UNIQUE_ID_name264$d.3__UNIQUE_ID_depends265$d.4get_cpu_type_nameget_video_format_nameget_current_vdec_chipcheck_efuse_chipget_cpu_major_idcodec_reg_readvdec1_set_clkhcodec_set_clkvdec2_set_clkhevc_set_clkvdec_get_clk_sourceset_clock_gate__dynamic_pr_debugcodec_reg_writeforce_hevc_clock_cntlprintkgclkstrcmpinit_modulememcpyregister_vdec_clk_mgrregister_vdec_clk_setting__this_module__platform_driver_register__stack_chk_failcleanup_moduleunregister_vdec_clk_mgrunregister_vdec_clk_settingclk_get_ratemutex_lockclk_prepareclk_enableclk_unpreparemutex_unlockclk_disableclk_set_rateamports_clock_gate_initparam_ops_uintvdec_clock_initvdec_clock_setvdec_clock_enablevdec_clock_hi_enablevdec_clock_onvdec_clock_offvdec2_clock_setvdec2_clock_enablevdec2_clock_hi_enablevdec2_clock_onvdec2_clock_offhcodec_clock_sethcodec_clock_enablehcodec_clock_hi_enablehcodec_clock_onhcodec_clock_offhevc_back_clock_inithevc_back_clock_sethevc_back_clock_enablehevc_back_clock_hi_enablehevc_clock_inithevc_clock_sethevc_clock_enablehevc_clock_hi_enablehevc_back_clock_onhevc_back_clock_offhevc_clock_onhevc_clock_offvdec_source_getvdec_clk_getget_clk_with_sourcevdec_source_changed_for_clk_setkmalloc_cacheskmem_cache_alloc_tracekfree__kmallocamports_switch_gategatesdevm_clk_get__mutex_initis_cpu_tm2_revbof_find_node_by_nameof_find_device_by_nodeof_match_deviceget_meson_cpu_version@X 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