/third_party/vixl/test/aarch32/ |
D | test-assembler-aarch32.cc | 241 __ Adds(r0, r0, 0); in TEST() local 269 __ Adds(r0, r4, r1); in TEST() local 295 __ Adds(r0, r0, 0); in TEST() local 310 __ Adds(r0, r0, 0); in TEST() local 325 __ Adds(r0, r0, 0); in TEST() local 340 __ Adds(r0, r0, 0); in TEST() local 355 __ Adds(r0, r0, 0); in TEST() local 370 __ Adds(r0, r0, 0); in TEST() local 385 __ Adds(r0, r1, r2); in TEST() local 403 __ Adds(r0, r0, 0); in TEST() local [all …]
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMParallelDSP.cpp | 89 SetVector<Instruction*> Adds; member in __anon1db754740111::Reduction
|
/third_party/vixl/test/aarch64/ |
D | test-assembler-aarch64.cc | 66 __ Adds(x3, x0, 0x18001); in TEST() local 67 __ Adds(w4, w0, 0xffffff1); in TEST() local 87 __ Adds(x14, sp, 0x1f7de); in TEST() local 5229 __ Adds(x0, x0, Operand(0)); in TEST() local 5294 __ Adds(x0, x0, Operand(0)); in TEST() local 5349 __ Adds(x0, x0, Operand(0)); in TEST() local 5363 __ Adds(x0, x0, Operand(0)); in TEST() local 5376 __ Adds(x0, x0, Operand(0)); in TEST() local 5395 __ Adds(x0, x0, Operand(0)); in TEST() local 5544 __ Adds(x0, x0, Operand(0)); in TEST() local [all …]
|
/third_party/node/deps/v8/src/compiler/backend/arm64/ |
D | code-generator-arm64.cc | 1113 __ Adds(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local 1122 __ Adds(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
|
/third_party/node/deps/v8/src/codegen/arm64/ |
D | macro-assembler-arm64-inl.h | 125 void TurboAssembler::Adds(const Register& rd, const Register& rn, in Adds() function
|
/third_party/vixl/src/aarch64/ |
D | macro-assembler-aarch64.cc | 1499 void MacroAssembler::Adds(const Register& rd, in Emit() function in vixl::aarch64::MacroAssembler
|
/third_party/vixl/src/aarch32/ |
D | macro-assembler-aarch32.h | 1283 void Adds(Condition cond, Register rd, Register rn, const Operand& operand) { in Assembler() function 1297 void Adds(Register rd, Register rn, const Operand& operand) { in Assembler() function
|