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1 // Copyright 2015, VIXL authors
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 //   * Redistributions of source code must retain the above copyright notice,
8 //     this list of conditions and the following disclaimer.
9 //   * Redistributions in binary form must reproduce the above copyright notice,
10 //     this list of conditions and the following disclaimer in the documentation
11 //     and/or other materials provided with the distribution.
12 //   * Neither the name of ARM Limited nor the names of its contributors may be
13 //     used to endorse or promote products derived from this software without
14 //     specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 
27 #include "instructions-aarch64.h"
28 #include "assembler-aarch64.h"
29 
30 namespace vixl {
31 namespace aarch64 {
32 
RepeatBitsAcrossReg(unsigned reg_size,uint64_t value,unsigned width)33 static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
34                                     uint64_t value,
35                                     unsigned width) {
36   VIXL_ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
37               (width == 32));
38   VIXL_ASSERT((reg_size == kBRegSize) || (reg_size == kHRegSize) ||
39               (reg_size == kSRegSize) || (reg_size == kDRegSize));
40   uint64_t result = value & ((UINT64_C(1) << width) - 1);
41   for (unsigned i = width; i < reg_size; i *= 2) {
42     result |= (result << i);
43   }
44   return result;
45 }
46 
CanTakeSVEMovprfx(const char * form,const Instruction * movprfx) const47 bool Instruction::CanTakeSVEMovprfx(const char* form,
48                                     const Instruction* movprfx) const {
49   return CanTakeSVEMovprfx(Hash(form), movprfx);
50 }
51 
CanTakeSVEMovprfx(uint32_t form_hash,const Instruction * movprfx) const52 bool Instruction::CanTakeSVEMovprfx(uint32_t form_hash,
53                                     const Instruction* movprfx) const {
54   bool movprfx_is_predicated = movprfx->Mask(SVEMovprfxMask) == MOVPRFX_z_p_z;
55   bool movprfx_is_unpredicated =
56       movprfx->Mask(SVEConstructivePrefix_UnpredicatedMask) == MOVPRFX_z_z;
57   VIXL_ASSERT(movprfx_is_predicated != movprfx_is_unpredicated);
58 
59   int movprfx_zd = movprfx->GetRd();
60   int movprfx_pg = movprfx_is_predicated ? movprfx->GetPgLow8() : -1;
61   VectorFormat movprfx_vform =
62       movprfx_is_predicated ? movprfx->GetSVEVectorFormat() : kFormatUndefined;
63 
64   bool pg_matches_low8 = movprfx_pg == GetPgLow8();
65   bool vform_matches = movprfx_vform == GetSVEVectorFormat();
66   bool zd_matches = movprfx_zd == GetRd();
67   bool zd_isnt_zn = movprfx_zd != GetRn();
68   bool zd_isnt_zm = movprfx_zd != GetRm();
69 
70   switch (form_hash) {
71     case Hash("cdot_z_zzzi_s"):
72     case Hash("sdot_z_zzzi_s"):
73     case Hash("sudot_z_zzzi_s"):
74     case Hash("udot_z_zzzi_s"):
75     case Hash("usdot_z_zzzi_s"):
76       return (GetRd() != static_cast<int>(ExtractBits(18, 16))) &&
77              movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
78 
79     case Hash("cdot_z_zzzi_d"):
80     case Hash("sdot_z_zzzi_d"):
81     case Hash("udot_z_zzzi_d"):
82       return (GetRd() != static_cast<int>(ExtractBits(19, 16))) &&
83              movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
84 
85     case Hash("fmlalb_z_zzzi_s"):
86     case Hash("fmlalt_z_zzzi_s"):
87     case Hash("fmlslb_z_zzzi_s"):
88     case Hash("fmlslt_z_zzzi_s"):
89     case Hash("smlalb_z_zzzi_d"):
90     case Hash("smlalb_z_zzzi_s"):
91     case Hash("smlalt_z_zzzi_d"):
92     case Hash("smlalt_z_zzzi_s"):
93     case Hash("smlslb_z_zzzi_d"):
94     case Hash("smlslb_z_zzzi_s"):
95     case Hash("smlslt_z_zzzi_d"):
96     case Hash("smlslt_z_zzzi_s"):
97     case Hash("sqdmlalb_z_zzzi_d"):
98     case Hash("sqdmlalb_z_zzzi_s"):
99     case Hash("sqdmlalt_z_zzzi_d"):
100     case Hash("sqdmlalt_z_zzzi_s"):
101     case Hash("sqdmlslb_z_zzzi_d"):
102     case Hash("sqdmlslb_z_zzzi_s"):
103     case Hash("sqdmlslt_z_zzzi_d"):
104     case Hash("sqdmlslt_z_zzzi_s"):
105     case Hash("umlalb_z_zzzi_d"):
106     case Hash("umlalb_z_zzzi_s"):
107     case Hash("umlalt_z_zzzi_d"):
108     case Hash("umlalt_z_zzzi_s"):
109     case Hash("umlslb_z_zzzi_d"):
110     case Hash("umlslb_z_zzzi_s"):
111     case Hash("umlslt_z_zzzi_d"):
112     case Hash("umlslt_z_zzzi_s"):
113       return (GetRd() != GetSVEMulLongZmAndIndex().first) &&
114              movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
115 
116     case Hash("cmla_z_zzzi_h"):
117     case Hash("cmla_z_zzzi_s"):
118     case Hash("fcmla_z_zzzi_h"):
119     case Hash("fcmla_z_zzzi_s"):
120     case Hash("fmla_z_zzzi_d"):
121     case Hash("fmla_z_zzzi_h"):
122     case Hash("fmla_z_zzzi_s"):
123     case Hash("fmls_z_zzzi_d"):
124     case Hash("fmls_z_zzzi_h"):
125     case Hash("fmls_z_zzzi_s"):
126     case Hash("mla_z_zzzi_d"):
127     case Hash("mla_z_zzzi_h"):
128     case Hash("mla_z_zzzi_s"):
129     case Hash("mls_z_zzzi_d"):
130     case Hash("mls_z_zzzi_h"):
131     case Hash("mls_z_zzzi_s"):
132     case Hash("sqrdcmlah_z_zzzi_h"):
133     case Hash("sqrdcmlah_z_zzzi_s"):
134     case Hash("sqrdmlah_z_zzzi_d"):
135     case Hash("sqrdmlah_z_zzzi_h"):
136     case Hash("sqrdmlah_z_zzzi_s"):
137     case Hash("sqrdmlsh_z_zzzi_d"):
138     case Hash("sqrdmlsh_z_zzzi_h"):
139     case Hash("sqrdmlsh_z_zzzi_s"):
140       return (GetRd() != GetSVEMulZmAndIndex().first) &&
141              movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
142 
143     case Hash("adclb_z_zzz"):
144     case Hash("adclt_z_zzz"):
145     case Hash("bcax_z_zzz"):
146     case Hash("bsl1n_z_zzz"):
147     case Hash("bsl2n_z_zzz"):
148     case Hash("bsl_z_zzz"):
149     case Hash("cdot_z_zzz"):
150     case Hash("cmla_z_zzz"):
151     case Hash("eor3_z_zzz"):
152     case Hash("eorbt_z_zz"):
153     case Hash("eortb_z_zz"):
154     case Hash("fmlalb_z_zzz"):
155     case Hash("fmlalt_z_zzz"):
156     case Hash("fmlslb_z_zzz"):
157     case Hash("fmlslt_z_zzz"):
158     case Hash("nbsl_z_zzz"):
159     case Hash("saba_z_zzz"):
160     case Hash("sabalb_z_zzz"):
161     case Hash("sabalt_z_zzz"):
162     case Hash("sbclb_z_zzz"):
163     case Hash("sbclt_z_zzz"):
164     case Hash("sdot_z_zzz"):
165     case Hash("smlalb_z_zzz"):
166     case Hash("smlalt_z_zzz"):
167     case Hash("smlslb_z_zzz"):
168     case Hash("smlslt_z_zzz"):
169     case Hash("sqdmlalb_z_zzz"):
170     case Hash("sqdmlalbt_z_zzz"):
171     case Hash("sqdmlalt_z_zzz"):
172     case Hash("sqdmlslb_z_zzz"):
173     case Hash("sqdmlslbt_z_zzz"):
174     case Hash("sqdmlslt_z_zzz"):
175     case Hash("sqrdcmlah_z_zzz"):
176     case Hash("sqrdmlah_z_zzz"):
177     case Hash("sqrdmlsh_z_zzz"):
178     case Hash("uaba_z_zzz"):
179     case Hash("uabalb_z_zzz"):
180     case Hash("uabalt_z_zzz"):
181     case Hash("udot_z_zzz"):
182     case Hash("umlalb_z_zzz"):
183     case Hash("umlalt_z_zzz"):
184     case Hash("umlslb_z_zzz"):
185     case Hash("umlslt_z_zzz"):
186     case Hash("usdot_z_zzz_s"):
187     case Hash("fmmla_z_zzz_s"):
188     case Hash("fmmla_z_zzz_d"):
189     case Hash("smmla_z_zzz"):
190     case Hash("ummla_z_zzz"):
191     case Hash("usmmla_z_zzz"):
192       return movprfx_is_unpredicated && zd_isnt_zm && zd_isnt_zn && zd_matches;
193 
194     case Hash("addp_z_p_zz"):
195     case Hash("cadd_z_zz"):
196     case Hash("clasta_z_p_zz"):
197     case Hash("clastb_z_p_zz"):
198     case Hash("decd_z_zs"):
199     case Hash("dech_z_zs"):
200     case Hash("decw_z_zs"):
201     case Hash("faddp_z_p_zz"):
202     case Hash("fmaxnmp_z_p_zz"):
203     case Hash("fmaxp_z_p_zz"):
204     case Hash("fminnmp_z_p_zz"):
205     case Hash("fminp_z_p_zz"):
206     case Hash("ftmad_z_zzi"):
207     case Hash("incd_z_zs"):
208     case Hash("inch_z_zs"):
209     case Hash("incw_z_zs"):
210     case Hash("insr_z_v"):
211     case Hash("smaxp_z_p_zz"):
212     case Hash("sminp_z_p_zz"):
213     case Hash("splice_z_p_zz_con"):
214     case Hash("splice_z_p_zz_des"):
215     case Hash("sqcadd_z_zz"):
216     case Hash("sqdecd_z_zs"):
217     case Hash("sqdech_z_zs"):
218     case Hash("sqdecw_z_zs"):
219     case Hash("sqincd_z_zs"):
220     case Hash("sqinch_z_zs"):
221     case Hash("sqincw_z_zs"):
222     case Hash("srsra_z_zi"):
223     case Hash("ssra_z_zi"):
224     case Hash("umaxp_z_p_zz"):
225     case Hash("uminp_z_p_zz"):
226     case Hash("uqdecd_z_zs"):
227     case Hash("uqdech_z_zs"):
228     case Hash("uqdecw_z_zs"):
229     case Hash("uqincd_z_zs"):
230     case Hash("uqinch_z_zs"):
231     case Hash("uqincw_z_zs"):
232     case Hash("ursra_z_zi"):
233     case Hash("usra_z_zi"):
234     case Hash("xar_z_zzi"):
235       return movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
236 
237     case Hash("add_z_zi"):
238     case Hash("and_z_zi"):
239     case Hash("decp_z_p_z"):
240     case Hash("eor_z_zi"):
241     case Hash("incp_z_p_z"):
242     case Hash("insr_z_r"):
243     case Hash("mul_z_zi"):
244     case Hash("orr_z_zi"):
245     case Hash("smax_z_zi"):
246     case Hash("smin_z_zi"):
247     case Hash("sqadd_z_zi"):
248     case Hash("sqdecp_z_p_z"):
249     case Hash("sqincp_z_p_z"):
250     case Hash("sqsub_z_zi"):
251     case Hash("sub_z_zi"):
252     case Hash("subr_z_zi"):
253     case Hash("umax_z_zi"):
254     case Hash("umin_z_zi"):
255     case Hash("uqadd_z_zi"):
256     case Hash("uqdecp_z_p_z"):
257     case Hash("uqincp_z_p_z"):
258     case Hash("uqsub_z_zi"):
259       return movprfx_is_unpredicated && zd_matches;
260 
261     case Hash("cpy_z_p_i"):
262       if (movprfx_is_predicated) {
263         if (!vform_matches) return false;
264         if (movprfx_pg != GetRx<19, 16>()) return false;
265       }
266       // Only the merging form can take movprfx.
267       if (ExtractBit(14) == 0) return false;
268       return zd_matches;
269 
270     case Hash("fcpy_z_p_i"):
271       return (movprfx_is_unpredicated ||
272               ((movprfx_pg == GetRx<19, 16>()) && vform_matches)) &&
273              zd_matches;
274 
275     case Hash("flogb_z_p_z"):
276       return (movprfx_is_unpredicated ||
277               ((movprfx_vform == GetSVEVectorFormat(17)) && pg_matches_low8)) &&
278              zd_isnt_zn && zd_matches;
279 
280     case Hash("asr_z_p_zi"):
281     case Hash("asrd_z_p_zi"):
282     case Hash("lsl_z_p_zi"):
283     case Hash("lsr_z_p_zi"):
284     case Hash("sqshl_z_p_zi"):
285     case Hash("sqshlu_z_p_zi"):
286     case Hash("srshr_z_p_zi"):
287     case Hash("uqshl_z_p_zi"):
288     case Hash("urshr_z_p_zi"):
289       return (movprfx_is_unpredicated ||
290               ((movprfx_vform ==
291                 SVEFormatFromLaneSizeInBytesLog2(
292                     GetSVEImmShiftAndLaneSizeLog2(true).second)) &&
293                pg_matches_low8)) &&
294              zd_matches;
295 
296     case Hash("fcvt_z_p_z_d2h"):
297     case Hash("fcvt_z_p_z_d2s"):
298     case Hash("fcvt_z_p_z_h2d"):
299     case Hash("fcvt_z_p_z_s2d"):
300     case Hash("fcvtx_z_p_z_d2s"):
301     case Hash("fcvtzs_z_p_z_d2w"):
302     case Hash("fcvtzs_z_p_z_d2x"):
303     case Hash("fcvtzs_z_p_z_fp162x"):
304     case Hash("fcvtzs_z_p_z_s2x"):
305     case Hash("fcvtzu_z_p_z_d2w"):
306     case Hash("fcvtzu_z_p_z_d2x"):
307     case Hash("fcvtzu_z_p_z_fp162x"):
308     case Hash("fcvtzu_z_p_z_s2x"):
309     case Hash("scvtf_z_p_z_w2d"):
310     case Hash("scvtf_z_p_z_x2d"):
311     case Hash("scvtf_z_p_z_x2fp16"):
312     case Hash("scvtf_z_p_z_x2s"):
313     case Hash("ucvtf_z_p_z_w2d"):
314     case Hash("ucvtf_z_p_z_x2d"):
315     case Hash("ucvtf_z_p_z_x2fp16"):
316     case Hash("ucvtf_z_p_z_x2s"):
317       return (movprfx_is_unpredicated ||
318               ((movprfx_vform == kFormatVnD) && pg_matches_low8)) &&
319              zd_isnt_zn && zd_matches;
320 
321     case Hash("fcvtzs_z_p_z_fp162h"):
322     case Hash("fcvtzu_z_p_z_fp162h"):
323     case Hash("scvtf_z_p_z_h2fp16"):
324     case Hash("ucvtf_z_p_z_h2fp16"):
325       return (movprfx_is_unpredicated ||
326               ((movprfx_vform == kFormatVnH) && pg_matches_low8)) &&
327              zd_isnt_zn && zd_matches;
328 
329     case Hash("fcvt_z_p_z_h2s"):
330     case Hash("fcvt_z_p_z_s2h"):
331     case Hash("fcvtzs_z_p_z_fp162w"):
332     case Hash("fcvtzs_z_p_z_s2w"):
333     case Hash("fcvtzu_z_p_z_fp162w"):
334     case Hash("fcvtzu_z_p_z_s2w"):
335     case Hash("scvtf_z_p_z_w2fp16"):
336     case Hash("scvtf_z_p_z_w2s"):
337     case Hash("ucvtf_z_p_z_w2fp16"):
338     case Hash("ucvtf_z_p_z_w2s"):
339       return (movprfx_is_unpredicated ||
340               ((movprfx_vform == kFormatVnS) && pg_matches_low8)) &&
341              zd_isnt_zn && zd_matches;
342 
343     case Hash("fcmla_z_p_zzz"):
344     case Hash("fmad_z_p_zzz"):
345     case Hash("fmla_z_p_zzz"):
346     case Hash("fmls_z_p_zzz"):
347     case Hash("fmsb_z_p_zzz"):
348     case Hash("fnmad_z_p_zzz"):
349     case Hash("fnmla_z_p_zzz"):
350     case Hash("fnmls_z_p_zzz"):
351     case Hash("fnmsb_z_p_zzz"):
352     case Hash("mad_z_p_zzz"):
353     case Hash("mla_z_p_zzz"):
354     case Hash("mls_z_p_zzz"):
355     case Hash("msb_z_p_zzz"):
356       return (movprfx_is_unpredicated || (pg_matches_low8 && vform_matches)) &&
357              zd_isnt_zm && zd_isnt_zn && zd_matches;
358 
359     case Hash("abs_z_p_z"):
360     case Hash("add_z_p_zz"):
361     case Hash("and_z_p_zz"):
362     case Hash("asr_z_p_zw"):
363     case Hash("asr_z_p_zz"):
364     case Hash("asrr_z_p_zz"):
365     case Hash("bic_z_p_zz"):
366     case Hash("cls_z_p_z"):
367     case Hash("clz_z_p_z"):
368     case Hash("cnot_z_p_z"):
369     case Hash("cnt_z_p_z"):
370     case Hash("cpy_z_p_v"):
371     case Hash("eor_z_p_zz"):
372     case Hash("fabd_z_p_zz"):
373     case Hash("fabs_z_p_z"):
374     case Hash("fadd_z_p_zz"):
375     case Hash("fcadd_z_p_zz"):
376     case Hash("fdiv_z_p_zz"):
377     case Hash("fdivr_z_p_zz"):
378     case Hash("fmax_z_p_zz"):
379     case Hash("fmaxnm_z_p_zz"):
380     case Hash("fmin_z_p_zz"):
381     case Hash("fminnm_z_p_zz"):
382     case Hash("fmul_z_p_zz"):
383     case Hash("fmulx_z_p_zz"):
384     case Hash("fneg_z_p_z"):
385     case Hash("frecpx_z_p_z"):
386     case Hash("frinta_z_p_z"):
387     case Hash("frinti_z_p_z"):
388     case Hash("frintm_z_p_z"):
389     case Hash("frintn_z_p_z"):
390     case Hash("frintp_z_p_z"):
391     case Hash("frintx_z_p_z"):
392     case Hash("frintz_z_p_z"):
393     case Hash("fscale_z_p_zz"):
394     case Hash("fsqrt_z_p_z"):
395     case Hash("fsub_z_p_zz"):
396     case Hash("fsubr_z_p_zz"):
397     case Hash("lsl_z_p_zw"):
398     case Hash("lsl_z_p_zz"):
399     case Hash("lslr_z_p_zz"):
400     case Hash("lsr_z_p_zw"):
401     case Hash("lsr_z_p_zz"):
402     case Hash("lsrr_z_p_zz"):
403     case Hash("mul_z_p_zz"):
404     case Hash("neg_z_p_z"):
405     case Hash("not_z_p_z"):
406     case Hash("orr_z_p_zz"):
407     case Hash("rbit_z_p_z"):
408     case Hash("revb_z_z"):
409     case Hash("revh_z_z"):
410     case Hash("revw_z_z"):
411     case Hash("sabd_z_p_zz"):
412     case Hash("sadalp_z_p_z"):
413     case Hash("sdiv_z_p_zz"):
414     case Hash("sdivr_z_p_zz"):
415     case Hash("shadd_z_p_zz"):
416     case Hash("shsub_z_p_zz"):
417     case Hash("shsubr_z_p_zz"):
418     case Hash("smax_z_p_zz"):
419     case Hash("smin_z_p_zz"):
420     case Hash("smulh_z_p_zz"):
421     case Hash("sqabs_z_p_z"):
422     case Hash("sqadd_z_p_zz"):
423     case Hash("sqneg_z_p_z"):
424     case Hash("sqrshl_z_p_zz"):
425     case Hash("sqrshlr_z_p_zz"):
426     case Hash("sqshl_z_p_zz"):
427     case Hash("sqshlr_z_p_zz"):
428     case Hash("sqsub_z_p_zz"):
429     case Hash("sqsubr_z_p_zz"):
430     case Hash("srhadd_z_p_zz"):
431     case Hash("srshl_z_p_zz"):
432     case Hash("srshlr_z_p_zz"):
433     case Hash("sub_z_p_zz"):
434     case Hash("subr_z_p_zz"):
435     case Hash("suqadd_z_p_zz"):
436     case Hash("sxtb_z_p_z"):
437     case Hash("sxth_z_p_z"):
438     case Hash("sxtw_z_p_z"):
439     case Hash("uabd_z_p_zz"):
440     case Hash("uadalp_z_p_z"):
441     case Hash("udiv_z_p_zz"):
442     case Hash("udivr_z_p_zz"):
443     case Hash("uhadd_z_p_zz"):
444     case Hash("uhsub_z_p_zz"):
445     case Hash("uhsubr_z_p_zz"):
446     case Hash("umax_z_p_zz"):
447     case Hash("umin_z_p_zz"):
448     case Hash("umulh_z_p_zz"):
449     case Hash("uqadd_z_p_zz"):
450     case Hash("uqrshl_z_p_zz"):
451     case Hash("uqrshlr_z_p_zz"):
452     case Hash("uqshl_z_p_zz"):
453     case Hash("uqshlr_z_p_zz"):
454     case Hash("uqsub_z_p_zz"):
455     case Hash("uqsubr_z_p_zz"):
456     case Hash("urecpe_z_p_z"):
457     case Hash("urhadd_z_p_zz"):
458     case Hash("urshl_z_p_zz"):
459     case Hash("urshlr_z_p_zz"):
460     case Hash("ursqrte_z_p_z"):
461     case Hash("usqadd_z_p_zz"):
462     case Hash("uxtb_z_p_z"):
463     case Hash("uxth_z_p_z"):
464     case Hash("uxtw_z_p_z"):
465       return (movprfx_is_unpredicated || (pg_matches_low8 && vform_matches)) &&
466              zd_isnt_zn && zd_matches;
467 
468     case Hash("cpy_z_p_r"):
469     case Hash("fadd_z_p_zs"):
470     case Hash("fmax_z_p_zs"):
471     case Hash("fmaxnm_z_p_zs"):
472     case Hash("fmin_z_p_zs"):
473     case Hash("fminnm_z_p_zs"):
474     case Hash("fmul_z_p_zs"):
475     case Hash("fsub_z_p_zs"):
476     case Hash("fsubr_z_p_zs"):
477       return (movprfx_is_unpredicated || (pg_matches_low8 && vform_matches)) &&
478              zd_matches;
479     default:
480       return false;
481   }
482 }  // NOLINT(readability/fn_size)
483 
IsLoad() const484 bool Instruction::IsLoad() const {
485   if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) {
486     return false;
487   }
488 
489   if (Mask(LoadStorePairAnyFMask) == LoadStorePairAnyFixed) {
490     return Mask(LoadStorePairLBit) != 0;
491   } else {
492     LoadStoreOp op = static_cast<LoadStoreOp>(Mask(LoadStoreMask));
493     switch (op) {
494       case LDRB_w:
495       case LDRH_w:
496       case LDR_w:
497       case LDR_x:
498       case LDRSB_w:
499       case LDRSB_x:
500       case LDRSH_w:
501       case LDRSH_x:
502       case LDRSW_x:
503       case LDR_b:
504       case LDR_h:
505       case LDR_s:
506       case LDR_d:
507       case LDR_q:
508         return true;
509       default:
510         return false;
511     }
512   }
513 }
514 
515 
IsStore() const516 bool Instruction::IsStore() const {
517   if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) {
518     return false;
519   }
520 
521   if (Mask(LoadStorePairAnyFMask) == LoadStorePairAnyFixed) {
522     return Mask(LoadStorePairLBit) == 0;
523   } else {
524     LoadStoreOp op = static_cast<LoadStoreOp>(Mask(LoadStoreMask));
525     switch (op) {
526       case STRB_w:
527       case STRH_w:
528       case STR_w:
529       case STR_x:
530       case STR_b:
531       case STR_h:
532       case STR_s:
533       case STR_d:
534       case STR_q:
535         return true;
536       default:
537         return false;
538     }
539   }
540 }
541 
542 
GetSVEPermuteIndexAndLaneSizeLog2() const543 std::pair<int, int> Instruction::GetSVEPermuteIndexAndLaneSizeLog2() const {
544   uint32_t imm_2 = ExtractBits<0x00C00000>();
545   uint32_t tsz_5 = ExtractBits<0x001F0000>();
546   uint32_t imm_7 = (imm_2 << 5) | tsz_5;
547   int lane_size_in_byte_log_2 = std::min(CountTrailingZeros(tsz_5), 5);
548   int index = ExtractUnsignedBitfield32(6, lane_size_in_byte_log_2 + 1, imm_7);
549   return std::make_pair(index, lane_size_in_byte_log_2);
550 }
551 
552 // Get the register and index for SVE indexed multiplies encoded in the forms:
553 //  .h : Zm = <18:16>, index = <22><20:19>
554 //  .s : Zm = <18:16>, index = <20:19>
555 //  .d : Zm = <19:16>, index = <20>
GetSVEMulZmAndIndex() const556 std::pair<int, int> Instruction::GetSVEMulZmAndIndex() const {
557   int reg_code = GetRmLow16();
558   int index = ExtractBits(20, 19);
559 
560   // For .h, index uses bit zero of the size field, so kFormatVnB below implies
561   // half-word lane, with most-significant bit of the index zero.
562   switch (GetSVEVectorFormat()) {
563     case kFormatVnD:
564       index >>= 1;  // Only bit 20 in the index for D lanes.
565       break;
566     case kFormatVnH:
567       index += 4;  // Bit 22 is the top bit of index.
568       VIXL_FALLTHROUGH();
569     case kFormatVnB:
570     case kFormatVnS:
571       reg_code &= 7;  // Three bits used for the register.
572       break;
573     default:
574       VIXL_UNIMPLEMENTED();
575       break;
576   }
577   return std::make_pair(reg_code, index);
578 }
579 
580 // Get the register and index for SVE indexed long multiplies encoded in the
581 // forms:
582 //  .h : Zm = <18:16>, index = <20:19><11>
583 //  .s : Zm = <19:16>, index = <20><11>
GetSVEMulLongZmAndIndex() const584 std::pair<int, int> Instruction::GetSVEMulLongZmAndIndex() const {
585   int reg_code = GetRmLow16();
586   int index = ExtractBit(11);
587 
588   // For long multiplies, the SVE size field <23:22> encodes the destination
589   // element size. The source element size is half the width.
590   switch (GetSVEVectorFormat()) {
591     case kFormatVnS:
592       reg_code &= 7;
593       index |= ExtractBits(20, 19) << 1;
594       break;
595     case kFormatVnD:
596       index |= ExtractBit(20) << 1;
597       break;
598     default:
599       VIXL_UNIMPLEMENTED();
600       break;
601   }
602   return std::make_pair(reg_code, index);
603 }
604 
605 // Logical immediates can't encode zero, so a return value of zero is used to
606 // indicate a failure case. Specifically, where the constraints on imm_s are
607 // not met.
GetImmLogical() const608 uint64_t Instruction::GetImmLogical() const {
609   unsigned reg_size = GetSixtyFourBits() ? kXRegSize : kWRegSize;
610   int32_t n = GetBitN();
611   int32_t imm_s = GetImmSetBits();
612   int32_t imm_r = GetImmRotate();
613   return DecodeImmBitMask(n, imm_s, imm_r, reg_size);
614 }
615 
616 // Logical immediates can't encode zero, so a return value of zero is used to
617 // indicate a failure case. Specifically, where the constraints on imm_s are
618 // not met.
GetSVEImmLogical() const619 uint64_t Instruction::GetSVEImmLogical() const {
620   int n = GetSVEBitN();
621   int imm_s = GetSVEImmSetBits();
622   int imm_r = GetSVEImmRotate();
623   int lane_size_in_bytes_log2 = GetSVEBitwiseImmLaneSizeInBytesLog2();
624   switch (lane_size_in_bytes_log2) {
625     case kDRegSizeInBytesLog2:
626     case kSRegSizeInBytesLog2:
627     case kHRegSizeInBytesLog2:
628     case kBRegSizeInBytesLog2: {
629       int lane_size_in_bits = 1 << (lane_size_in_bytes_log2 + 3);
630       return DecodeImmBitMask(n, imm_s, imm_r, lane_size_in_bits);
631     }
632     default:
633       return 0;
634   }
635 }
636 
GetSVEImmShiftAndLaneSizeLog2(bool is_predicated) const637 std::pair<int, int> Instruction::GetSVEImmShiftAndLaneSizeLog2(
638     bool is_predicated) const {
639   Instr tsize =
640       is_predicated ? ExtractBits<0x00C00300>() : ExtractBits<0x00D80000>();
641   Instr imm_3 =
642       is_predicated ? ExtractBits<0x000000E0>() : ExtractBits<0x00070000>();
643   if (tsize == 0) {
644     // The bit field `tsize` means undefined if it is zero, so return a
645     // convenience value kWMinInt to indicate a failure case.
646     return std::make_pair(kWMinInt, kWMinInt);
647   }
648 
649   int lane_size_in_bytes_log_2 = 32 - CountLeadingZeros(tsize, 32) - 1;
650   int esize = (1 << lane_size_in_bytes_log_2) * kBitsPerByte;
651   int shift = (2 * esize) - ((tsize << 3) | imm_3);
652   return std::make_pair(shift, lane_size_in_bytes_log_2);
653 }
654 
GetSVEMsizeFromDtype(bool is_signed,int dtype_h_lsb) const655 int Instruction::GetSVEMsizeFromDtype(bool is_signed, int dtype_h_lsb) const {
656   Instr dtype_h = ExtractBits(dtype_h_lsb + 1, dtype_h_lsb);
657   if (is_signed) {
658     dtype_h = dtype_h ^ 0x3;
659   }
660   return dtype_h;
661 }
662 
GetSVEEsizeFromDtype(bool is_signed,int dtype_l_lsb) const663 int Instruction::GetSVEEsizeFromDtype(bool is_signed, int dtype_l_lsb) const {
664   Instr dtype_l = ExtractBits(dtype_l_lsb + 1, dtype_l_lsb);
665   if (is_signed) {
666     dtype_l = dtype_l ^ 0x3;
667   }
668   return dtype_l;
669 }
670 
GetSVEBitwiseImmLaneSizeInBytesLog2() const671 int Instruction::GetSVEBitwiseImmLaneSizeInBytesLog2() const {
672   int n = GetSVEBitN();
673   int imm_s = GetSVEImmSetBits();
674   unsigned type_bitset =
675       (n << SVEImmSetBits_width) | (~imm_s & GetUintMask(SVEImmSetBits_width));
676 
677   // An lane size is constructed from the n and imm_s bits according to
678   // the following table:
679   //
680   // N   imms   size
681   // 0  0xxxxx   32
682   // 0  10xxxx   16
683   // 0  110xxx    8
684   // 0  1110xx    8
685   // 0  11110x    8
686   // 1  xxxxxx   64
687 
688   if (type_bitset == 0) {
689     // Bail out early since `HighestSetBitPosition` doesn't accept zero
690     // value input.
691     return -1;
692   }
693 
694   switch (HighestSetBitPosition(type_bitset)) {
695     case 6:
696       return kDRegSizeInBytesLog2;
697     case 5:
698       return kSRegSizeInBytesLog2;
699     case 4:
700       return kHRegSizeInBytesLog2;
701     case 3:
702     case 2:
703     case 1:
704       return kBRegSizeInBytesLog2;
705     default:
706       // RESERVED encoding.
707       return -1;
708   }
709 }
710 
GetSVEExtractImmediate() const711 int Instruction::GetSVEExtractImmediate() const {
712   const int imm8h_mask = 0x001F0000;
713   const int imm8l_mask = 0x00001C00;
714   return ExtractBits<imm8h_mask | imm8l_mask>();
715 }
716 
DecodeImmBitMask(int32_t n,int32_t imm_s,int32_t imm_r,int32_t size) const717 uint64_t Instruction::DecodeImmBitMask(int32_t n,
718                                        int32_t imm_s,
719                                        int32_t imm_r,
720                                        int32_t size) const {
721   // An integer is constructed from the n, imm_s and imm_r bits according to
722   // the following table:
723   //
724   //  N   imms    immr    size        S             R
725   //  1  ssssss  rrrrrr    64    UInt(ssssss)  UInt(rrrrrr)
726   //  0  0sssss  xrrrrr    32    UInt(sssss)   UInt(rrrrr)
727   //  0  10ssss  xxrrrr    16    UInt(ssss)    UInt(rrrr)
728   //  0  110sss  xxxrrr     8    UInt(sss)     UInt(rrr)
729   //  0  1110ss  xxxxrr     4    UInt(ss)      UInt(rr)
730   //  0  11110s  xxxxxr     2    UInt(s)       UInt(r)
731   // (s bits must not be all set)
732   //
733   // A pattern is constructed of size bits, where the least significant S+1
734   // bits are set. The pattern is rotated right by R, and repeated across a
735   // 32 or 64-bit value, depending on destination register width.
736   //
737 
738   if (n == 1) {
739     if (imm_s == 0x3f) {
740       return 0;
741     }
742     uint64_t bits = (UINT64_C(1) << (imm_s + 1)) - 1;
743     return RotateRight(bits, imm_r, 64);
744   } else {
745     if ((imm_s >> 1) == 0x1f) {
746       return 0;
747     }
748     for (int width = 0x20; width >= 0x2; width >>= 1) {
749       if ((imm_s & width) == 0) {
750         int mask = width - 1;
751         if ((imm_s & mask) == mask) {
752           return 0;
753         }
754         uint64_t bits = (UINT64_C(1) << ((imm_s & mask) + 1)) - 1;
755         return RepeatBitsAcrossReg(size,
756                                    RotateRight(bits, imm_r & mask, width),
757                                    width);
758       }
759     }
760   }
761   VIXL_UNREACHABLE();
762   return 0;
763 }
764 
765 
GetImmNEONabcdefgh() const766 uint32_t Instruction::GetImmNEONabcdefgh() const {
767   return GetImmNEONabc() << 5 | GetImmNEONdefgh();
768 }
769 
770 
Imm8ToFloat16(uint32_t imm8)771 Float16 Instruction::Imm8ToFloat16(uint32_t imm8) {
772   // Imm8: abcdefgh (8 bits)
773   // Half: aBbb.cdef.gh00.0000 (16 bits)
774   // where B is b ^ 1
775   uint32_t bits = imm8;
776   uint16_t bit7 = (bits >> 7) & 0x1;
777   uint16_t bit6 = (bits >> 6) & 0x1;
778   uint16_t bit5_to_0 = bits & 0x3f;
779   uint16_t result = (bit7 << 15) | ((4 - bit6) << 12) | (bit5_to_0 << 6);
780   return RawbitsToFloat16(result);
781 }
782 
783 
Imm8ToFP32(uint32_t imm8)784 float Instruction::Imm8ToFP32(uint32_t imm8) {
785   // Imm8: abcdefgh (8 bits)
786   // Single: aBbb.bbbc.defg.h000.0000.0000.0000.0000 (32 bits)
787   // where B is b ^ 1
788   uint32_t bits = imm8;
789   uint32_t bit7 = (bits >> 7) & 0x1;
790   uint32_t bit6 = (bits >> 6) & 0x1;
791   uint32_t bit5_to_0 = bits & 0x3f;
792   uint32_t result = (bit7 << 31) | ((32 - bit6) << 25) | (bit5_to_0 << 19);
793 
794   return RawbitsToFloat(result);
795 }
796 
797 
GetImmFP16() const798 Float16 Instruction::GetImmFP16() const { return Imm8ToFloat16(GetImmFP()); }
799 
800 
GetImmFP32() const801 float Instruction::GetImmFP32() const { return Imm8ToFP32(GetImmFP()); }
802 
803 
Imm8ToFP64(uint32_t imm8)804 double Instruction::Imm8ToFP64(uint32_t imm8) {
805   // Imm8: abcdefgh (8 bits)
806   // Double: aBbb.bbbb.bbcd.efgh.0000.0000.0000.0000
807   //         0000.0000.0000.0000.0000.0000.0000.0000 (64 bits)
808   // where B is b ^ 1
809   uint32_t bits = imm8;
810   uint64_t bit7 = (bits >> 7) & 0x1;
811   uint64_t bit6 = (bits >> 6) & 0x1;
812   uint64_t bit5_to_0 = bits & 0x3f;
813   uint64_t result = (bit7 << 63) | ((256 - bit6) << 54) | (bit5_to_0 << 48);
814 
815   return RawbitsToDouble(result);
816 }
817 
818 
GetImmFP64() const819 double Instruction::GetImmFP64() const { return Imm8ToFP64(GetImmFP()); }
820 
821 
GetImmNEONFP16() const822 Float16 Instruction::GetImmNEONFP16() const {
823   return Imm8ToFloat16(GetImmNEONabcdefgh());
824 }
825 
826 
GetImmNEONFP32() const827 float Instruction::GetImmNEONFP32() const {
828   return Imm8ToFP32(GetImmNEONabcdefgh());
829 }
830 
831 
GetImmNEONFP64() const832 double Instruction::GetImmNEONFP64() const {
833   return Imm8ToFP64(GetImmNEONabcdefgh());
834 }
835 
836 
CalcLSDataSize(LoadStoreOp op)837 unsigned CalcLSDataSize(LoadStoreOp op) {
838   VIXL_ASSERT((LSSize_offset + LSSize_width) == (kInstructionSize * 8));
839   unsigned size = static_cast<Instr>(op) >> LSSize_offset;
840   if ((op & LSVector_mask) != 0) {
841     // Vector register memory operations encode the access size in the "size"
842     // and "opc" fields.
843     if ((size == 0) && ((op & LSOpc_mask) >> LSOpc_offset) >= 2) {
844       size = kQRegSizeInBytesLog2;
845     }
846   }
847   return size;
848 }
849 
850 
CalcLSPairDataSize(LoadStorePairOp op)851 unsigned CalcLSPairDataSize(LoadStorePairOp op) {
852   VIXL_STATIC_ASSERT(kXRegSizeInBytes == kDRegSizeInBytes);
853   VIXL_STATIC_ASSERT(kWRegSizeInBytes == kSRegSizeInBytes);
854   switch (op) {
855     case STP_q:
856     case LDP_q:
857       return kQRegSizeInBytesLog2;
858     case STP_x:
859     case LDP_x:
860     case STP_d:
861     case LDP_d:
862       return kXRegSizeInBytesLog2;
863     default:
864       return kWRegSizeInBytesLog2;
865   }
866 }
867 
868 
GetImmBranchRangeBitwidth(ImmBranchType branch_type)869 int Instruction::GetImmBranchRangeBitwidth(ImmBranchType branch_type) {
870   switch (branch_type) {
871     case UncondBranchType:
872       return ImmUncondBranch_width;
873     case CondBranchType:
874       return ImmCondBranch_width;
875     case CompareBranchType:
876       return ImmCmpBranch_width;
877     case TestBranchType:
878       return ImmTestBranch_width;
879     default:
880       VIXL_UNREACHABLE();
881       return 0;
882   }
883 }
884 
885 
GetImmBranchForwardRange(ImmBranchType branch_type)886 int32_t Instruction::GetImmBranchForwardRange(ImmBranchType branch_type) {
887   int32_t encoded_max = 1 << (GetImmBranchRangeBitwidth(branch_type) - 1);
888   return encoded_max * kInstructionSize;
889 }
890 
891 
IsValidImmPCOffset(ImmBranchType branch_type,int64_t offset)892 bool Instruction::IsValidImmPCOffset(ImmBranchType branch_type,
893                                      int64_t offset) {
894   return IsIntN(GetImmBranchRangeBitwidth(branch_type), offset);
895 }
896 
897 
GetImmPCOffsetTarget() const898 const Instruction* Instruction::GetImmPCOffsetTarget() const {
899   const Instruction* base = this;
900   ptrdiff_t offset;
901   if (IsPCRelAddressing()) {
902     // ADR and ADRP.
903     offset = GetImmPCRel();
904     if (Mask(PCRelAddressingMask) == ADRP) {
905       base = AlignDown(base, kPageSize);
906       offset *= kPageSize;
907     } else {
908       VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR);
909     }
910   } else {
911     // All PC-relative branches.
912     VIXL_ASSERT(GetBranchType() != UnknownBranchType);
913     // Relative branch offsets are instruction-size-aligned.
914     offset = GetImmBranch() * static_cast<int>(kInstructionSize);
915   }
916   return base + offset;
917 }
918 
919 
GetImmBranch() const920 int Instruction::GetImmBranch() const {
921   switch (GetBranchType()) {
922     case CondBranchType:
923       return GetImmCondBranch();
924     case UncondBranchType:
925       return GetImmUncondBranch();
926     case CompareBranchType:
927       return GetImmCmpBranch();
928     case TestBranchType:
929       return GetImmTestBranch();
930     default:
931       VIXL_UNREACHABLE();
932   }
933   return 0;
934 }
935 
936 
SetImmPCOffsetTarget(const Instruction * target)937 void Instruction::SetImmPCOffsetTarget(const Instruction* target) {
938   if (IsPCRelAddressing()) {
939     SetPCRelImmTarget(target);
940   } else {
941     SetBranchImmTarget(target);
942   }
943 }
944 
945 
SetPCRelImmTarget(const Instruction * target)946 void Instruction::SetPCRelImmTarget(const Instruction* target) {
947   ptrdiff_t imm21;
948   if ((Mask(PCRelAddressingMask) == ADR)) {
949     imm21 = target - this;
950   } else {
951     VIXL_ASSERT(Mask(PCRelAddressingMask) == ADRP);
952     uintptr_t this_page = reinterpret_cast<uintptr_t>(this) / kPageSize;
953     uintptr_t target_page = reinterpret_cast<uintptr_t>(target) / kPageSize;
954     imm21 = target_page - this_page;
955   }
956   Instr imm = Assembler::ImmPCRelAddress(static_cast<int32_t>(imm21));
957 
958   SetInstructionBits(Mask(~ImmPCRel_mask) | imm);
959 }
960 
961 
SetBranchImmTarget(const Instruction * target)962 void Instruction::SetBranchImmTarget(const Instruction* target) {
963   VIXL_ASSERT(((target - this) & 3) == 0);
964   Instr branch_imm = 0;
965   uint32_t imm_mask = 0;
966   int offset = static_cast<int>((target - this) >> kInstructionSizeLog2);
967   switch (GetBranchType()) {
968     case CondBranchType: {
969       branch_imm = Assembler::ImmCondBranch(offset);
970       imm_mask = ImmCondBranch_mask;
971       break;
972     }
973     case UncondBranchType: {
974       branch_imm = Assembler::ImmUncondBranch(offset);
975       imm_mask = ImmUncondBranch_mask;
976       break;
977     }
978     case CompareBranchType: {
979       branch_imm = Assembler::ImmCmpBranch(offset);
980       imm_mask = ImmCmpBranch_mask;
981       break;
982     }
983     case TestBranchType: {
984       branch_imm = Assembler::ImmTestBranch(offset);
985       imm_mask = ImmTestBranch_mask;
986       break;
987     }
988     default:
989       VIXL_UNREACHABLE();
990   }
991   SetInstructionBits(Mask(~imm_mask) | branch_imm);
992 }
993 
994 
SetImmLLiteral(const Instruction * source)995 void Instruction::SetImmLLiteral(const Instruction* source) {
996   VIXL_ASSERT(IsWordAligned(source));
997   ptrdiff_t offset = (source - this) >> kLiteralEntrySizeLog2;
998   Instr imm = Assembler::ImmLLiteral(static_cast<int>(offset));
999   Instr mask = ImmLLiteral_mask;
1000 
1001   SetInstructionBits(Mask(~mask) | imm);
1002 }
1003 
1004 
VectorFormatHalfWidth(VectorFormat vform)1005 VectorFormat VectorFormatHalfWidth(VectorFormat vform) {
1006   switch (vform) {
1007     case kFormat8H:
1008       return kFormat8B;
1009     case kFormat4S:
1010       return kFormat4H;
1011     case kFormat2D:
1012       return kFormat2S;
1013     case kFormatH:
1014       return kFormatB;
1015     case kFormatS:
1016       return kFormatH;
1017     case kFormatD:
1018       return kFormatS;
1019     case kFormatVnH:
1020       return kFormatVnB;
1021     case kFormatVnS:
1022       return kFormatVnH;
1023     case kFormatVnD:
1024       return kFormatVnS;
1025     default:
1026       VIXL_UNREACHABLE();
1027       return kFormatUndefined;
1028   }
1029 }
1030 
1031 
VectorFormatDoubleWidth(VectorFormat vform)1032 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) {
1033   switch (vform) {
1034     case kFormat8B:
1035       return kFormat8H;
1036     case kFormat4H:
1037       return kFormat4S;
1038     case kFormat2S:
1039       return kFormat2D;
1040     case kFormatB:
1041       return kFormatH;
1042     case kFormatH:
1043       return kFormatS;
1044     case kFormatS:
1045       return kFormatD;
1046     case kFormatVnB:
1047       return kFormatVnH;
1048     case kFormatVnH:
1049       return kFormatVnS;
1050     case kFormatVnS:
1051       return kFormatVnD;
1052     default:
1053       VIXL_UNREACHABLE();
1054       return kFormatUndefined;
1055   }
1056 }
1057 
1058 
VectorFormatFillQ(VectorFormat vform)1059 VectorFormat VectorFormatFillQ(VectorFormat vform) {
1060   switch (vform) {
1061     case kFormatB:
1062     case kFormat8B:
1063     case kFormat16B:
1064       return kFormat16B;
1065     case kFormatH:
1066     case kFormat4H:
1067     case kFormat8H:
1068       return kFormat8H;
1069     case kFormatS:
1070     case kFormat2S:
1071     case kFormat4S:
1072       return kFormat4S;
1073     case kFormatD:
1074     case kFormat1D:
1075     case kFormat2D:
1076       return kFormat2D;
1077     default:
1078       VIXL_UNREACHABLE();
1079       return kFormatUndefined;
1080   }
1081 }
1082 
VectorFormatHalfWidthDoubleLanes(VectorFormat vform)1083 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) {
1084   switch (vform) {
1085     case kFormat4H:
1086       return kFormat8B;
1087     case kFormat8H:
1088       return kFormat16B;
1089     case kFormat2S:
1090       return kFormat4H;
1091     case kFormat4S:
1092       return kFormat8H;
1093     case kFormat1D:
1094       return kFormat2S;
1095     case kFormat2D:
1096       return kFormat4S;
1097     case kFormatVnH:
1098       return kFormatVnB;
1099     case kFormatVnS:
1100       return kFormatVnH;
1101     case kFormatVnD:
1102       return kFormatVnS;
1103     default:
1104       VIXL_UNREACHABLE();
1105       return kFormatUndefined;
1106   }
1107 }
1108 
VectorFormatDoubleLanes(VectorFormat vform)1109 VectorFormat VectorFormatDoubleLanes(VectorFormat vform) {
1110   VIXL_ASSERT(vform == kFormat8B || vform == kFormat4H || vform == kFormat2S);
1111   switch (vform) {
1112     case kFormat8B:
1113       return kFormat16B;
1114     case kFormat4H:
1115       return kFormat8H;
1116     case kFormat2S:
1117       return kFormat4S;
1118     default:
1119       VIXL_UNREACHABLE();
1120       return kFormatUndefined;
1121   }
1122 }
1123 
1124 
VectorFormatHalfLanes(VectorFormat vform)1125 VectorFormat VectorFormatHalfLanes(VectorFormat vform) {
1126   VIXL_ASSERT(vform == kFormat16B || vform == kFormat8H || vform == kFormat4S);
1127   switch (vform) {
1128     case kFormat16B:
1129       return kFormat8B;
1130     case kFormat8H:
1131       return kFormat4H;
1132     case kFormat4S:
1133       return kFormat2S;
1134     default:
1135       VIXL_UNREACHABLE();
1136       return kFormatUndefined;
1137   }
1138 }
1139 
1140 
ScalarFormatFromLaneSize(int lane_size_in_bits)1141 VectorFormat ScalarFormatFromLaneSize(int lane_size_in_bits) {
1142   switch (lane_size_in_bits) {
1143     case 8:
1144       return kFormatB;
1145     case 16:
1146       return kFormatH;
1147     case 32:
1148       return kFormatS;
1149     case 64:
1150       return kFormatD;
1151     default:
1152       VIXL_UNREACHABLE();
1153       return kFormatUndefined;
1154   }
1155 }
1156 
1157 
IsSVEFormat(VectorFormat vform)1158 bool IsSVEFormat(VectorFormat vform) {
1159   switch (vform) {
1160     case kFormatVnB:
1161     case kFormatVnH:
1162     case kFormatVnS:
1163     case kFormatVnD:
1164     case kFormatVnQ:
1165     case kFormatVnO:
1166       return true;
1167     default:
1168       return false;
1169   }
1170 }
1171 
1172 
SVEFormatFromLaneSizeInBytes(int lane_size_in_bytes)1173 VectorFormat SVEFormatFromLaneSizeInBytes(int lane_size_in_bytes) {
1174   switch (lane_size_in_bytes) {
1175     case 1:
1176       return kFormatVnB;
1177     case 2:
1178       return kFormatVnH;
1179     case 4:
1180       return kFormatVnS;
1181     case 8:
1182       return kFormatVnD;
1183     case 16:
1184       return kFormatVnQ;
1185     default:
1186       VIXL_UNREACHABLE();
1187       return kFormatUndefined;
1188   }
1189 }
1190 
1191 
SVEFormatFromLaneSizeInBits(int lane_size_in_bits)1192 VectorFormat SVEFormatFromLaneSizeInBits(int lane_size_in_bits) {
1193   switch (lane_size_in_bits) {
1194     case 8:
1195     case 16:
1196     case 32:
1197     case 64:
1198     case 128:
1199       return SVEFormatFromLaneSizeInBytes(lane_size_in_bits / kBitsPerByte);
1200     default:
1201       VIXL_UNREACHABLE();
1202       return kFormatUndefined;
1203   }
1204 }
1205 
1206 
SVEFormatFromLaneSizeInBytesLog2(int lane_size_in_bytes_log2)1207 VectorFormat SVEFormatFromLaneSizeInBytesLog2(int lane_size_in_bytes_log2) {
1208   switch (lane_size_in_bytes_log2) {
1209     case 0:
1210     case 1:
1211     case 2:
1212     case 3:
1213     case 4:
1214       return SVEFormatFromLaneSizeInBytes(1 << lane_size_in_bytes_log2);
1215     default:
1216       VIXL_UNREACHABLE();
1217       return kFormatUndefined;
1218   }
1219 }
1220 
1221 
ScalarFormatFromFormat(VectorFormat vform)1222 VectorFormat ScalarFormatFromFormat(VectorFormat vform) {
1223   return ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform));
1224 }
1225 
1226 
RegisterSizeInBitsFromFormat(VectorFormat vform)1227 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform) {
1228   VIXL_ASSERT(vform != kFormatUndefined);
1229   VIXL_ASSERT(!IsSVEFormat(vform));
1230   switch (vform) {
1231     case kFormatB:
1232       return kBRegSize;
1233     case kFormatH:
1234       return kHRegSize;
1235     case kFormatS:
1236     case kFormat2H:
1237       return kSRegSize;
1238     case kFormatD:
1239     case kFormat8B:
1240     case kFormat4H:
1241     case kFormat2S:
1242     case kFormat1D:
1243       return kDRegSize;
1244     case kFormat16B:
1245     case kFormat8H:
1246     case kFormat4S:
1247     case kFormat2D:
1248       return kQRegSize;
1249     default:
1250       VIXL_UNREACHABLE();
1251       return 0;
1252   }
1253 }
1254 
1255 
RegisterSizeInBytesFromFormat(VectorFormat vform)1256 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform) {
1257   return RegisterSizeInBitsFromFormat(vform) / 8;
1258 }
1259 
1260 
LaneSizeInBitsFromFormat(VectorFormat vform)1261 unsigned LaneSizeInBitsFromFormat(VectorFormat vform) {
1262   VIXL_ASSERT(vform != kFormatUndefined);
1263   switch (vform) {
1264     case kFormatB:
1265     case kFormat8B:
1266     case kFormat16B:
1267     case kFormatVnB:
1268       return 8;
1269     case kFormatH:
1270     case kFormat2H:
1271     case kFormat4H:
1272     case kFormat8H:
1273     case kFormatVnH:
1274       return 16;
1275     case kFormatS:
1276     case kFormat2S:
1277     case kFormat4S:
1278     case kFormatVnS:
1279       return 32;
1280     case kFormatD:
1281     case kFormat1D:
1282     case kFormat2D:
1283     case kFormatVnD:
1284       return 64;
1285     case kFormatVnQ:
1286       return 128;
1287     case kFormatVnO:
1288       return 256;
1289     default:
1290       VIXL_UNREACHABLE();
1291       return 0;
1292   }
1293 }
1294 
1295 
LaneSizeInBytesFromFormat(VectorFormat vform)1296 int LaneSizeInBytesFromFormat(VectorFormat vform) {
1297   return LaneSizeInBitsFromFormat(vform) / 8;
1298 }
1299 
1300 
LaneSizeInBytesLog2FromFormat(VectorFormat vform)1301 int LaneSizeInBytesLog2FromFormat(VectorFormat vform) {
1302   VIXL_ASSERT(vform != kFormatUndefined);
1303   switch (vform) {
1304     case kFormatB:
1305     case kFormat8B:
1306     case kFormat16B:
1307     case kFormatVnB:
1308       return 0;
1309     case kFormatH:
1310     case kFormat2H:
1311     case kFormat4H:
1312     case kFormat8H:
1313     case kFormatVnH:
1314       return 1;
1315     case kFormatS:
1316     case kFormat2S:
1317     case kFormat4S:
1318     case kFormatVnS:
1319       return 2;
1320     case kFormatD:
1321     case kFormat1D:
1322     case kFormat2D:
1323     case kFormatVnD:
1324       return 3;
1325     case kFormatVnQ:
1326       return 4;
1327     default:
1328       VIXL_UNREACHABLE();
1329       return 0;
1330   }
1331 }
1332 
1333 
LaneCountFromFormat(VectorFormat vform)1334 int LaneCountFromFormat(VectorFormat vform) {
1335   VIXL_ASSERT(vform != kFormatUndefined);
1336   switch (vform) {
1337     case kFormat16B:
1338       return 16;
1339     case kFormat8B:
1340     case kFormat8H:
1341       return 8;
1342     case kFormat4H:
1343     case kFormat4S:
1344       return 4;
1345     case kFormat2H:
1346     case kFormat2S:
1347     case kFormat2D:
1348       return 2;
1349     case kFormat1D:
1350     case kFormatB:
1351     case kFormatH:
1352     case kFormatS:
1353     case kFormatD:
1354       return 1;
1355     default:
1356       VIXL_UNREACHABLE();
1357       return 0;
1358   }
1359 }
1360 
1361 
MaxLaneCountFromFormat(VectorFormat vform)1362 int MaxLaneCountFromFormat(VectorFormat vform) {
1363   VIXL_ASSERT(vform != kFormatUndefined);
1364   switch (vform) {
1365     case kFormatB:
1366     case kFormat8B:
1367     case kFormat16B:
1368       return 16;
1369     case kFormatH:
1370     case kFormat4H:
1371     case kFormat8H:
1372       return 8;
1373     case kFormatS:
1374     case kFormat2S:
1375     case kFormat4S:
1376       return 4;
1377     case kFormatD:
1378     case kFormat1D:
1379     case kFormat2D:
1380       return 2;
1381     default:
1382       VIXL_UNREACHABLE();
1383       return 0;
1384   }
1385 }
1386 
1387 
1388 // Does 'vform' indicate a vector format or a scalar format?
IsVectorFormat(VectorFormat vform)1389 bool IsVectorFormat(VectorFormat vform) {
1390   VIXL_ASSERT(vform != kFormatUndefined);
1391   switch (vform) {
1392     case kFormatB:
1393     case kFormatH:
1394     case kFormatS:
1395     case kFormatD:
1396       return false;
1397     default:
1398       return true;
1399   }
1400 }
1401 
1402 
MaxIntFromFormat(VectorFormat vform)1403 int64_t MaxIntFromFormat(VectorFormat vform) {
1404   int lane_size = LaneSizeInBitsFromFormat(vform);
1405   return static_cast<int64_t>(GetUintMask(lane_size) >> 1);
1406 }
1407 
1408 
MinIntFromFormat(VectorFormat vform)1409 int64_t MinIntFromFormat(VectorFormat vform) {
1410   return -MaxIntFromFormat(vform) - 1;
1411 }
1412 
1413 
MaxUintFromFormat(VectorFormat vform)1414 uint64_t MaxUintFromFormat(VectorFormat vform) {
1415   return GetUintMask(LaneSizeInBitsFromFormat(vform));
1416 }
1417 
1418 }  // namespace aarch64
1419 }  // namespace vixl
1420