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1  //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2  //
3  // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4  // See https://llvm.org/LICENSE.txt for license information.
5  // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6  //
7  /// \file
8  //===----------------------------------------------------------------------===//
9  
10  #include "llvm/MC/MCInstrDesc.h"
11  
12  #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
13  #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14  
15  namespace llvm {
16  
17  namespace SIInstrFlags {
18  // This needs to be kept in sync with the field bits in InstSI.
19  enum : uint64_t {
20    // Low bits - basic encoding information.
21    SALU = 1 << 0,
22    VALU = 1 << 1,
23  
24    // SALU instruction formats.
25    SOP1 = 1 << 2,
26    SOP2 = 1 << 3,
27    SOPC = 1 << 4,
28    SOPK = 1 << 5,
29    SOPP = 1 << 6,
30  
31    // VALU instruction formats.
32    VOP1 = 1 << 7,
33    VOP2 = 1 << 8,
34    VOPC = 1 << 9,
35  
36   // TODO: Should this be spilt into VOP3 a and b?
37    VOP3 = 1 << 10,
38    VOP3P = 1 << 12,
39  
40    VINTRP = 1 << 13,
41    SDWA = 1 << 14,
42    DPP = 1 << 15,
43  
44    // Memory instruction formats.
45    MUBUF = 1 << 16,
46    MTBUF = 1 << 17,
47    SMRD = 1 << 18,
48    MIMG = 1 << 19,
49    EXP = 1 << 20,
50    FLAT = 1 << 21,
51    DS = 1 << 22,
52  
53    // Pseudo instruction formats.
54    VGPRSpill = 1 << 23,
55    SGPRSpill = 1 << 24,
56  
57    // High bits - other information.
58    VM_CNT = UINT64_C(1) << 32,
59    EXP_CNT = UINT64_C(1) << 33,
60    LGKM_CNT = UINT64_C(1) << 34,
61  
62    WQM = UINT64_C(1) << 35,
63    DisableWQM = UINT64_C(1) << 36,
64    Gather4 = UINT64_C(1) << 37,
65    SOPK_ZEXT = UINT64_C(1) << 38,
66    SCALAR_STORE = UINT64_C(1) << 39,
67    FIXED_SIZE = UINT64_C(1) << 40,
68    VOPAsmPrefer32Bit = UINT64_C(1) << 41,
69    VOP3_OPSEL = UINT64_C(1) << 42,
70    maybeAtomic = UINT64_C(1) << 43,
71    renamedInGFX9 = UINT64_C(1) << 44,
72  
73    // Is a clamp on FP type.
74    FPClamp = UINT64_C(1) << 45,
75  
76    // Is an integer clamp
77    IntClamp = UINT64_C(1) << 46,
78  
79    // Clamps lo component of register.
80    ClampLo = UINT64_C(1) << 47,
81  
82    // Clamps hi component of register.
83    // ClampLo and ClampHi set for packed clamp.
84    ClampHi = UINT64_C(1) << 48,
85  
86    // Is a packed VOP3P instruction.
87    IsPacked = UINT64_C(1) << 49,
88  
89    // Is a D16 buffer instruction.
90    D16Buf = UINT64_C(1) << 50,
91  
92    // FLAT instruction accesses FLAT_GLBL or FLAT_SCRATCH segment.
93    IsNonFlatSeg = UINT64_C(1) << 51,
94  
95    // Uses floating point double precision rounding mode
96    FPDPRounding = UINT64_C(1) << 52,
97  
98    // Instruction is FP atomic.
99    FPAtomic = UINT64_C(1) << 53,
100  
101    // Is a MFMA instruction.
102    IsMAI = UINT64_C(1) << 54,
103  
104    // Is a DOT instruction.
105    IsDOT = UINT64_C(1) << 55
106  };
107  
108  // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
109  // The result is true if any of these tests are true.
110  enum ClassFlags : unsigned {
111    S_NAN = 1 << 0,        // Signaling NaN
112    Q_NAN = 1 << 1,        // Quiet NaN
113    N_INFINITY = 1 << 2,   // Negative infinity
114    N_NORMAL = 1 << 3,     // Negative normal
115    N_SUBNORMAL = 1 << 4,  // Negative subnormal
116    N_ZERO = 1 << 5,       // Negative zero
117    P_ZERO = 1 << 6,       // Positive zero
118    P_SUBNORMAL = 1 << 7,  // Positive subnormal
119    P_NORMAL = 1 << 8,     // Positive normal
120    P_INFINITY = 1 << 9    // Positive infinity
121  };
122  }
123  
124  namespace AMDGPU {
125    enum OperandType : unsigned {
126      /// Operands with register or 32-bit immediate
127      OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
128      OPERAND_REG_IMM_INT64,
129      OPERAND_REG_IMM_INT16,
130      OPERAND_REG_IMM_FP32,
131      OPERAND_REG_IMM_FP64,
132      OPERAND_REG_IMM_FP16,
133      OPERAND_REG_IMM_V2FP16,
134      OPERAND_REG_IMM_V2INT16,
135  
136      /// Operands with register or inline constant
137      OPERAND_REG_INLINE_C_INT16,
138      OPERAND_REG_INLINE_C_INT32,
139      OPERAND_REG_INLINE_C_INT64,
140      OPERAND_REG_INLINE_C_FP16,
141      OPERAND_REG_INLINE_C_FP32,
142      OPERAND_REG_INLINE_C_FP64,
143      OPERAND_REG_INLINE_C_V2FP16,
144      OPERAND_REG_INLINE_C_V2INT16,
145  
146      /// Operands with an AccVGPR register or inline constant
147      OPERAND_REG_INLINE_AC_INT16,
148      OPERAND_REG_INLINE_AC_INT32,
149      OPERAND_REG_INLINE_AC_FP16,
150      OPERAND_REG_INLINE_AC_FP32,
151      OPERAND_REG_INLINE_AC_V2FP16,
152      OPERAND_REG_INLINE_AC_V2INT16,
153  
154      OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
155      OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2INT16,
156  
157      OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
158      OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2INT16,
159  
160      OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16,
161      OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2INT16,
162  
163      OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
164      OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
165  
166      // Operand for source modifiers for VOP instructions
167      OPERAND_INPUT_MODS,
168  
169      // Operand for SDWA instructions
170      OPERAND_SDWA_VOPC_DST,
171  
172      /// Operand with 32-bit immediate that uses the constant bus.
173      OPERAND_KIMM32,
174      OPERAND_KIMM16
175    };
176  }
177  
178  // Input operand modifiers bit-masks
179  // NEG and SEXT share same bit-mask because they can't be set simultaneously.
180  namespace SISrcMods {
181    enum : unsigned {
182     NEG = 1 << 0,   // Floating-point negate modifier
183     ABS = 1 << 1,   // Floating-point absolute modifier
184     SEXT = 1 << 0,  // Integer sign-extend modifier
185     NEG_HI = ABS,   // Floating-point negate high packed component modifier.
186     OP_SEL_0 = 1 << 2,
187     OP_SEL_1 = 1 << 3,
188     DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
189    };
190  }
191  
192  namespace SIOutMods {
193    enum : unsigned {
194      NONE = 0,
195      MUL2 = 1,
196      MUL4 = 2,
197      DIV2 = 3
198    };
199  }
200  
201  namespace AMDGPU {
202  namespace VGPRIndexMode {
203  
204  enum Id : unsigned { // id of symbolic names
205    ID_SRC0 = 0,
206    ID_SRC1,
207    ID_SRC2,
208    ID_DST,
209  
210    ID_MIN = ID_SRC0,
211    ID_MAX = ID_DST
212  };
213  
214  enum EncBits : unsigned {
215    OFF = 0,
216    SRC0_ENABLE = 1 << ID_SRC0,
217    SRC1_ENABLE = 1 << ID_SRC1,
218    SRC2_ENABLE = 1 << ID_SRC2,
219    DST_ENABLE = 1 << ID_DST,
220    ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE
221  };
222  
223  } // namespace VGPRIndexMode
224  } // namespace AMDGPU
225  
226  namespace AMDGPUAsmVariants {
227    enum : unsigned {
228      DEFAULT = 0,
229      VOP3 = 1,
230      SDWA = 2,
231      SDWA9 = 3,
232      DPP = 4
233    };
234  }
235  
236  namespace AMDGPU {
237  namespace EncValues { // Encoding values of enum9/8/7 operands
238  
239  enum : unsigned {
240    SGPR_MIN = 0,
241    SGPR_MAX_SI = 101,
242    SGPR_MAX_GFX10 = 105,
243    TTMP_VI_MIN = 112,
244    TTMP_VI_MAX = 123,
245    TTMP_GFX9_GFX10_MIN = 108,
246    TTMP_GFX9_GFX10_MAX = 123,
247    INLINE_INTEGER_C_MIN = 128,
248    INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
249    INLINE_INTEGER_C_MAX = 208,
250    INLINE_FLOATING_C_MIN = 240,
251    INLINE_FLOATING_C_MAX = 248,
252    LITERAL_CONST = 255,
253    VGPR_MIN = 256,
254    VGPR_MAX = 511
255  };
256  
257  } // namespace EncValues
258  } // namespace AMDGPU
259  
260  namespace AMDGPU {
261  namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
262  
263  enum Id { // Message ID, width(4) [3:0].
264    ID_UNKNOWN_ = -1,
265    ID_INTERRUPT = 1,
266    ID_GS,
267    ID_GS_DONE,
268    ID_GS_ALLOC_REQ = 9,
269    ID_GET_DOORBELL = 10,
270    ID_SYSMSG = 15,
271    ID_GAPS_LAST_, // Indicate that sequence has gaps.
272    ID_GAPS_FIRST_ = ID_INTERRUPT,
273    ID_SHIFT_ = 0,
274    ID_WIDTH_ = 4,
275    ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
276  };
277  
278  enum Op { // Both GS and SYS operation IDs.
279    OP_UNKNOWN_ = -1,
280    OP_SHIFT_ = 4,
281    OP_NONE_ = 0,
282    // Bits used for operation encoding
283    OP_WIDTH_ = 3,
284    OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
285    // GS operations are encoded in bits 5:4
286    OP_GS_NOP = 0,
287    OP_GS_CUT,
288    OP_GS_EMIT,
289    OP_GS_EMIT_CUT,
290    OP_GS_LAST_,
291    OP_GS_FIRST_ = OP_GS_NOP,
292    // SYS operations are encoded in bits 6:4
293    OP_SYS_ECC_ERR_INTERRUPT = 1,
294    OP_SYS_REG_RD,
295    OP_SYS_HOST_TRAP_ACK,
296    OP_SYS_TTRACE_PC,
297    OP_SYS_LAST_,
298    OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
299  };
300  
301  enum StreamId : unsigned { // Stream ID, (2) [9:8].
302    STREAM_ID_NONE_ = 0,
303    STREAM_ID_DEFAULT_ = 0,
304    STREAM_ID_LAST_ = 4,
305    STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
306    STREAM_ID_SHIFT_ = 8,
307    STREAM_ID_WIDTH_=  2,
308    STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
309  };
310  
311  } // namespace SendMsg
312  
313  namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
314  
315  enum Id { // HwRegCode, (6) [5:0]
316    ID_UNKNOWN_ = -1,
317    ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
318    ID_MODE = 1,
319    ID_STATUS = 2,
320    ID_TRAPSTS = 3,
321    ID_HW_ID = 4,
322    ID_GPR_ALLOC = 5,
323    ID_LDS_ALLOC = 6,
324    ID_IB_STS = 7,
325    ID_MEM_BASES = 15,
326    ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES,
327    ID_TBA_LO = 16,
328    ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO,
329    ID_TBA_HI = 17,
330    ID_TMA_LO = 18,
331    ID_TMA_HI = 19,
332    ID_FLAT_SCR_LO = 20,
333    ID_FLAT_SCR_HI = 21,
334    ID_XNACK_MASK = 22,
335    ID_POPS_PACKER = 25,
336    ID_SYMBOLIC_LAST_ = 26,
337    ID_SHIFT_ = 0,
338    ID_WIDTH_ = 6,
339    ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
340  };
341  
342  enum Offset : unsigned { // Offset, (5) [10:6]
343    OFFSET_DEFAULT_ = 0,
344    OFFSET_SHIFT_ = 6,
345    OFFSET_WIDTH_ = 5,
346    OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
347  
348    OFFSET_MEM_VIOL = 8,
349  
350    OFFSET_SRC_SHARED_BASE = 16,
351    OFFSET_SRC_PRIVATE_BASE = 0
352  };
353  
354  enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
355    WIDTH_M1_DEFAULT_ = 31,
356    WIDTH_M1_SHIFT_ = 11,
357    WIDTH_M1_WIDTH_ = 5,
358    WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
359  
360    WIDTH_M1_SRC_SHARED_BASE = 15,
361    WIDTH_M1_SRC_PRIVATE_BASE = 15
362  };
363  
364  // Some values from WidthMinusOne mapped into Width domain.
365  enum Width : unsigned {
366    WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1,
367  };
368  
369  } // namespace Hwreg
370  
371  namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
372  
373  enum Id : unsigned { // id of symbolic names
374    ID_QUAD_PERM = 0,
375    ID_BITMASK_PERM,
376    ID_SWAP,
377    ID_REVERSE,
378    ID_BROADCAST
379  };
380  
381  enum EncBits : unsigned {
382  
383    // swizzle mode encodings
384  
385    QUAD_PERM_ENC         = 0x8000,
386    QUAD_PERM_ENC_MASK    = 0xFF00,
387  
388    BITMASK_PERM_ENC      = 0x0000,
389    BITMASK_PERM_ENC_MASK = 0x8000,
390  
391    // QUAD_PERM encodings
392  
393    LANE_MASK             = 0x3,
394    LANE_MAX              = LANE_MASK,
395    LANE_SHIFT            = 2,
396    LANE_NUM              = 4,
397  
398    // BITMASK_PERM encodings
399  
400    BITMASK_MASK          = 0x1F,
401    BITMASK_MAX           = BITMASK_MASK,
402    BITMASK_WIDTH         = 5,
403  
404    BITMASK_AND_SHIFT     = 0,
405    BITMASK_OR_SHIFT      = 5,
406    BITMASK_XOR_SHIFT     = 10
407  };
408  
409  } // namespace Swizzle
410  
411  namespace SDWA {
412  
413  enum SdwaSel : unsigned {
414    BYTE_0 = 0,
415    BYTE_1 = 1,
416    BYTE_2 = 2,
417    BYTE_3 = 3,
418    WORD_0 = 4,
419    WORD_1 = 5,
420    DWORD = 6,
421  };
422  
423  enum DstUnused : unsigned {
424    UNUSED_PAD = 0,
425    UNUSED_SEXT = 1,
426    UNUSED_PRESERVE = 2,
427  };
428  
429  enum SDWA9EncValues : unsigned {
430    SRC_SGPR_MASK = 0x100,
431    SRC_VGPR_MASK = 0xFF,
432    VOPC_DST_VCC_MASK = 0x80,
433    VOPC_DST_SGPR_MASK = 0x7F,
434  
435    SRC_VGPR_MIN = 0,
436    SRC_VGPR_MAX = 255,
437    SRC_SGPR_MIN = 256,
438    SRC_SGPR_MAX_SI = 357,
439    SRC_SGPR_MAX_GFX10 = 361,
440    SRC_TTMP_MIN = 364,
441    SRC_TTMP_MAX = 379,
442  };
443  
444  } // namespace SDWA
445  
446  namespace DPP {
447  
448  enum DppCtrl : unsigned {
449    QUAD_PERM_FIRST   = 0,
450    QUAD_PERM_ID      = 0xE4, // identity permutation
451    QUAD_PERM_LAST    = 0xFF,
452    DPP_UNUSED1       = 0x100,
453    ROW_SHL0          = 0x100,
454    ROW_SHL_FIRST     = 0x101,
455    ROW_SHL_LAST      = 0x10F,
456    DPP_UNUSED2       = 0x110,
457    ROW_SHR0          = 0x110,
458    ROW_SHR_FIRST     = 0x111,
459    ROW_SHR_LAST      = 0x11F,
460    DPP_UNUSED3       = 0x120,
461    ROW_ROR0          = 0x120,
462    ROW_ROR_FIRST     = 0x121,
463    ROW_ROR_LAST      = 0x12F,
464    WAVE_SHL1         = 0x130,
465    DPP_UNUSED4_FIRST = 0x131,
466    DPP_UNUSED4_LAST  = 0x133,
467    WAVE_ROL1         = 0x134,
468    DPP_UNUSED5_FIRST = 0x135,
469    DPP_UNUSED5_LAST  = 0x137,
470    WAVE_SHR1         = 0x138,
471    DPP_UNUSED6_FIRST = 0x139,
472    DPP_UNUSED6_LAST  = 0x13B,
473    WAVE_ROR1         = 0x13C,
474    DPP_UNUSED7_FIRST = 0x13D,
475    DPP_UNUSED7_LAST  = 0x13F,
476    ROW_MIRROR        = 0x140,
477    ROW_HALF_MIRROR   = 0x141,
478    BCAST15           = 0x142,
479    BCAST31           = 0x143,
480    DPP_UNUSED8_FIRST = 0x144,
481    DPP_UNUSED8_LAST  = 0x14F,
482    ROW_SHARE_FIRST   = 0x150,
483    ROW_SHARE_LAST    = 0x15F,
484    ROW_XMASK_FIRST   = 0x160,
485    ROW_XMASK_LAST    = 0x16F,
486    DPP_LAST          = ROW_XMASK_LAST
487  };
488  
489  enum DppFiMode {
490    DPP_FI_0  = 0,
491    DPP_FI_1  = 1,
492    DPP8_FI_0 = 0xE9,
493    DPP8_FI_1 = 0xEA,
494  };
495  
496  } // namespace DPP
497  } // namespace AMDGPU
498  
499  #define R_00B028_SPI_SHADER_PGM_RSRC1_PS                                0x00B028
500  #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS                                0x00B02C
501  #define   S_00B02C_EXTRA_LDS_SIZE(x)                                  (((x) & 0xFF) << 8)
502  #define R_00B128_SPI_SHADER_PGM_RSRC1_VS                                0x00B128
503  #define R_00B228_SPI_SHADER_PGM_RSRC1_GS                                0x00B228
504  #define R_00B328_SPI_SHADER_PGM_RSRC1_ES                                0x00B328
505  #define R_00B428_SPI_SHADER_PGM_RSRC1_HS                                0x00B428
506  #define R_00B528_SPI_SHADER_PGM_RSRC1_LS                                0x00B528
507  #define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
508  #define   S_00B028_VGPRS(x)                                           (((x) & 0x3F) << 0)
509  #define   S_00B028_SGPRS(x)                                           (((x) & 0x0F) << 6)
510  
511  #define R_00B84C_COMPUTE_PGM_RSRC2                                      0x00B84C
512  #define   S_00B84C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
513  #define   G_00B84C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
514  #define   C_00B84C_SCRATCH_EN                                         0xFFFFFFFE
515  #define   S_00B84C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
516  #define   G_00B84C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
517  #define   C_00B84C_USER_SGPR                                          0xFFFFFFC1
518  #define   S_00B84C_TRAP_HANDLER(x)                                    (((x) & 0x1) << 6)
519  #define   G_00B84C_TRAP_HANDLER(x)                                    (((x) >> 6) & 0x1)
520  #define   C_00B84C_TRAP_HANDLER                                       0xFFFFFFBF
521  #define   S_00B84C_TGID_X_EN(x)                                       (((x) & 0x1) << 7)
522  #define   G_00B84C_TGID_X_EN(x)                                       (((x) >> 7) & 0x1)
523  #define   C_00B84C_TGID_X_EN                                          0xFFFFFF7F
524  #define   S_00B84C_TGID_Y_EN(x)                                       (((x) & 0x1) << 8)
525  #define   G_00B84C_TGID_Y_EN(x)                                       (((x) >> 8) & 0x1)
526  #define   C_00B84C_TGID_Y_EN                                          0xFFFFFEFF
527  #define   S_00B84C_TGID_Z_EN(x)                                       (((x) & 0x1) << 9)
528  #define   G_00B84C_TGID_Z_EN(x)                                       (((x) >> 9) & 0x1)
529  #define   C_00B84C_TGID_Z_EN                                          0xFFFFFDFF
530  #define   S_00B84C_TG_SIZE_EN(x)                                      (((x) & 0x1) << 10)
531  #define   G_00B84C_TG_SIZE_EN(x)                                      (((x) >> 10) & 0x1)
532  #define   C_00B84C_TG_SIZE_EN                                         0xFFFFFBFF
533  #define   S_00B84C_TIDIG_COMP_CNT(x)                                  (((x) & 0x03) << 11)
534  #define   G_00B84C_TIDIG_COMP_CNT(x)                                  (((x) >> 11) & 0x03)
535  #define   C_00B84C_TIDIG_COMP_CNT                                     0xFFFFE7FF
536  /* CIK */
537  #define   S_00B84C_EXCP_EN_MSB(x)                                     (((x) & 0x03) << 13)
538  #define   G_00B84C_EXCP_EN_MSB(x)                                     (((x) >> 13) & 0x03)
539  #define   C_00B84C_EXCP_EN_MSB                                        0xFFFF9FFF
540  /*     */
541  #define   S_00B84C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 15)
542  #define   G_00B84C_LDS_SIZE(x)                                        (((x) >> 15) & 0x1FF)
543  #define   C_00B84C_LDS_SIZE                                           0xFF007FFF
544  #define   S_00B84C_EXCP_EN(x)                                         (((x) & 0x7F) << 24)
545  #define   G_00B84C_EXCP_EN(x)                                         (((x) >> 24) & 0x7F)
546  #define   C_00B84C_EXCP_EN
547  
548  #define R_0286CC_SPI_PS_INPUT_ENA                                       0x0286CC
549  #define R_0286D0_SPI_PS_INPUT_ADDR                                      0x0286D0
550  
551  #define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
552  #define   S_00B848_VGPRS(x)                                           (((x) & 0x3F) << 0)
553  #define   G_00B848_VGPRS(x)                                           (((x) >> 0) & 0x3F)
554  #define   C_00B848_VGPRS                                              0xFFFFFFC0
555  #define   S_00B848_SGPRS(x)                                           (((x) & 0x0F) << 6)
556  #define   G_00B848_SGPRS(x)                                           (((x) >> 6) & 0x0F)
557  #define   C_00B848_SGPRS                                              0xFFFFFC3F
558  #define   S_00B848_PRIORITY(x)                                        (((x) & 0x03) << 10)
559  #define   G_00B848_PRIORITY(x)                                        (((x) >> 10) & 0x03)
560  #define   C_00B848_PRIORITY                                           0xFFFFF3FF
561  #define   S_00B848_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
562  #define   G_00B848_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
563  #define   C_00B848_FLOAT_MODE                                         0xFFF00FFF
564  #define   S_00B848_PRIV(x)                                            (((x) & 0x1) << 20)
565  #define   G_00B848_PRIV(x)                                            (((x) >> 20) & 0x1)
566  #define   C_00B848_PRIV                                               0xFFEFFFFF
567  #define   S_00B848_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
568  #define   G_00B848_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
569  #define   C_00B848_DX10_CLAMP                                         0xFFDFFFFF
570  #define   S_00B848_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
571  #define   G_00B848_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
572  #define   C_00B848_DEBUG_MODE                                         0xFFBFFFFF
573  #define   S_00B848_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
574  #define   G_00B848_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
575  #define   C_00B848_IEEE_MODE                                          0xFF7FFFFF
576  #define   S_00B848_WGP_MODE(x)                                        (((x) & 0x1) << 29)
577  #define   G_00B848_WGP_MODE(x)                                        (((x) >> 29) & 0x1)
578  #define   C_00B848_WGP_MODE                                           0xDFFFFFFF
579  #define   S_00B848_MEM_ORDERED(x)                                     (((x) & 0x1) << 30)
580  #define   G_00B848_MEM_ORDERED(x)                                     (((x) >> 30) & 0x1)
581  #define   C_00B848_MEM_ORDERED                                        0xBFFFFFFF
582  #define   S_00B848_FWD_PROGRESS(x)                                    (((x) & 0x1) << 31)
583  #define   G_00B848_FWD_PROGRESS(x)                                    (((x) >> 31) & 0x1)
584  #define   C_00B848_FWD_PROGRESS                                       0x7FFFFFFF
585  
586  
587  // Helpers for setting FLOAT_MODE
588  #define FP_ROUND_ROUND_TO_NEAREST 0
589  #define FP_ROUND_ROUND_TO_INF 1
590  #define FP_ROUND_ROUND_TO_NEGINF 2
591  #define FP_ROUND_ROUND_TO_ZERO 3
592  
593  // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
594  // precision.
595  #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
596  #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
597  
598  #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
599  #define FP_DENORM_FLUSH_OUT 1
600  #define FP_DENORM_FLUSH_IN 2
601  #define FP_DENORM_FLUSH_NONE 3
602  
603  
604  // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
605  // precision.
606  #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
607  #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
608  
609  #define R_00B860_COMPUTE_TMPRING_SIZE                                   0x00B860
610  #define   S_00B860_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
611  
612  #define R_0286E8_SPI_TMPRING_SIZE                                       0x0286E8
613  #define   S_0286E8_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
614  
615  #define R_028B54_VGT_SHADER_STAGES_EN                                 0x028B54
616  #define   S_028B54_HS_W32_EN(x)                                       (((x) & 0x1) << 21)
617  #define   S_028B54_GS_W32_EN(x)                                       (((x) & 0x1) << 22)
618  #define   S_028B54_VS_W32_EN(x)                                       (((x) & 0x1) << 23)
619  #define R_0286D8_SPI_PS_IN_CONTROL                                    0x0286D8
620  #define   S_0286D8_PS_W32_EN(x)                                       (((x) & 0x1) << 15)
621  #define R_00B800_COMPUTE_DISPATCH_INITIATOR                           0x00B800
622  #define   S_00B800_CS_W32_EN(x)                                       (((x) & 0x1) << 15)
623  
624  #define R_SPILLED_SGPRS         0x4
625  #define R_SPILLED_VGPRS         0x8
626  } // End namespace llvm
627  
628  #endif
629