/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86InstrFoldTables.cpp | 5515 lookupFoldTableImpl(ArrayRef<X86MemoryFoldTableEntry> Table, unsigned RegOp) { in lookupFoldTableImpl() 5580 llvm::lookupTwoAddrFoldTable(unsigned RegOp) { in lookupTwoAddrFoldTable() 5585 llvm::lookupFoldTable(unsigned RegOp, unsigned OpNum) { in lookupFoldTable()
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D | X86MCInstLower.cpp | 351 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
D | LanaiInstPrinter.cpp | 214 const MCOperand &RegOp) { in printMemoryBaseRegister() 240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand() local 255 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRrOperand() local 276 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemSplsOperand() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/MCTargetDesc/ |
D | BPFInstPrinter.cpp | 67 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
D | AVRAsmPrinter.cpp | 96 const MachineOperand &RegOp = MI->getOperand(OpNum); in PrintAsmOperand() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
D | LanaiAsmPrinter.cpp | 130 unsigned RegOp = OpNo + 1; in PrintAsmOperand() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/AsmParser/ |
D | BPFAsmParser.cpp | 87 struct RegOp { struct 88 unsigned RegNum;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
D | SparcAsmParser.cpp | 230 struct RegOp { struct in __anond97033fd0211::SparcOperand 231 unsigned RegNum; 232 RegisterKind Kind;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/ |
D | AVRMCCodeEmitter.cpp | 137 auto RegOp = MI.getOperand(OpNo); in encodeMemri() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
D | X86Operand.h | 46 struct RegOp { struct 47 unsigned RegNo;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86MCCodeEmitter.cpp | 1606 unsigned RegOp = CurOp++; in encodeInstruction() local 1619 unsigned RegOp = CurOp++; in encodeInstruction() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
D | SystemZAsmParser.cpp | 105 struct RegOp { struct in __anon122763890111::SystemZOperand 106 RegisterKind Kind; 107 unsigned Num;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIFoldOperands.cpp | 1388 const MachineOperand *RegOp = nullptr; in isOMod() local 1439 const MachineOperand *RegOp; in tryFoldOMod() local
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D | AMDGPUMachineCFGStructurizer.cpp | 1882 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfBlock() local 2341 MachineOperand RegOp = in createIfRegion() local 2400 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfRegion() local
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D | SIInstrInfo.cpp | 875 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local 889 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local 1652 MachineOperand &RegOp, in swapRegAndNonRegOperand() 6419 auto &RegOp = MI.getOperand(1 + 2 * I); in getRegSequenceSubReg() local
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D | GCNHazardRecognizer.cpp | 126 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/AsmParser/ |
D | LanaiAsmParser.cpp | 120 struct RegOp { struct 121 unsigned RegNum;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | MachineInstrBuilder.h | 496 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
D | AArch64AsmParser.cpp | 310 struct RegOp { struct in __anona71ef61d0111::AArch64Operand 311 unsigned RegNum; 312 RegKind Kind; 313 int ElementWidth; 317 RegConstraintEqualityTy EqualityTy; 333 ShiftExtendOp ShiftExtend;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/ |
D | RISCVAsmParser.cpp | 226 struct RegOp { struct 227 Register RegNum;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64InstructionSelector.cpp | 629 MachineOperand &RegOp = I.getOperand(1); in selectSubregisterCopy() local 758 MachineOperand &RegOp = I.getOperand(1); in selectCopy() local 1649 MachineOperand &RegOp = I.getOperand(0); in select() local 4032 MachineOperand &RegOp = I.getOperand(1); in selectBuildVector() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsAsmPrinter.cpp | 586 unsigned RegOp = OpNum; in PrintAsmOperand() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMAsmPrinter.cpp | 388 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1; in PrintAsmOperand() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
D | AMDGPUAsmParser.cpp | 203 struct RegOp { struct in __anond10a7bc70111::AMDGPUOperand 204 unsigned RegNo; 205 Modifiers Mods;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonConstExtenders.cpp | 1760 const MachineOperand &RegOp = MI.getOperand(IsAddi ? 1 : 2); in replaceInstrExpr() local
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