1 /**********************************************************
2 * Copyright 2008-2013 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26 /**
27 * @file svga_cmd_vgpu10.c
28 *
29 * Command construction utility for the vgpu10 SVGA3D protocol.
30 *
31 * \author Mingcheng Chen
32 * \author Brian Paul
33 */
34
35
36 #include "svga_winsys.h"
37 #include "svga_resource_buffer.h"
38 #include "svga_resource_texture.h"
39 #include "svga_surface.h"
40 #include "svga_cmd.h"
41
42
43 /**
44 * Emit a surface relocation for RenderTargetViewId
45 */
46 static void
view_relocation(struct svga_winsys_context * swc,struct pipe_surface * surface,SVGA3dRenderTargetViewId * id,unsigned flags)47 view_relocation(struct svga_winsys_context *swc, // IN
48 struct pipe_surface *surface, // IN
49 SVGA3dRenderTargetViewId *id, // OUT
50 unsigned flags)
51 {
52 if (surface) {
53 struct svga_surface *s = svga_surface(surface);
54 assert(s->handle);
55 swc->surface_relocation(swc, id, NULL, s->handle, flags);
56 }
57 else {
58 swc->surface_relocation(swc, id, NULL, NULL, flags);
59 }
60 }
61
62
63 /**
64 * Emit a surface relocation for a ResourceId.
65 */
66 static void
surface_to_resourceid(struct svga_winsys_context * swc,struct svga_winsys_surface * surface,SVGA3dSurfaceId * sid,unsigned flags)67 surface_to_resourceid(struct svga_winsys_context *swc, // IN
68 struct svga_winsys_surface *surface, // IN
69 SVGA3dSurfaceId *sid, // OUT
70 unsigned flags) // IN
71 {
72 if (surface) {
73 swc->surface_relocation(swc, sid, NULL, surface, flags);
74 }
75 else {
76 swc->surface_relocation(swc, sid, NULL, NULL, flags);
77 }
78 }
79
80
81 #define SVGA3D_CREATE_COMMAND(CommandName, CommandCode) \
82 SVGA3dCmdDX##CommandName *cmd; \
83 { \
84 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_##CommandCode, \
85 sizeof(SVGA3dCmdDX##CommandName), 0); \
86 if (!cmd) \
87 return PIPE_ERROR_OUT_OF_MEMORY; \
88 }
89
90 #define SVGA3D_CREATE_CMD_COUNT(CommandName, CommandCode, ElementClassName) \
91 SVGA3dCmdDX##CommandName *cmd; \
92 { \
93 assert(count > 0); \
94 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_##CommandCode, \
95 sizeof(SVGA3dCmdDX##CommandName) + \
96 count * sizeof(ElementClassName), 0); \
97 if (!cmd) \
98 return PIPE_ERROR_OUT_OF_MEMORY; \
99 }
100
101 #define SVGA3D_COPY_BASIC(VariableName) \
102 { \
103 cmd->VariableName = VariableName; \
104 }
105
106 #define SVGA3D_COPY_BASIC_2(VariableName1, VariableName2) \
107 { \
108 SVGA3D_COPY_BASIC(VariableName1); \
109 SVGA3D_COPY_BASIC(VariableName2); \
110 }
111
112 #define SVGA3D_COPY_BASIC_3(VariableName1, VariableName2, VariableName3) \
113 { \
114 SVGA3D_COPY_BASIC_2(VariableName1, VariableName2); \
115 SVGA3D_COPY_BASIC(VariableName3); \
116 }
117
118 #define SVGA3D_COPY_BASIC_4(VariableName1, VariableName2, VariableName3, \
119 VariableName4) \
120 { \
121 SVGA3D_COPY_BASIC_2(VariableName1, VariableName2); \
122 SVGA3D_COPY_BASIC_2(VariableName3, VariableName4); \
123 }
124
125 #define SVGA3D_COPY_BASIC_5(VariableName1, VariableName2, VariableName3, \
126 VariableName4, VariableName5) \
127 {\
128 SVGA3D_COPY_BASIC_3(VariableName1, VariableName2, VariableName3); \
129 SVGA3D_COPY_BASIC_2(VariableName4, VariableName5); \
130 }
131
132 #define SVGA3D_COPY_BASIC_6(VariableName1, VariableName2, VariableName3, \
133 VariableName4, VariableName5, VariableName6) \
134 {\
135 SVGA3D_COPY_BASIC_3(VariableName1, VariableName2, VariableName3); \
136 SVGA3D_COPY_BASIC_3(VariableName4, VariableName5, VariableName6); \
137 }
138
139 #define SVGA3D_COPY_BASIC_7(VariableName1, VariableName2, VariableName3, \
140 VariableName4, VariableName5, VariableName6, \
141 VariableName7) \
142 {\
143 SVGA3D_COPY_BASIC_4(VariableName1, VariableName2, VariableName3, \
144 VariableName4); \
145 SVGA3D_COPY_BASIC_3(VariableName5, VariableName6, VariableName7); \
146 }
147
148 #define SVGA3D_COPY_BASIC_8(VariableName1, VariableName2, VariableName3, \
149 VariableName4, VariableName5, VariableName6, \
150 VariableName7, VariableName8) \
151 {\
152 SVGA3D_COPY_BASIC_4(VariableName1, VariableName2, VariableName3, \
153 VariableName4); \
154 SVGA3D_COPY_BASIC_4(VariableName5, VariableName6, VariableName7, \
155 VariableName8); \
156 }
157
158 #define SVGA3D_COPY_BASIC_9(VariableName1, VariableName2, VariableName3, \
159 VariableName4, VariableName5, VariableName6, \
160 VariableName7, VariableName8, VariableName9) \
161 {\
162 SVGA3D_COPY_BASIC_5(VariableName1, VariableName2, VariableName3, \
163 VariableName4, VariableName5); \
164 SVGA3D_COPY_BASIC_4(VariableName6, VariableName7, VariableName8, \
165 VariableName9); \
166 }
167
168
169 enum pipe_error
SVGA3D_vgpu10_PredCopyRegion(struct svga_winsys_context * swc,struct svga_winsys_surface * dstSurf,uint32 dstSubResource,struct svga_winsys_surface * srcSurf,uint32 srcSubResource,const SVGA3dCopyBox * box)170 SVGA3D_vgpu10_PredCopyRegion(struct svga_winsys_context *swc,
171 struct svga_winsys_surface *dstSurf,
172 uint32 dstSubResource,
173 struct svga_winsys_surface *srcSurf,
174 uint32 srcSubResource,
175 const SVGA3dCopyBox *box)
176 {
177 SVGA3dCmdDXPredCopyRegion *cmd =
178 SVGA3D_FIFOReserve(swc,
179 SVGA_3D_CMD_DX_PRED_COPY_REGION,
180 sizeof(SVGA3dCmdDXPredCopyRegion),
181 2); /* two relocations */
182 if (!cmd)
183 return PIPE_ERROR_OUT_OF_MEMORY;
184
185 swc->surface_relocation(swc, &cmd->dstSid, NULL, dstSurf, SVGA_RELOC_WRITE);
186 swc->surface_relocation(swc, &cmd->srcSid, NULL, srcSurf, SVGA_RELOC_READ);
187 cmd->dstSubResource = dstSubResource;
188 cmd->srcSubResource = srcSubResource;
189 cmd->box = *box;
190
191 swc->commit(swc);
192
193 return PIPE_OK;
194 }
195
196
197 enum pipe_error
SVGA3D_vgpu10_PredCopy(struct svga_winsys_context * swc,struct svga_winsys_surface * dstSurf,struct svga_winsys_surface * srcSurf)198 SVGA3D_vgpu10_PredCopy(struct svga_winsys_context *swc,
199 struct svga_winsys_surface *dstSurf,
200 struct svga_winsys_surface *srcSurf)
201 {
202 SVGA3dCmdDXPredCopy *cmd =
203 SVGA3D_FIFOReserve(swc,
204 SVGA_3D_CMD_DX_PRED_COPY,
205 sizeof(SVGA3dCmdDXPredCopy),
206 2); /* two relocations */
207 if (!cmd)
208 return PIPE_ERROR_OUT_OF_MEMORY;
209
210 swc->surface_relocation(swc, &cmd->dstSid, NULL, dstSurf, SVGA_RELOC_WRITE);
211 swc->surface_relocation(swc, &cmd->srcSid, NULL, srcSurf, SVGA_RELOC_READ);
212
213 swc->commit(swc);
214
215 return PIPE_OK;
216 }
217
218 enum pipe_error
SVGA3D_vgpu10_SetViewports(struct svga_winsys_context * swc,unsigned count,const SVGA3dViewport * viewports)219 SVGA3D_vgpu10_SetViewports(struct svga_winsys_context *swc,
220 unsigned count,
221 const SVGA3dViewport *viewports)
222 {
223 SVGA3D_CREATE_CMD_COUNT(SetViewports, SET_VIEWPORTS, SVGA3dViewport);
224
225 cmd->pad0 = 0;
226 memcpy(cmd + 1, viewports, count * sizeof(SVGA3dViewport));
227
228 swc->commit(swc);
229 return PIPE_OK;
230 }
231
232
233 enum pipe_error
SVGA3D_vgpu10_SetShader(struct svga_winsys_context * swc,SVGA3dShaderType type,struct svga_winsys_gb_shader * gbshader,SVGA3dShaderId shaderId)234 SVGA3D_vgpu10_SetShader(struct svga_winsys_context *swc,
235 SVGA3dShaderType type,
236 struct svga_winsys_gb_shader *gbshader,
237 SVGA3dShaderId shaderId)
238 {
239 SVGA3dCmdDXSetShader *cmd = SVGA3D_FIFOReserve(swc,
240 SVGA_3D_CMD_DX_SET_SHADER,
241 sizeof *cmd,
242 1); /* one relocation */
243 if (!cmd)
244 return PIPE_ERROR_OUT_OF_MEMORY;
245
246 swc->shader_relocation(swc, &cmd->shaderId, NULL, NULL, gbshader, 0);
247
248 cmd->type = type;
249 cmd->shaderId = shaderId;
250 swc->commit(swc);
251
252 return PIPE_OK;
253 }
254
255
256 enum pipe_error
SVGA3D_vgpu10_SetShaderResources(struct svga_winsys_context * swc,SVGA3dShaderType type,uint32 startView,unsigned count,const SVGA3dShaderResourceViewId ids[],struct svga_winsys_surface ** views)257 SVGA3D_vgpu10_SetShaderResources(struct svga_winsys_context *swc,
258 SVGA3dShaderType type,
259 uint32 startView,
260 unsigned count,
261 const SVGA3dShaderResourceViewId ids[],
262 struct svga_winsys_surface **views)
263 {
264 SVGA3dCmdDXSetShaderResources *cmd;
265 SVGA3dShaderResourceViewId *cmd_ids;
266 unsigned i;
267
268 cmd = SVGA3D_FIFOReserve(swc,
269 SVGA_3D_CMD_DX_SET_SHADER_RESOURCES,
270 sizeof(SVGA3dCmdDXSetShaderResources) +
271 count * sizeof(SVGA3dShaderResourceViewId),
272 count); /* 'count' relocations */
273 if (!cmd)
274 return PIPE_ERROR_OUT_OF_MEMORY;
275
276
277 cmd->type = type;
278 cmd->startView = startView;
279
280 cmd_ids = (SVGA3dShaderResourceViewId *) (cmd + 1);
281 for (i = 0; i < count; i++) {
282 swc->surface_relocation(swc, cmd_ids + i, NULL, views[i],
283 SVGA_RELOC_READ);
284 cmd_ids[i] = ids[i];
285 }
286
287 swc->commit(swc);
288 return PIPE_OK;
289 }
290
291
292 enum pipe_error
SVGA3D_vgpu10_SetSamplers(struct svga_winsys_context * swc,unsigned count,uint32 startSampler,SVGA3dShaderType type,const SVGA3dSamplerId * samplerIds)293 SVGA3D_vgpu10_SetSamplers(struct svga_winsys_context *swc,
294 unsigned count,
295 uint32 startSampler,
296 SVGA3dShaderType type,
297 const SVGA3dSamplerId *samplerIds)
298 {
299 SVGA3D_CREATE_CMD_COUNT(SetSamplers, SET_SAMPLERS, SVGA3dSamplerId);
300
301 SVGA3D_COPY_BASIC_2(startSampler, type);
302 memcpy(cmd + 1, samplerIds, count * sizeof(SVGA3dSamplerId));
303
304 swc->commit(swc);
305 return PIPE_OK;
306 }
307
308
309 enum pipe_error
SVGA3D_vgpu10_ClearRenderTargetView(struct svga_winsys_context * swc,struct pipe_surface * color_surf,const float * rgba)310 SVGA3D_vgpu10_ClearRenderTargetView(struct svga_winsys_context *swc,
311 struct pipe_surface *color_surf,
312 const float *rgba)
313 {
314 SVGA3dCmdDXClearRenderTargetView *cmd;
315 struct svga_surface *ss = svga_surface(color_surf);
316
317 cmd = SVGA3D_FIFOReserve(swc,
318 SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW,
319 sizeof(SVGA3dCmdDXClearRenderTargetView),
320 1); /* one relocation */
321 if (!cmd)
322 return PIPE_ERROR_OUT_OF_MEMORY;
323
324
325 /* NOTE: The following is pretty tricky. We need to emit a view/surface
326 * relocation and we have to provide a pointer to an ID which lies in
327 * the bounds of the command space which we just allocated. However,
328 * we then need to overwrite it with the original RenderTargetViewId.
329 */
330 view_relocation(swc, color_surf, &cmd->renderTargetViewId,
331 SVGA_RELOC_WRITE);
332 cmd->renderTargetViewId = ss->view_id;
333
334 COPY_4V(cmd->rgba.value, rgba);
335
336 swc->commit(swc);
337 return PIPE_OK;
338 }
339
340
341 enum pipe_error
SVGA3D_vgpu10_SetRenderTargets(struct svga_winsys_context * swc,unsigned color_count,struct pipe_surface ** color_surfs,struct pipe_surface * depth_stencil_surf)342 SVGA3D_vgpu10_SetRenderTargets(struct svga_winsys_context *swc,
343 unsigned color_count,
344 struct pipe_surface **color_surfs,
345 struct pipe_surface *depth_stencil_surf)
346 {
347 const unsigned surf_count = color_count + 1;
348 SVGA3dCmdDXSetRenderTargets *cmd;
349 SVGA3dRenderTargetViewId *ctarget;
350 struct svga_surface *ss;
351 unsigned i;
352
353 assert(surf_count > 0);
354
355 cmd = SVGA3D_FIFOReserve(swc,
356 SVGA_3D_CMD_DX_SET_RENDERTARGETS,
357 sizeof(SVGA3dCmdDXSetRenderTargets) +
358 color_count * sizeof(SVGA3dRenderTargetViewId),
359 surf_count); /* 'surf_count' relocations */
360 if (!cmd)
361 return PIPE_ERROR_OUT_OF_MEMORY;
362
363 /* NOTE: See earlier comment about the tricky handling of the ViewIds.
364 */
365
366 /* Depth / Stencil buffer */
367 if (depth_stencil_surf) {
368 ss = svga_surface(depth_stencil_surf);
369 view_relocation(swc, depth_stencil_surf, &cmd->depthStencilViewId,
370 SVGA_RELOC_WRITE);
371 cmd->depthStencilViewId = ss->view_id;
372 }
373 else {
374 /* no depth/stencil buffer - still need a relocation */
375 view_relocation(swc, NULL, &cmd->depthStencilViewId,
376 SVGA_RELOC_WRITE);
377 cmd->depthStencilViewId = SVGA3D_INVALID_ID;
378 }
379
380 /* Color buffers */
381 ctarget = (SVGA3dRenderTargetViewId *) &cmd[1];
382 for (i = 0; i < color_count; i++) {
383 if (color_surfs[i]) {
384 ss = svga_surface(color_surfs[i]);
385 view_relocation(swc, color_surfs[i], ctarget + i, SVGA_RELOC_WRITE);
386 ctarget[i] = ss->view_id;
387 }
388 else {
389 view_relocation(swc, NULL, ctarget + i, SVGA_RELOC_WRITE);
390 ctarget[i] = SVGA3D_INVALID_ID;
391 }
392 }
393
394 swc->commit(swc);
395 return PIPE_OK;
396 }
397
398
399 enum pipe_error
SVGA3D_vgpu10_SetBlendState(struct svga_winsys_context * swc,SVGA3dBlendStateId blendId,const float * blendFactor,uint32 sampleMask)400 SVGA3D_vgpu10_SetBlendState(struct svga_winsys_context *swc,
401 SVGA3dBlendStateId blendId,
402 const float *blendFactor,
403 uint32 sampleMask)
404 {
405 SVGA3D_CREATE_COMMAND(SetBlendState, SET_BLEND_STATE);
406
407 SVGA3D_COPY_BASIC_2(blendId, sampleMask);
408 memcpy(cmd->blendFactor, blendFactor, sizeof(float) * 4);
409
410 swc->commit(swc);
411 return PIPE_OK;
412 }
413
414 enum pipe_error
SVGA3D_vgpu10_SetDepthStencilState(struct svga_winsys_context * swc,SVGA3dDepthStencilStateId depthStencilId,uint32 stencilRef)415 SVGA3D_vgpu10_SetDepthStencilState(struct svga_winsys_context *swc,
416 SVGA3dDepthStencilStateId depthStencilId,
417 uint32 stencilRef)
418 {
419 SVGA3D_CREATE_COMMAND(SetDepthStencilState, SET_DEPTHSTENCIL_STATE);
420
421 SVGA3D_COPY_BASIC_2(depthStencilId, stencilRef);
422
423 swc->commit(swc);
424 return PIPE_OK;
425 }
426
427 enum pipe_error
SVGA3D_vgpu10_SetRasterizerState(struct svga_winsys_context * swc,SVGA3dRasterizerStateId rasterizerId)428 SVGA3D_vgpu10_SetRasterizerState(struct svga_winsys_context *swc,
429 SVGA3dRasterizerStateId rasterizerId)
430 {
431 SVGA3D_CREATE_COMMAND(SetRasterizerState, SET_RASTERIZER_STATE);
432
433 cmd->rasterizerId = rasterizerId;
434
435 swc->commit(swc);
436 return PIPE_OK;
437 }
438
439 enum pipe_error
SVGA3D_vgpu10_SetPredication(struct svga_winsys_context * swc,SVGA3dQueryId queryId,uint32 predicateValue)440 SVGA3D_vgpu10_SetPredication(struct svga_winsys_context *swc,
441 SVGA3dQueryId queryId,
442 uint32 predicateValue)
443 {
444 SVGA3dCmdDXSetPredication *cmd;
445
446 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_SET_PREDICATION,
447 sizeof *cmd, 0);
448
449 if (!cmd)
450 return PIPE_ERROR_OUT_OF_MEMORY;
451
452 cmd->queryId = queryId;
453 cmd->predicateValue = predicateValue;
454 swc->commit(swc);
455 return PIPE_OK;
456 }
457
458 enum pipe_error
SVGA3D_vgpu10_SetSOTargets(struct svga_winsys_context * swc,unsigned count,const SVGA3dSoTarget * targets,struct svga_winsys_surface ** surfaces)459 SVGA3D_vgpu10_SetSOTargets(struct svga_winsys_context *swc,
460 unsigned count,
461 const SVGA3dSoTarget *targets,
462 struct svga_winsys_surface **surfaces)
463 {
464 SVGA3dCmdDXSetSOTargets *cmd;
465 SVGA3dSoTarget *sot;
466 unsigned i;
467
468 cmd = SVGA3D_FIFOReserve(swc,
469 SVGA_3D_CMD_DX_SET_SOTARGETS,
470 sizeof(SVGA3dCmdDXSetSOTargets) +
471 count * sizeof(SVGA3dSoTarget),
472 count);
473
474 if (!cmd)
475 return PIPE_ERROR_OUT_OF_MEMORY;
476
477 cmd->pad0 = 0;
478 sot = (SVGA3dSoTarget *)(cmd + 1);
479 for (i = 0; i < count; i++, sot++) {
480 if (surfaces[i]) {
481 sot->offset = targets[i].offset;
482 sot->sizeInBytes = targets[i].sizeInBytes;
483 swc->surface_relocation(swc, &sot->sid, NULL, surfaces[i],
484 SVGA_RELOC_WRITE);
485 }
486 else {
487 sot->offset = 0;
488 sot->sizeInBytes = ~0u;
489 swc->surface_relocation(swc, &sot->sid, NULL, NULL,
490 SVGA_RELOC_WRITE);
491 }
492 }
493 swc->commit(swc);
494 return PIPE_OK;
495 }
496
497 enum pipe_error
SVGA3D_vgpu10_SetScissorRects(struct svga_winsys_context * swc,unsigned count,const SVGASignedRect * rects)498 SVGA3D_vgpu10_SetScissorRects(struct svga_winsys_context *swc,
499 unsigned count,
500 const SVGASignedRect *rects)
501 {
502 SVGA3dCmdDXSetScissorRects *cmd;
503
504 assert(count > 0);
505 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_SET_SCISSORRECTS,
506 sizeof(SVGA3dCmdDXSetScissorRects) +
507 count * sizeof(SVGASignedRect),
508 0);
509 if (!cmd)
510 return PIPE_ERROR_OUT_OF_MEMORY;
511
512 cmd->pad0 = 0;
513 memcpy(cmd + 1, rects, count * sizeof(SVGASignedRect));
514
515 swc->commit(swc);
516 return PIPE_OK;
517 }
518
519 enum pipe_error
SVGA3D_vgpu10_SetStreamOutput(struct svga_winsys_context * swc,SVGA3dStreamOutputId soid)520 SVGA3D_vgpu10_SetStreamOutput(struct svga_winsys_context *swc,
521 SVGA3dStreamOutputId soid)
522 {
523 SVGA3D_CREATE_COMMAND(SetStreamOutput, SET_STREAMOUTPUT);
524
525 cmd->soid = soid;
526
527 swc->commit(swc);
528 return PIPE_OK;
529 }
530
531 enum pipe_error
SVGA3D_vgpu10_Draw(struct svga_winsys_context * swc,uint32 vertexCount,uint32 startVertexLocation)532 SVGA3D_vgpu10_Draw(struct svga_winsys_context *swc,
533 uint32 vertexCount,
534 uint32 startVertexLocation)
535 {
536 SVGA3D_CREATE_COMMAND(Draw, DRAW);
537
538 SVGA3D_COPY_BASIC_2(vertexCount, startVertexLocation);
539
540 swc->hints |= SVGA_HINT_FLAG_CAN_PRE_FLUSH;
541 swc->commit(swc);
542 swc->num_draw_commands++;
543 return PIPE_OK;
544 }
545
546 enum pipe_error
SVGA3D_vgpu10_DrawIndexed(struct svga_winsys_context * swc,uint32 indexCount,uint32 startIndexLocation,int32 baseVertexLocation)547 SVGA3D_vgpu10_DrawIndexed(struct svga_winsys_context *swc,
548 uint32 indexCount,
549 uint32 startIndexLocation,
550 int32 baseVertexLocation)
551 {
552 SVGA3D_CREATE_COMMAND(DrawIndexed, DRAW_INDEXED);
553
554 SVGA3D_COPY_BASIC_3(indexCount, startIndexLocation,
555 baseVertexLocation);
556
557 swc->hints |= SVGA_HINT_FLAG_CAN_PRE_FLUSH;
558 swc->commit(swc);
559 swc->num_draw_commands++;
560 return PIPE_OK;
561 }
562
563 enum pipe_error
SVGA3D_vgpu10_DrawInstanced(struct svga_winsys_context * swc,uint32 vertexCountPerInstance,uint32 instanceCount,uint32 startVertexLocation,uint32 startInstanceLocation)564 SVGA3D_vgpu10_DrawInstanced(struct svga_winsys_context *swc,
565 uint32 vertexCountPerInstance,
566 uint32 instanceCount,
567 uint32 startVertexLocation,
568 uint32 startInstanceLocation)
569 {
570 SVGA3D_CREATE_COMMAND(DrawInstanced, DRAW_INSTANCED);
571
572 SVGA3D_COPY_BASIC_4(vertexCountPerInstance, instanceCount,
573 startVertexLocation, startInstanceLocation);
574
575 swc->hints |= SVGA_HINT_FLAG_CAN_PRE_FLUSH;
576 swc->commit(swc);
577 swc->num_draw_commands++;
578 return PIPE_OK;
579 }
580
581 enum pipe_error
SVGA3D_vgpu10_DrawIndexedInstanced(struct svga_winsys_context * swc,uint32 indexCountPerInstance,uint32 instanceCount,uint32 startIndexLocation,int32 baseVertexLocation,uint32 startInstanceLocation)582 SVGA3D_vgpu10_DrawIndexedInstanced(struct svga_winsys_context *swc,
583 uint32 indexCountPerInstance,
584 uint32 instanceCount,
585 uint32 startIndexLocation,
586 int32 baseVertexLocation,
587 uint32 startInstanceLocation)
588 {
589 SVGA3D_CREATE_COMMAND(DrawIndexedInstanced, DRAW_INDEXED_INSTANCED);
590
591 SVGA3D_COPY_BASIC_5(indexCountPerInstance, instanceCount,
592 startIndexLocation, baseVertexLocation,
593 startInstanceLocation);
594
595
596 swc->hints |= SVGA_HINT_FLAG_CAN_PRE_FLUSH;
597 swc->commit(swc);
598 swc->num_draw_commands++;
599 return PIPE_OK;
600 }
601
602 enum pipe_error
SVGA3D_vgpu10_DrawAuto(struct svga_winsys_context * swc)603 SVGA3D_vgpu10_DrawAuto(struct svga_winsys_context *swc)
604 {
605 SVGA3D_CREATE_COMMAND(DrawAuto, DRAW_AUTO);
606
607 cmd->pad0 = 0;
608 swc->hints |= SVGA_HINT_FLAG_CAN_PRE_FLUSH;
609 swc->commit(swc);
610 swc->num_draw_commands++;
611 return PIPE_OK;
612 }
613
614 enum pipe_error
SVGA3D_vgpu10_DefineQuery(struct svga_winsys_context * swc,SVGA3dQueryId queryId,SVGA3dQueryType type,SVGA3dDXQueryFlags flags)615 SVGA3D_vgpu10_DefineQuery(struct svga_winsys_context *swc,
616 SVGA3dQueryId queryId,
617 SVGA3dQueryType type,
618 SVGA3dDXQueryFlags flags)
619 {
620 SVGA3D_CREATE_COMMAND(DefineQuery, DEFINE_QUERY);
621
622 SVGA3D_COPY_BASIC_3(queryId, type, flags);
623
624 swc->commit(swc);
625 return PIPE_OK;
626 }
627
628 enum pipe_error
SVGA3D_vgpu10_DestroyQuery(struct svga_winsys_context * swc,SVGA3dQueryId queryId)629 SVGA3D_vgpu10_DestroyQuery(struct svga_winsys_context *swc,
630 SVGA3dQueryId queryId)
631 {
632 SVGA3D_CREATE_COMMAND(DestroyQuery, DESTROY_QUERY);
633
634 cmd->queryId = queryId;
635
636 swc->commit(swc);
637 return PIPE_OK;
638 }
639
640 enum pipe_error
SVGA3D_vgpu10_BindQuery(struct svga_winsys_context * swc,struct svga_winsys_gb_query * gbQuery,SVGA3dQueryId queryId)641 SVGA3D_vgpu10_BindQuery(struct svga_winsys_context *swc,
642 struct svga_winsys_gb_query *gbQuery,
643 SVGA3dQueryId queryId)
644 {
645 SVGA3dCmdDXBindQuery *cmd = SVGA3D_FIFOReserve(swc,
646 SVGA_3D_CMD_DX_BIND_QUERY,
647 sizeof *cmd,
648 1);
649 if (!cmd)
650 return PIPE_ERROR_OUT_OF_MEMORY;
651
652 cmd->queryId = queryId;
653 swc->query_relocation(swc, &cmd->mobid, gbQuery);
654
655 swc->commit(swc);
656 return PIPE_OK;
657 }
658
659 enum pipe_error
SVGA3D_vgpu10_SetQueryOffset(struct svga_winsys_context * swc,SVGA3dQueryId queryId,uint32 mobOffset)660 SVGA3D_vgpu10_SetQueryOffset(struct svga_winsys_context *swc,
661 SVGA3dQueryId queryId,
662 uint32 mobOffset)
663 {
664 SVGA3D_CREATE_COMMAND(SetQueryOffset, SET_QUERY_OFFSET);
665 SVGA3D_COPY_BASIC_2(queryId, mobOffset);
666 swc->commit(swc);
667 return PIPE_OK;
668 }
669
670 enum pipe_error
SVGA3D_vgpu10_BeginQuery(struct svga_winsys_context * swc,SVGA3dQueryId queryId)671 SVGA3D_vgpu10_BeginQuery(struct svga_winsys_context *swc,
672 SVGA3dQueryId queryId)
673 {
674 SVGA3D_CREATE_COMMAND(BeginQuery, BEGIN_QUERY);
675 cmd->queryId = queryId;
676 swc->commit(swc);
677 return PIPE_OK;
678 }
679
680 enum pipe_error
SVGA3D_vgpu10_EndQuery(struct svga_winsys_context * swc,SVGA3dQueryId queryId)681 SVGA3D_vgpu10_EndQuery(struct svga_winsys_context *swc,
682 SVGA3dQueryId queryId)
683 {
684 SVGA3D_CREATE_COMMAND(EndQuery, END_QUERY);
685 cmd->queryId = queryId;
686 swc->commit(swc);
687 return PIPE_OK;
688 }
689
690
691 enum pipe_error
SVGA3D_vgpu10_ClearDepthStencilView(struct svga_winsys_context * swc,struct pipe_surface * ds_surf,uint16 flags,uint16 stencil,float depth)692 SVGA3D_vgpu10_ClearDepthStencilView(struct svga_winsys_context *swc,
693 struct pipe_surface *ds_surf,
694 uint16 flags,
695 uint16 stencil,
696 float depth)
697 {
698 SVGA3dCmdDXClearDepthStencilView *cmd;
699 struct svga_surface *ss = svga_surface(ds_surf);
700
701 cmd = SVGA3D_FIFOReserve(swc,
702 SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW,
703 sizeof(SVGA3dCmdDXClearDepthStencilView),
704 1); /* one relocation */
705 if (!cmd)
706 return PIPE_ERROR_OUT_OF_MEMORY;
707
708 /* NOTE: The following is pretty tricky. We need to emit a view/surface
709 * relocation and we have to provide a pointer to an ID which lies in
710 * the bounds of the command space which we just allocated. However,
711 * we then need to overwrite it with the original DepthStencilViewId.
712 */
713 view_relocation(swc, ds_surf, &cmd->depthStencilViewId,
714 SVGA_RELOC_WRITE);
715 cmd->depthStencilViewId = ss->view_id;
716 cmd->flags = flags;
717 cmd->stencil = stencil;
718 cmd->depth = depth;
719
720 swc->commit(swc);
721 return PIPE_OK;
722 }
723
724 enum pipe_error
SVGA3D_vgpu10_DefineShaderResourceView(struct svga_winsys_context * swc,SVGA3dShaderResourceViewId shaderResourceViewId,struct svga_winsys_surface * surface,SVGA3dSurfaceFormat format,SVGA3dResourceType resourceDimension,const SVGA3dShaderResourceViewDesc * desc)725 SVGA3D_vgpu10_DefineShaderResourceView(struct svga_winsys_context *swc,
726 SVGA3dShaderResourceViewId shaderResourceViewId,
727 struct svga_winsys_surface *surface,
728 SVGA3dSurfaceFormat format,
729 SVGA3dResourceType resourceDimension,
730 const SVGA3dShaderResourceViewDesc *desc)
731 {
732 SVGA3dCmdDXDefineShaderResourceView *cmd;
733
734 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW,
735 sizeof(SVGA3dCmdDXDefineShaderResourceView),
736 1); /* one relocation */
737 if (!cmd)
738 return PIPE_ERROR_OUT_OF_MEMORY;
739
740 SVGA3D_COPY_BASIC_3(shaderResourceViewId, format, resourceDimension);
741
742 swc->surface_relocation(swc, &cmd->sid, NULL, surface,
743 SVGA_RELOC_READ);
744
745 cmd->desc = *desc;
746
747 swc->commit(swc);
748 return PIPE_OK;
749 }
750
751 enum pipe_error
SVGA3D_vgpu10_DestroyShaderResourceView(struct svga_winsys_context * swc,SVGA3dShaderResourceViewId shaderResourceViewId)752 SVGA3D_vgpu10_DestroyShaderResourceView(struct svga_winsys_context *swc,
753 SVGA3dShaderResourceViewId shaderResourceViewId)
754 {
755 SVGA3D_CREATE_COMMAND(DestroyShaderResourceView,
756 DESTROY_SHADERRESOURCE_VIEW);
757
758 cmd->shaderResourceViewId = shaderResourceViewId;
759
760 swc->commit(swc);
761 return PIPE_OK;
762 }
763
764
765 enum pipe_error
SVGA3D_vgpu10_DefineRenderTargetView(struct svga_winsys_context * swc,SVGA3dRenderTargetViewId renderTargetViewId,struct svga_winsys_surface * surface,SVGA3dSurfaceFormat format,SVGA3dResourceType resourceDimension,const SVGA3dRenderTargetViewDesc * desc)766 SVGA3D_vgpu10_DefineRenderTargetView(struct svga_winsys_context *swc,
767 SVGA3dRenderTargetViewId renderTargetViewId,
768 struct svga_winsys_surface *surface,
769 SVGA3dSurfaceFormat format,
770 SVGA3dResourceType resourceDimension,
771 const SVGA3dRenderTargetViewDesc *desc)
772 {
773 SVGA3dCmdDXDefineRenderTargetView *cmd;
774
775 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW,
776 sizeof(SVGA3dCmdDXDefineRenderTargetView),
777 1); /* one relocation */
778 if (!cmd)
779 return PIPE_ERROR_OUT_OF_MEMORY;
780
781 SVGA3D_COPY_BASIC_3(renderTargetViewId, format, resourceDimension);
782 cmd->desc = *desc;
783
784 surface_to_resourceid(swc, surface,
785 &cmd->sid,
786 SVGA_RELOC_READ | SVGA_RELOC_WRITE);
787
788 swc->commit(swc);
789 return PIPE_OK;
790 }
791
792 enum pipe_error
SVGA3D_vgpu10_DestroyRenderTargetView(struct svga_winsys_context * swc,SVGA3dRenderTargetViewId renderTargetViewId)793 SVGA3D_vgpu10_DestroyRenderTargetView(struct svga_winsys_context *swc,
794 SVGA3dRenderTargetViewId renderTargetViewId)
795 {
796 SVGA3D_CREATE_COMMAND(DestroyRenderTargetView, DESTROY_RENDERTARGET_VIEW);
797
798 cmd->renderTargetViewId = renderTargetViewId;
799
800 swc->commit(swc);
801 return PIPE_OK;
802 }
803
804
805 enum pipe_error
SVGA3D_vgpu10_DefineDepthStencilView(struct svga_winsys_context * swc,SVGA3dDepthStencilViewId depthStencilViewId,struct svga_winsys_surface * surface,SVGA3dSurfaceFormat format,SVGA3dResourceType resourceDimension,const SVGA3dRenderTargetViewDesc * desc)806 SVGA3D_vgpu10_DefineDepthStencilView(struct svga_winsys_context *swc,
807 SVGA3dDepthStencilViewId depthStencilViewId,
808 struct svga_winsys_surface *surface,
809 SVGA3dSurfaceFormat format,
810 SVGA3dResourceType resourceDimension,
811 const SVGA3dRenderTargetViewDesc *desc)
812 {
813 SVGA3dCmdDXDefineDepthStencilView *cmd;
814
815 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW,
816 sizeof(SVGA3dCmdDXDefineDepthStencilView),
817 1); /* one relocation */
818 if (!cmd)
819 return PIPE_ERROR_OUT_OF_MEMORY;
820
821 SVGA3D_COPY_BASIC_3(depthStencilViewId, format, resourceDimension);
822 cmd->mipSlice = desc->tex.mipSlice;
823 cmd->firstArraySlice = desc->tex.firstArraySlice;
824 cmd->arraySize = desc->tex.arraySize;
825 cmd->flags = 0;
826 cmd->pad0 = 0;
827 cmd->pad1 = 0;
828
829 surface_to_resourceid(swc, surface,
830 &cmd->sid,
831 SVGA_RELOC_READ | SVGA_RELOC_WRITE);
832
833 swc->commit(swc);
834 return PIPE_OK;
835 }
836
837 enum pipe_error
SVGA3D_vgpu10_DestroyDepthStencilView(struct svga_winsys_context * swc,SVGA3dDepthStencilViewId depthStencilViewId)838 SVGA3D_vgpu10_DestroyDepthStencilView(struct svga_winsys_context *swc,
839 SVGA3dDepthStencilViewId depthStencilViewId)
840 {
841 SVGA3D_CREATE_COMMAND(DestroyDepthStencilView, DESTROY_DEPTHSTENCIL_VIEW);
842
843 cmd->depthStencilViewId = depthStencilViewId;
844
845 swc->commit(swc);
846 return PIPE_OK;
847 }
848
849 enum pipe_error
SVGA3D_vgpu10_DefineElementLayout(struct svga_winsys_context * swc,unsigned count,SVGA3dElementLayoutId elementLayoutId,const SVGA3dInputElementDesc * elements)850 SVGA3D_vgpu10_DefineElementLayout(struct svga_winsys_context *swc,
851 unsigned count,
852 SVGA3dElementLayoutId elementLayoutId,
853 const SVGA3dInputElementDesc *elements)
854 {
855 SVGA3dCmdDXDefineElementLayout *cmd;
856 unsigned i;
857
858 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT,
859 sizeof(SVGA3dCmdDXDefineElementLayout) +
860 count * sizeof(SVGA3dInputElementDesc), 0);
861 if (!cmd)
862 return PIPE_ERROR_OUT_OF_MEMORY;
863
864 /* check that all offsets are multiples of four */
865 for (i = 0; i < count; i++) {
866 assert(elements[i].alignedByteOffset % 4 == 0);
867 }
868 (void) i; /* silence unused var in release build */
869
870 cmd->elementLayoutId = elementLayoutId;
871 memcpy(cmd + 1, elements, count * sizeof(SVGA3dInputElementDesc));
872
873 swc->commit(swc);
874 return PIPE_OK;
875 }
876
877 enum pipe_error
SVGA3D_vgpu10_DestroyElementLayout(struct svga_winsys_context * swc,SVGA3dElementLayoutId elementLayoutId)878 SVGA3D_vgpu10_DestroyElementLayout(struct svga_winsys_context *swc,
879 SVGA3dElementLayoutId elementLayoutId)
880 {
881 SVGA3D_CREATE_COMMAND(DestroyElementLayout, DESTROY_ELEMENTLAYOUT);
882
883 cmd->elementLayoutId = elementLayoutId;
884
885 swc->commit(swc);
886 return PIPE_OK;
887 }
888
889 enum pipe_error
SVGA3D_vgpu10_DefineBlendState(struct svga_winsys_context * swc,SVGA3dBlendStateId blendId,uint8 alphaToCoverageEnable,uint8 independentBlendEnable,const SVGA3dDXBlendStatePerRT * perRT)890 SVGA3D_vgpu10_DefineBlendState(struct svga_winsys_context *swc,
891 SVGA3dBlendStateId blendId,
892 uint8 alphaToCoverageEnable,
893 uint8 independentBlendEnable,
894 const SVGA3dDXBlendStatePerRT *perRT)
895 {
896 int i;
897
898 SVGA3D_CREATE_COMMAND(DefineBlendState, DEFINE_BLEND_STATE);
899
900 for (i = 0; i < SVGA3D_MAX_RENDER_TARGETS; i++) {
901 /* At most, one of blend or logicop can be enabled */
902 assert(perRT[i].blendEnable == 0 || perRT[i].logicOpEnable == 0);
903 }
904
905 cmd->blendId = blendId;
906 cmd->alphaToCoverageEnable = alphaToCoverageEnable;
907 cmd->independentBlendEnable = independentBlendEnable;
908 memcpy(cmd->perRT, perRT, sizeof(cmd->perRT));
909 cmd->pad0 = 0;
910
911 swc->commit(swc);
912 return PIPE_OK;
913 }
914
915 enum pipe_error
SVGA3D_vgpu10_DestroyBlendState(struct svga_winsys_context * swc,SVGA3dBlendStateId blendId)916 SVGA3D_vgpu10_DestroyBlendState(struct svga_winsys_context *swc,
917 SVGA3dBlendStateId blendId)
918 {
919 SVGA3D_CREATE_COMMAND(DestroyBlendState, DESTROY_BLEND_STATE);
920
921 cmd->blendId = blendId;
922
923 swc->commit(swc);
924 return PIPE_OK;
925 }
926
927 enum pipe_error
SVGA3D_vgpu10_DefineDepthStencilState(struct svga_winsys_context * swc,SVGA3dDepthStencilStateId depthStencilId,uint8 depthEnable,SVGA3dDepthWriteMask depthWriteMask,SVGA3dComparisonFunc depthFunc,uint8 stencilEnable,uint8 frontEnable,uint8 backEnable,uint8 stencilReadMask,uint8 stencilWriteMask,uint8 frontStencilFailOp,uint8 frontStencilDepthFailOp,uint8 frontStencilPassOp,SVGA3dComparisonFunc frontStencilFunc,uint8 backStencilFailOp,uint8 backStencilDepthFailOp,uint8 backStencilPassOp,SVGA3dComparisonFunc backStencilFunc)928 SVGA3D_vgpu10_DefineDepthStencilState(struct svga_winsys_context *swc,
929 SVGA3dDepthStencilStateId depthStencilId,
930 uint8 depthEnable,
931 SVGA3dDepthWriteMask depthWriteMask,
932 SVGA3dComparisonFunc depthFunc,
933 uint8 stencilEnable,
934 uint8 frontEnable,
935 uint8 backEnable,
936 uint8 stencilReadMask,
937 uint8 stencilWriteMask,
938 uint8 frontStencilFailOp,
939 uint8 frontStencilDepthFailOp,
940 uint8 frontStencilPassOp,
941 SVGA3dComparisonFunc frontStencilFunc,
942 uint8 backStencilFailOp,
943 uint8 backStencilDepthFailOp,
944 uint8 backStencilPassOp,
945 SVGA3dComparisonFunc backStencilFunc)
946 {
947 SVGA3D_CREATE_COMMAND(DefineDepthStencilState, DEFINE_DEPTHSTENCIL_STATE);
948
949 SVGA3D_COPY_BASIC_9(depthStencilId, depthEnable,
950 depthWriteMask, depthFunc,
951 stencilEnable, frontEnable,
952 backEnable, stencilReadMask,
953 stencilWriteMask);
954 SVGA3D_COPY_BASIC_8(frontStencilFailOp, frontStencilDepthFailOp,
955 frontStencilPassOp, frontStencilFunc,
956 backStencilFailOp, backStencilDepthFailOp,
957 backStencilPassOp, backStencilFunc);
958
959 swc->commit(swc);
960 return PIPE_OK;
961 }
962
963 enum pipe_error
SVGA3D_vgpu10_DestroyDepthStencilState(struct svga_winsys_context * swc,SVGA3dDepthStencilStateId depthStencilId)964 SVGA3D_vgpu10_DestroyDepthStencilState(struct svga_winsys_context *swc,
965 SVGA3dDepthStencilStateId depthStencilId)
966 {
967 SVGA3D_CREATE_COMMAND(DestroyDepthStencilState,
968 DESTROY_DEPTHSTENCIL_STATE);
969
970 cmd->depthStencilId = depthStencilId;
971
972 swc->commit(swc);
973 return PIPE_OK;
974 }
975
976 enum pipe_error
SVGA3D_vgpu10_DefineRasterizerState(struct svga_winsys_context * swc,SVGA3dRasterizerStateId rasterizerId,uint8 fillMode,SVGA3dCullMode cullMode,uint8 frontCounterClockwise,int32 depthBias,float depthBiasClamp,float slopeScaledDepthBias,uint8 depthClipEnable,uint8 scissorEnable,uint8 multisampleEnable,uint8 antialiasedLineEnable,float lineWidth,uint8 lineStippleEnable,uint8 lineStippleFactor,uint16 lineStipplePattern,uint8 provokingVertexLast)977 SVGA3D_vgpu10_DefineRasterizerState(struct svga_winsys_context *swc,
978 SVGA3dRasterizerStateId rasterizerId,
979 uint8 fillMode,
980 SVGA3dCullMode cullMode,
981 uint8 frontCounterClockwise,
982 int32 depthBias,
983 float depthBiasClamp,
984 float slopeScaledDepthBias,
985 uint8 depthClipEnable,
986 uint8 scissorEnable,
987 uint8 multisampleEnable,
988 uint8 antialiasedLineEnable,
989 float lineWidth,
990 uint8 lineStippleEnable,
991 uint8 lineStippleFactor,
992 uint16 lineStipplePattern,
993 uint8 provokingVertexLast)
994 {
995 SVGA3D_CREATE_COMMAND(DefineRasterizerState, DEFINE_RASTERIZER_STATE);
996
997 SVGA3D_COPY_BASIC_5(rasterizerId, fillMode,
998 cullMode, frontCounterClockwise,
999 depthBias);
1000 SVGA3D_COPY_BASIC_6(depthBiasClamp, slopeScaledDepthBias,
1001 depthClipEnable, scissorEnable,
1002 multisampleEnable, antialiasedLineEnable);
1003 cmd->lineWidth = lineWidth;
1004 cmd->lineStippleEnable = lineStippleEnable;
1005 cmd->lineStippleFactor = lineStippleFactor;
1006 cmd->lineStipplePattern = lineStipplePattern;
1007 cmd->provokingVertexLast = provokingVertexLast;
1008
1009 swc->commit(swc);
1010 return PIPE_OK;
1011 }
1012
1013 enum pipe_error
SVGA3D_vgpu10_DestroyRasterizerState(struct svga_winsys_context * swc,SVGA3dRasterizerStateId rasterizerId)1014 SVGA3D_vgpu10_DestroyRasterizerState(struct svga_winsys_context *swc,
1015 SVGA3dRasterizerStateId rasterizerId)
1016 {
1017 SVGA3D_CREATE_COMMAND(DestroyRasterizerState, DESTROY_RASTERIZER_STATE);
1018
1019 cmd->rasterizerId = rasterizerId;
1020
1021 swc->commit(swc);
1022 return PIPE_OK;
1023 }
1024
1025 enum pipe_error
SVGA3D_vgpu10_DefineSamplerState(struct svga_winsys_context * swc,SVGA3dSamplerId samplerId,SVGA3dFilter filter,uint8 addressU,uint8 addressV,uint8 addressW,float mipLODBias,uint8 maxAnisotropy,uint8 comparisonFunc,SVGA3dRGBAFloat borderColor,float minLOD,float maxLOD)1026 SVGA3D_vgpu10_DefineSamplerState(struct svga_winsys_context *swc,
1027 SVGA3dSamplerId samplerId,
1028 SVGA3dFilter filter,
1029 uint8 addressU,
1030 uint8 addressV,
1031 uint8 addressW,
1032 float mipLODBias,
1033 uint8 maxAnisotropy,
1034 uint8 comparisonFunc,
1035 SVGA3dRGBAFloat borderColor,
1036 float minLOD,
1037 float maxLOD)
1038 {
1039 SVGA3D_CREATE_COMMAND(DefineSamplerState, DEFINE_SAMPLER_STATE);
1040
1041 SVGA3D_COPY_BASIC_6(samplerId, filter,
1042 addressU, addressV,
1043 addressW, mipLODBias);
1044 SVGA3D_COPY_BASIC_5(maxAnisotropy, comparisonFunc,
1045 borderColor, minLOD,
1046 maxLOD);
1047 cmd->pad0 = 0;
1048 cmd->pad1 = 0;
1049
1050 swc->commit(swc);
1051 return PIPE_OK;
1052 }
1053
1054 enum pipe_error
SVGA3D_vgpu10_DestroySamplerState(struct svga_winsys_context * swc,SVGA3dSamplerId samplerId)1055 SVGA3D_vgpu10_DestroySamplerState(struct svga_winsys_context *swc,
1056 SVGA3dSamplerId samplerId)
1057 {
1058 SVGA3D_CREATE_COMMAND(DestroySamplerState, DESTROY_SAMPLER_STATE);
1059
1060 cmd->samplerId = samplerId;
1061
1062 swc->commit(swc);
1063 return PIPE_OK;
1064 }
1065
1066
1067 enum pipe_error
SVGA3D_vgpu10_DefineAndBindShader(struct svga_winsys_context * swc,struct svga_winsys_gb_shader * gbshader,SVGA3dShaderId shaderId,SVGA3dShaderType type,uint32 sizeInBytes)1068 SVGA3D_vgpu10_DefineAndBindShader(struct svga_winsys_context *swc,
1069 struct svga_winsys_gb_shader *gbshader,
1070 SVGA3dShaderId shaderId,
1071 SVGA3dShaderType type,
1072 uint32 sizeInBytes)
1073 {
1074 SVGA3dCmdHeader *header;
1075 SVGA3dCmdDXDefineShader *dcmd;
1076 SVGA3dCmdDXBindShader *bcmd;
1077 unsigned totalSize = 2 * sizeof(*header) +
1078 sizeof(*dcmd) + sizeof(*bcmd);
1079
1080 /* Make sure there is room for both commands */
1081 header = swc->reserve(swc, totalSize, 2);
1082 if (!header)
1083 return PIPE_ERROR_OUT_OF_MEMORY;
1084
1085 /* DXDefineShader command */
1086 header->id = SVGA_3D_CMD_DX_DEFINE_SHADER;
1087 header->size = sizeof(*dcmd);
1088 dcmd = (SVGA3dCmdDXDefineShader *)(header + 1);
1089 dcmd->shaderId = shaderId;
1090 dcmd->type = type;
1091 dcmd->sizeInBytes = sizeInBytes;
1092
1093 /* DXBindShader command */
1094 header = (SVGA3dCmdHeader *)(dcmd + 1);
1095
1096 header->id = SVGA_3D_CMD_DX_BIND_SHADER;
1097 header->size = sizeof(*bcmd);
1098 bcmd = (SVGA3dCmdDXBindShader *)(header + 1);
1099
1100 bcmd->cid = swc->cid;
1101 swc->shader_relocation(swc, NULL, &bcmd->mobid,
1102 &bcmd->offsetInBytes, gbshader, 0);
1103
1104 bcmd->shid = shaderId;
1105
1106 swc->commit(swc);
1107 return PIPE_OK;
1108 }
1109
1110 enum pipe_error
SVGA3D_vgpu10_DestroyShader(struct svga_winsys_context * swc,SVGA3dShaderId shaderId)1111 SVGA3D_vgpu10_DestroyShader(struct svga_winsys_context *swc,
1112 SVGA3dShaderId shaderId)
1113 {
1114 SVGA3D_CREATE_COMMAND(DestroyShader, DESTROY_SHADER);
1115
1116 cmd->shaderId = shaderId;
1117
1118 swc->commit(swc);
1119 return PIPE_OK;
1120 }
1121
1122 enum pipe_error
SVGA3D_vgpu10_DefineStreamOutput(struct svga_winsys_context * swc,SVGA3dStreamOutputId soid,uint32 numOutputStreamEntries,uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS],const SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_STREAMOUT_DECLS])1123 SVGA3D_vgpu10_DefineStreamOutput(struct svga_winsys_context *swc,
1124 SVGA3dStreamOutputId soid,
1125 uint32 numOutputStreamEntries,
1126 uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS],
1127 const SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_STREAMOUT_DECLS])
1128 {
1129 unsigned i;
1130 SVGA3D_CREATE_COMMAND(DefineStreamOutput, DEFINE_STREAMOUTPUT);
1131
1132 cmd->soid = soid;
1133 cmd->numOutputStreamEntries = numOutputStreamEntries;
1134
1135 for (i = 0; i < ARRAY_SIZE(cmd->streamOutputStrideInBytes); i++)
1136 cmd->streamOutputStrideInBytes[i] = streamOutputStrideInBytes[i];
1137
1138 memcpy(cmd->decl, decl,
1139 sizeof(SVGA3dStreamOutputDeclarationEntry)
1140 * SVGA3D_MAX_DX10_STREAMOUT_DECLS);
1141
1142 cmd->rasterizedStream = 0;
1143 swc->commit(swc);
1144 return PIPE_OK;
1145 }
1146
1147 enum pipe_error
SVGA3D_vgpu10_DestroyStreamOutput(struct svga_winsys_context * swc,SVGA3dStreamOutputId soid)1148 SVGA3D_vgpu10_DestroyStreamOutput(struct svga_winsys_context *swc,
1149 SVGA3dStreamOutputId soid)
1150 {
1151 SVGA3D_CREATE_COMMAND(DestroyStreamOutput, DESTROY_STREAMOUTPUT);
1152
1153 cmd->soid = soid;
1154
1155 swc->commit(swc);
1156 return PIPE_OK;
1157 }
1158
1159 enum pipe_error
SVGA3D_vgpu10_SetInputLayout(struct svga_winsys_context * swc,SVGA3dElementLayoutId elementLayoutId)1160 SVGA3D_vgpu10_SetInputLayout(struct svga_winsys_context *swc,
1161 SVGA3dElementLayoutId elementLayoutId)
1162 {
1163 SVGA3D_CREATE_COMMAND(SetInputLayout, SET_INPUT_LAYOUT);
1164
1165 cmd->elementLayoutId = elementLayoutId;
1166
1167 swc->commit(swc);
1168 return PIPE_OK;
1169 }
1170
1171 enum pipe_error
SVGA3D_vgpu10_SetVertexBuffers(struct svga_winsys_context * swc,unsigned count,uint32 startBuffer,const SVGA3dVertexBuffer_v2 * bufferInfo,struct svga_winsys_surface ** surfaces)1172 SVGA3D_vgpu10_SetVertexBuffers(struct svga_winsys_context *swc,
1173 unsigned count,
1174 uint32 startBuffer,
1175 const SVGA3dVertexBuffer_v2 *bufferInfo,
1176 struct svga_winsys_surface **surfaces)
1177 {
1178 SVGA3dCmdDXSetVertexBuffers *cmd;
1179 SVGA3dVertexBuffer *bufs;
1180 unsigned i;
1181
1182 assert(count > 0);
1183
1184 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS,
1185 sizeof(SVGA3dCmdDXSetVertexBuffers) +
1186 count * sizeof(SVGA3dVertexBuffer),
1187 count); /* 'count' relocations */
1188 if (!cmd)
1189 return PIPE_ERROR_OUT_OF_MEMORY;
1190
1191 cmd->startBuffer = startBuffer;
1192
1193 bufs = (SVGA3dVertexBuffer *) &cmd[1];
1194 for (i = 0; i < count; i++) {
1195 bufs[i].stride = bufferInfo[i].stride;
1196 bufs[i].offset = bufferInfo[i].offset;
1197 assert(bufs[i].stride % 4 == 0);
1198 assert(bufs[i].offset % 4 == 0);
1199 swc->surface_relocation(swc, &bufs[i].sid, NULL, surfaces[i],
1200 SVGA_RELOC_READ);
1201 }
1202
1203 swc->commit(swc);
1204 return PIPE_OK;
1205 }
1206
1207 enum pipe_error
SVGA3D_vgpu10_SetVertexBuffersOffsetAndSize(struct svga_winsys_context * swc,unsigned count,uint32 startBuffer,const SVGA3dVertexBuffer_v2 * bufferInfo)1208 SVGA3D_vgpu10_SetVertexBuffersOffsetAndSize(struct svga_winsys_context *swc,
1209 unsigned count,
1210 uint32 startBuffer,
1211 const SVGA3dVertexBuffer_v2 *bufferInfo)
1212 {
1213 SVGA3dCmdDXSetVertexBuffersOffsetAndSize *cmd;
1214 SVGA3dVertexBufferOffsetAndSize *bufs;
1215 unsigned i;
1216
1217 assert(count > 0);
1218
1219 cmd = SVGA3D_FIFOReserve(swc,
1220 SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS_OFFSET_AND_SIZE,
1221 sizeof(SVGA3dCmdDXSetVertexBuffersOffsetAndSize) +
1222 count * sizeof(SVGA3dVertexBufferOffsetAndSize),
1223 0); /* no relocation */
1224 if (!cmd)
1225 return PIPE_ERROR_OUT_OF_MEMORY;
1226
1227 cmd->startBuffer = startBuffer;
1228
1229 bufs = (SVGA3dVertexBufferOffsetAndSize *) &cmd[1];
1230 for (i = 0; i < count; i++) {
1231 bufs[i].stride = bufferInfo[i].stride;
1232 bufs[i].offset = bufferInfo[i].offset;
1233 bufs[i].sizeInBytes = bufferInfo[i].sizeInBytes;
1234 assert(bufs[i].stride % 4 == 0);
1235 assert(bufs[i].offset % 4 == 0);
1236 }
1237
1238 swc->commit(swc);
1239 return PIPE_OK;
1240 }
1241
1242 enum pipe_error
SVGA3D_vgpu10_SetTopology(struct svga_winsys_context * swc,SVGA3dPrimitiveType topology)1243 SVGA3D_vgpu10_SetTopology(struct svga_winsys_context *swc,
1244 SVGA3dPrimitiveType topology)
1245 {
1246 SVGA3D_CREATE_COMMAND(SetTopology, SET_TOPOLOGY);
1247
1248 cmd->topology = topology;
1249
1250 swc->commit(swc);
1251 return PIPE_OK;
1252 }
1253
1254 enum pipe_error
SVGA3D_vgpu10_SetIndexBuffer(struct svga_winsys_context * swc,struct svga_winsys_surface * indexes,SVGA3dSurfaceFormat format,uint32 offset)1255 SVGA3D_vgpu10_SetIndexBuffer(struct svga_winsys_context *swc,
1256 struct svga_winsys_surface *indexes,
1257 SVGA3dSurfaceFormat format,
1258 uint32 offset)
1259 {
1260 SVGA3dCmdDXSetIndexBuffer *cmd;
1261
1262 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_SET_INDEX_BUFFER,
1263 sizeof(SVGA3dCmdDXSetIndexBuffer),
1264 1); /* one relocations */
1265 if (!cmd)
1266 return PIPE_ERROR_OUT_OF_MEMORY;
1267
1268 swc->surface_relocation(swc, &cmd->sid, NULL, indexes, SVGA_RELOC_READ);
1269 SVGA3D_COPY_BASIC_2(format, offset);
1270
1271 swc->commit(swc);
1272 return PIPE_OK;
1273 }
1274
1275 enum pipe_error
SVGA3D_vgpu10_SetIndexBuffer_v2(struct svga_winsys_context * swc,struct svga_winsys_surface * indexes,SVGA3dSurfaceFormat format,uint32 offset,uint32 sizeInBytes)1276 SVGA3D_vgpu10_SetIndexBuffer_v2(struct svga_winsys_context *swc,
1277 struct svga_winsys_surface *indexes,
1278 SVGA3dSurfaceFormat format,
1279 uint32 offset,
1280 uint32 sizeInBytes)
1281 {
1282 SVGA3dCmdDXSetIndexBuffer_v2 *cmd;
1283
1284 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_SET_INDEX_BUFFER_V2,
1285 sizeof(SVGA3dCmdDXSetIndexBuffer),
1286 1); /* one relocations */
1287 if (!cmd)
1288 return PIPE_ERROR_OUT_OF_MEMORY;
1289
1290 swc->surface_relocation(swc, &cmd->sid, NULL, indexes, SVGA_RELOC_READ);
1291 SVGA3D_COPY_BASIC_3(format, offset, sizeInBytes);
1292
1293 swc->commit(swc);
1294 return PIPE_OK;
1295 }
1296
1297 enum pipe_error
SVGA3D_vgpu10_SetIndexBufferOffsetAndSize(struct svga_winsys_context * swc,SVGA3dSurfaceFormat format,uint32 offset,uint32 sizeInBytes)1298 SVGA3D_vgpu10_SetIndexBufferOffsetAndSize(struct svga_winsys_context *swc,
1299 SVGA3dSurfaceFormat format,
1300 uint32 offset,
1301 uint32 sizeInBytes)
1302 {
1303 SVGA3dCmdDXSetIndexBufferOffsetAndSize *cmd;
1304
1305 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_SET_INDEX_BUFFER_OFFSET_AND_SIZE,
1306 sizeof(SVGA3dCmdDXSetIndexBufferOffsetAndSize),
1307 0); /* one relocations */
1308 if (!cmd)
1309 return PIPE_ERROR_OUT_OF_MEMORY;
1310
1311 SVGA3D_COPY_BASIC_3(format, offset, sizeInBytes);
1312
1313 swc->commit(swc);
1314 return PIPE_OK;
1315 }
1316
1317 enum pipe_error
SVGA3D_vgpu10_SetSingleConstantBuffer(struct svga_winsys_context * swc,unsigned slot,SVGA3dShaderType type,struct svga_winsys_surface * surface,uint32 offsetInBytes,uint32 sizeInBytes)1318 SVGA3D_vgpu10_SetSingleConstantBuffer(struct svga_winsys_context *swc,
1319 unsigned slot,
1320 SVGA3dShaderType type,
1321 struct svga_winsys_surface *surface,
1322 uint32 offsetInBytes,
1323 uint32 sizeInBytes)
1324 {
1325 SVGA3dCmdDXSetSingleConstantBuffer *cmd;
1326
1327 assert(offsetInBytes % 256 == 0);
1328 if (!surface)
1329 assert(sizeInBytes == 0);
1330 else
1331 assert(sizeInBytes > 0);
1332
1333 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER,
1334 sizeof(SVGA3dCmdDXSetSingleConstantBuffer),
1335 1); /* one relocation */
1336 if (!cmd)
1337 return PIPE_ERROR_OUT_OF_MEMORY;
1338
1339 cmd->slot = slot;
1340 cmd->type = type;
1341 swc->surface_relocation(swc, &cmd->sid, NULL, surface, SVGA_RELOC_READ);
1342 cmd->offsetInBytes = offsetInBytes;
1343 cmd->sizeInBytes = sizeInBytes;
1344
1345 swc->commit(swc);
1346
1347 return PIPE_OK;
1348 }
1349
1350
1351 enum pipe_error
SVGA3D_vgpu10_SetConstantBufferOffset(struct svga_winsys_context * swc,unsigned command,unsigned slot,uint32 offsetInBytes)1352 SVGA3D_vgpu10_SetConstantBufferOffset(struct svga_winsys_context *swc,
1353 unsigned command,
1354 unsigned slot,
1355 uint32 offsetInBytes)
1356 {
1357 SVGA3dCmdDXSetConstantBufferOffset *cmd;
1358
1359 assert(offsetInBytes % 256 == 0);
1360
1361 cmd = SVGA3D_FIFOReserve(swc, command,
1362 sizeof(SVGA3dCmdDXSetConstantBufferOffset),
1363 0); /* one relocation */
1364 if (!cmd)
1365 return PIPE_ERROR_OUT_OF_MEMORY;
1366
1367 cmd->slot = slot;
1368 cmd->offsetInBytes = offsetInBytes;
1369
1370 swc->commit(swc);
1371
1372 return PIPE_OK;
1373 }
1374
1375
1376 enum pipe_error
SVGA3D_vgpu10_ReadbackSubResource(struct svga_winsys_context * swc,struct svga_winsys_surface * surface,unsigned subResource)1377 SVGA3D_vgpu10_ReadbackSubResource(struct svga_winsys_context *swc,
1378 struct svga_winsys_surface *surface,
1379 unsigned subResource)
1380 {
1381 SVGA3dCmdDXReadbackSubResource *cmd;
1382
1383 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_READBACK_SUBRESOURCE,
1384 sizeof(SVGA3dCmdDXReadbackSubResource),
1385 1);
1386 if (!cmd)
1387 return PIPE_ERROR_OUT_OF_MEMORY;
1388
1389 swc->surface_relocation(swc, &cmd->sid, NULL, surface,
1390 SVGA_RELOC_READ | SVGA_RELOC_INTERNAL);
1391 cmd->subResource = subResource;
1392
1393 swc->commit(swc);
1394 return PIPE_OK;
1395 }
1396
1397 enum pipe_error
SVGA3D_vgpu10_UpdateSubResource(struct svga_winsys_context * swc,struct svga_winsys_surface * surface,const SVGA3dBox * box,unsigned subResource)1398 SVGA3D_vgpu10_UpdateSubResource(struct svga_winsys_context *swc,
1399 struct svga_winsys_surface *surface,
1400 const SVGA3dBox *box,
1401 unsigned subResource)
1402 {
1403 SVGA3dCmdDXUpdateSubResource *cmd;
1404
1405 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE,
1406 sizeof(SVGA3dCmdDXUpdateSubResource),
1407 1);
1408 if (!cmd)
1409 return PIPE_ERROR_OUT_OF_MEMORY;
1410
1411 swc->surface_relocation(swc, &cmd->sid, NULL, surface,
1412 SVGA_RELOC_WRITE | SVGA_RELOC_INTERNAL);
1413 cmd->subResource = subResource;
1414 cmd->box = *box;
1415
1416 swc->commit(swc);
1417 return PIPE_OK;
1418 }
1419
1420 enum pipe_error
SVGA3D_vgpu10_GenMips(struct svga_winsys_context * swc,SVGA3dShaderResourceViewId shaderResourceViewId,struct svga_winsys_surface * view)1421 SVGA3D_vgpu10_GenMips(struct svga_winsys_context *swc,
1422 SVGA3dShaderResourceViewId shaderResourceViewId,
1423 struct svga_winsys_surface *view)
1424 {
1425 SVGA3dCmdDXGenMips *cmd;
1426
1427 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_GENMIPS,
1428 sizeof(SVGA3dCmdDXGenMips), 1);
1429
1430 if (!cmd)
1431 return PIPE_ERROR_OUT_OF_MEMORY;
1432
1433 swc->surface_relocation(swc, &cmd->shaderResourceViewId, NULL, view,
1434 SVGA_RELOC_WRITE);
1435 cmd->shaderResourceViewId = shaderResourceViewId;
1436
1437 swc->commit(swc);
1438 return PIPE_OK;
1439 }
1440
1441
1442 enum pipe_error
SVGA3D_vgpu10_BufferCopy(struct svga_winsys_context * swc,struct svga_winsys_surface * src,struct svga_winsys_surface * dst,unsigned srcx,unsigned dstx,unsigned width)1443 SVGA3D_vgpu10_BufferCopy(struct svga_winsys_context *swc,
1444 struct svga_winsys_surface *src,
1445 struct svga_winsys_surface *dst,
1446 unsigned srcx, unsigned dstx, unsigned width)
1447 {
1448 SVGA3dCmdDXBufferCopy *cmd;
1449
1450 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_BUFFER_COPY, sizeof *cmd, 2);
1451
1452 if (!cmd)
1453 return PIPE_ERROR_OUT_OF_MEMORY;
1454
1455 swc->surface_relocation(swc, &cmd->dest, NULL, dst, SVGA_RELOC_WRITE);
1456 swc->surface_relocation(swc, &cmd->src, NULL, src, SVGA_RELOC_READ);
1457 cmd->destX = dstx;
1458 cmd->srcX = srcx;
1459 cmd->width = width;
1460
1461 swc->commit(swc);
1462 return PIPE_OK;
1463 }
1464
1465 enum pipe_error
SVGA3D_vgpu10_TransferFromBuffer(struct svga_winsys_context * swc,struct svga_winsys_surface * src,unsigned srcOffset,unsigned srcPitch,unsigned srcSlicePitch,struct svga_winsys_surface * dst,unsigned dstSubResource,SVGA3dBox * dstBox)1466 SVGA3D_vgpu10_TransferFromBuffer(struct svga_winsys_context *swc,
1467 struct svga_winsys_surface *src,
1468 unsigned srcOffset, unsigned srcPitch,
1469 unsigned srcSlicePitch,
1470 struct svga_winsys_surface *dst,
1471 unsigned dstSubResource,
1472 SVGA3dBox *dstBox)
1473 {
1474 SVGA3dCmdDXTransferFromBuffer *cmd;
1475
1476 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER,
1477 sizeof(SVGA3dCmdDXTransferFromBuffer), 2);
1478
1479 if (!cmd)
1480 return PIPE_ERROR_OUT_OF_MEMORY;
1481
1482 swc->surface_relocation(swc, &cmd->srcSid, NULL, src, SVGA_RELOC_READ);
1483 swc->surface_relocation(swc, &cmd->destSid, NULL, dst, SVGA_RELOC_WRITE);
1484 cmd->srcOffset = srcOffset;
1485 cmd->srcPitch = srcPitch;
1486 cmd->srcSlicePitch = srcSlicePitch;
1487 cmd->destSubResource = dstSubResource;
1488 cmd->destBox = *dstBox;
1489
1490 swc->commit(swc);
1491 return PIPE_OK;
1492 }
1493
1494 enum pipe_error
SVGA3D_vgpu10_IntraSurfaceCopy(struct svga_winsys_context * swc,struct svga_winsys_surface * surface,unsigned level,unsigned face,const SVGA3dCopyBox * box)1495 SVGA3D_vgpu10_IntraSurfaceCopy(struct svga_winsys_context *swc,
1496 struct svga_winsys_surface *surface,
1497 unsigned level, unsigned face,
1498 const SVGA3dCopyBox *box)
1499 {
1500 SVGA3dCmdIntraSurfaceCopy *cmd =
1501 SVGA3D_FIFOReserve(swc,
1502 SVGA_3D_CMD_INTRA_SURFACE_COPY,
1503 sizeof(SVGA3dCmdIntraSurfaceCopy),
1504 1); /* one relocation */
1505 if (!cmd)
1506 return PIPE_ERROR_OUT_OF_MEMORY;
1507
1508 swc->surface_relocation(swc, &cmd->surface.sid, NULL, surface, SVGA_RELOC_READ | SVGA_RELOC_WRITE);
1509 cmd->surface.face = face;
1510 cmd->surface.mipmap = level;
1511 cmd->box = *box;
1512
1513 swc->commit(swc);
1514
1515 return PIPE_OK;
1516 }
1517
1518 enum pipe_error
SVGA3D_vgpu10_ResolveCopy(struct svga_winsys_context * swc,unsigned dstSubResource,struct svga_winsys_surface * dst,unsigned srcSubResource,struct svga_winsys_surface * src,const SVGA3dSurfaceFormat copyFormat)1519 SVGA3D_vgpu10_ResolveCopy(struct svga_winsys_context *swc,
1520 unsigned dstSubResource,
1521 struct svga_winsys_surface *dst,
1522 unsigned srcSubResource,
1523 struct svga_winsys_surface *src,
1524 const SVGA3dSurfaceFormat copyFormat)
1525 {
1526 SVGA3dCmdDXResolveCopy *cmd =
1527 SVGA3D_FIFOReserve(swc,
1528 SVGA_3D_CMD_DX_RESOLVE_COPY,
1529 sizeof(SVGA3dCmdDXResolveCopy),
1530 2); /* two relocations */
1531 if (!cmd)
1532 return PIPE_ERROR_OUT_OF_MEMORY;
1533
1534 cmd->dstSubResource = dstSubResource;
1535 swc->surface_relocation(swc, &cmd->dstSid, NULL, dst, SVGA_RELOC_WRITE);
1536 cmd->srcSubResource = srcSubResource;
1537 swc->surface_relocation(swc, &cmd->srcSid, NULL, src, SVGA_RELOC_READ);
1538 cmd->copyFormat = copyFormat;
1539
1540 swc->commit(swc);
1541
1542 return PIPE_OK;
1543 }
1544
1545
1546 enum pipe_error
SVGA3D_sm5_DrawIndexedInstancedIndirect(struct svga_winsys_context * swc,struct svga_winsys_surface * argBuffer,unsigned argOffset)1547 SVGA3D_sm5_DrawIndexedInstancedIndirect(struct svga_winsys_context *swc,
1548 struct svga_winsys_surface *argBuffer,
1549 unsigned argOffset)
1550 {
1551 SVGA3dCmdDXDrawIndexedInstancedIndirect *cmd =
1552 SVGA3D_FIFOReserve(swc,
1553 SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT,
1554 sizeof(SVGA3dCmdDXDrawIndexedInstancedIndirect),
1555 1); /* one relocation */
1556 if (!cmd)
1557 return PIPE_ERROR_OUT_OF_MEMORY;
1558
1559 swc->surface_relocation(swc, &cmd->argsBufferSid, NULL, argBuffer,
1560 SVGA_RELOC_READ);
1561 cmd->byteOffsetForArgs = argOffset;
1562
1563 swc->commit(swc);
1564
1565 return PIPE_OK;
1566 }
1567
1568
1569 enum pipe_error
SVGA3D_sm5_DrawInstancedIndirect(struct svga_winsys_context * swc,struct svga_winsys_surface * argBuffer,unsigned argOffset)1570 SVGA3D_sm5_DrawInstancedIndirect(struct svga_winsys_context *swc,
1571 struct svga_winsys_surface *argBuffer,
1572 unsigned argOffset)
1573 {
1574 SVGA3dCmdDXDrawInstancedIndirect *cmd =
1575 SVGA3D_FIFOReserve(swc,
1576 SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT,
1577 sizeof(SVGA3dCmdDXDrawInstancedIndirect),
1578 1); /* one relocation */
1579 if (!cmd)
1580 return PIPE_ERROR_OUT_OF_MEMORY;
1581
1582 swc->surface_relocation(swc, &cmd->argsBufferSid, NULL, argBuffer,
1583 SVGA_RELOC_READ);
1584 cmd->byteOffsetForArgs = argOffset;
1585
1586 swc->commit(swc);
1587
1588 return PIPE_OK;
1589 }
1590
1591
1592 enum pipe_error
SVGA3D_sm5_DefineUAView(struct svga_winsys_context * swc,SVGA3dUAViewId uaViewId,struct svga_winsys_surface * surface,SVGA3dSurfaceFormat format,SVGA3dResourceType resourceDimension,const SVGA3dUAViewDesc * desc)1593 SVGA3D_sm5_DefineUAView(struct svga_winsys_context *swc,
1594 SVGA3dUAViewId uaViewId,
1595 struct svga_winsys_surface *surface,
1596 SVGA3dSurfaceFormat format,
1597 SVGA3dResourceType resourceDimension,
1598 const SVGA3dUAViewDesc *desc)
1599 {
1600 SVGA3dCmdDXDefineUAView *cmd;
1601
1602 cmd = SVGA3D_FIFOReserve(swc, SVGA_3D_CMD_DX_DEFINE_UA_VIEW,
1603 sizeof(SVGA3dCmdDXDefineUAView),
1604 1); /* one relocation */
1605 if (!cmd)
1606 return PIPE_ERROR_OUT_OF_MEMORY;
1607
1608 SVGA3D_COPY_BASIC_3(uaViewId, format, resourceDimension);
1609
1610 swc->surface_relocation(swc, &cmd->sid, NULL, surface,
1611 SVGA_RELOC_READ | SVGA_RELOC_WRITE);
1612
1613 cmd->desc = *desc;
1614
1615 swc->commit(swc);
1616 return PIPE_OK;
1617 }
1618
1619
1620 enum pipe_error
SVGA3D_sm5_DestroyUAView(struct svga_winsys_context * swc,SVGA3dUAViewId uaViewId)1621 SVGA3D_sm5_DestroyUAView(struct svga_winsys_context *swc,
1622 SVGA3dUAViewId uaViewId)
1623 {
1624 SVGA3D_CREATE_COMMAND(DestroyUAView, DESTROY_UA_VIEW);
1625 cmd->uaViewId = uaViewId;
1626 swc->commit(swc);
1627 return PIPE_OK;
1628 }
1629
1630
1631 enum pipe_error
SVGA3D_sm5_SetUAViews(struct svga_winsys_context * swc,uint32 uavSpliceIndex,unsigned count,const SVGA3dUAViewId ids[],struct svga_winsys_surface ** uaViews)1632 SVGA3D_sm5_SetUAViews(struct svga_winsys_context *swc,
1633 uint32 uavSpliceIndex,
1634 unsigned count,
1635 const SVGA3dUAViewId ids[],
1636 struct svga_winsys_surface **uaViews)
1637 {
1638 SVGA3dCmdDXSetUAViews *cmd;
1639 SVGA3dUAViewId *cmd_uavIds;
1640 unsigned i;
1641
1642 cmd = SVGA3D_FIFOReserve(swc,
1643 SVGA_3D_CMD_DX_SET_UA_VIEWS,
1644 sizeof(SVGA3dCmdDXSetUAViews) +
1645 count * sizeof(SVGA3dUAViewId),
1646 count); /* 'count' relocations */
1647 if (!cmd)
1648 return PIPE_ERROR_OUT_OF_MEMORY;
1649
1650 cmd->uavSpliceIndex = uavSpliceIndex;
1651 cmd_uavIds = (SVGA3dUAViewId *) (cmd + 1);
1652
1653 for (i = 0; i < count; i++, cmd_uavIds++) {
1654 swc->surface_relocation(swc, cmd_uavIds, NULL,
1655 uaViews[i],
1656 SVGA_RELOC_READ | SVGA_RELOC_WRITE);
1657 *cmd_uavIds = ids[i];
1658 }
1659
1660 swc->commit(swc);
1661 return PIPE_OK;
1662 }
1663
1664
1665 enum pipe_error
SVGA3D_sm5_Dispatch(struct svga_winsys_context * swc,const uint32 threadGroupCount[3])1666 SVGA3D_sm5_Dispatch(struct svga_winsys_context *swc,
1667 const uint32 threadGroupCount[3])
1668 {
1669 SVGA3dCmdDXDispatch *cmd;
1670
1671 cmd = SVGA3D_FIFOReserve(swc,
1672 SVGA_3D_CMD_DX_DISPATCH,
1673 sizeof(SVGA3dCmdDXDispatch),
1674 0);
1675 if (!cmd)
1676 return PIPE_ERROR_OUT_OF_MEMORY;
1677
1678 cmd->threadGroupCountX = threadGroupCount[0];
1679 cmd->threadGroupCountY = threadGroupCount[1];
1680 cmd->threadGroupCountZ = threadGroupCount[2];
1681
1682 swc->commit(swc);
1683 return PIPE_OK;
1684 }
1685
1686
1687 enum pipe_error
SVGA3D_sm5_DispatchIndirect(struct svga_winsys_context * swc,struct svga_winsys_surface * argBuffer,uint32 argOffset)1688 SVGA3D_sm5_DispatchIndirect(struct svga_winsys_context *swc,
1689 struct svga_winsys_surface *argBuffer,
1690 uint32 argOffset)
1691 {
1692 SVGA3dCmdDXDispatchIndirect *cmd;
1693
1694 cmd = SVGA3D_FIFOReserve(swc,
1695 SVGA_3D_CMD_DX_DISPATCH_INDIRECT,
1696 sizeof(SVGA3dCmdDXDispatchIndirect),
1697 1);
1698 if (!cmd)
1699 return PIPE_ERROR_OUT_OF_MEMORY;
1700
1701 swc->surface_relocation(swc, &cmd->argsBufferSid, NULL, argBuffer,
1702 SVGA_RELOC_READ);
1703 cmd->byteOffsetForArgs = argOffset;
1704
1705 swc->commit(swc);
1706 return PIPE_OK;
1707 }
1708
1709
1710 enum pipe_error
SVGA3D_sm5_SetCSUAViews(struct svga_winsys_context * swc,unsigned count,const SVGA3dUAViewId ids[],struct svga_winsys_surface ** uaViews)1711 SVGA3D_sm5_SetCSUAViews(struct svga_winsys_context *swc,
1712 unsigned count,
1713 const SVGA3dUAViewId ids[],
1714 struct svga_winsys_surface **uaViews)
1715 {
1716 SVGA3dCmdDXSetCSUAViews *cmd;
1717 SVGA3dUAViewId *cmd_uavIds;
1718 unsigned i;
1719
1720 cmd = SVGA3D_FIFOReserve(swc,
1721 SVGA_3D_CMD_DX_SET_CS_UA_VIEWS,
1722 sizeof(SVGA3dCmdDXSetCSUAViews) +
1723 count * sizeof(SVGA3dUAViewId),
1724 count); /* 'count' relocations */
1725 if (!cmd)
1726 return PIPE_ERROR_OUT_OF_MEMORY;
1727
1728 cmd->startIndex = 0;
1729 cmd_uavIds = (SVGA3dUAViewId *) (cmd + 1);
1730
1731 for (i = 0; i < count; i++, cmd_uavIds++) {
1732 swc->surface_relocation(swc, cmd_uavIds, NULL,
1733 uaViews[i],
1734 SVGA_RELOC_READ | SVGA_RELOC_WRITE);
1735 *cmd_uavIds = ids[i];
1736 }
1737
1738 swc->commit(swc);
1739 return PIPE_OK;
1740 }
1741
1742 /**
1743 * We don't want any flush between DefineStreamOutputWithMob and
1744 * BindStreamOutput because it will cause partial state in command
1745 * buffer. This function make that sure there is enough room for
1746 * both commands before issuing them
1747 */
1748
1749 enum pipe_error
SVGA3D_sm5_DefineAndBindStreamOutput(struct svga_winsys_context * swc,SVGA3dStreamOutputId soid,uint32 numOutputStreamEntries,uint32 numOutputStreamStrides,uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS],struct svga_winsys_buffer * declBuf,uint32 rasterizedStream,uint32 sizeInBytes)1750 SVGA3D_sm5_DefineAndBindStreamOutput(struct svga_winsys_context *swc,
1751 SVGA3dStreamOutputId soid,
1752 uint32 numOutputStreamEntries,
1753 uint32 numOutputStreamStrides,
1754 uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS],
1755 struct svga_winsys_buffer *declBuf,
1756 uint32 rasterizedStream,
1757 uint32 sizeInBytes)
1758 {
1759 unsigned i;
1760 SVGA3dCmdHeader *header;
1761 SVGA3dCmdDXDefineStreamOutputWithMob *dcmd;
1762 SVGA3dCmdDXBindStreamOutput *bcmd;
1763
1764 unsigned totalSize = 2 * sizeof(*header) +
1765 sizeof(*dcmd) + sizeof(*bcmd);
1766
1767 /* Make sure there is room for both commands */
1768 header = swc->reserve(swc, totalSize, 2);
1769 if (!header)
1770 return PIPE_ERROR_OUT_OF_MEMORY;
1771
1772 /* DXDefineStreamOutputWithMob command */
1773 header->id = SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB;
1774 header->size = sizeof(*dcmd);
1775 dcmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)(header + 1);
1776 dcmd->soid= soid;
1777 dcmd->numOutputStreamEntries = numOutputStreamEntries;
1778 dcmd->numOutputStreamStrides = numOutputStreamStrides;
1779 dcmd->rasterizedStream = rasterizedStream;
1780
1781 for (i = 0; i < ARRAY_SIZE(dcmd->streamOutputStrideInBytes); i++)
1782 dcmd->streamOutputStrideInBytes[i] = streamOutputStrideInBytes[i];
1783
1784
1785 /* DXBindStreamOutput command */
1786 header = (SVGA3dCmdHeader *)(dcmd + 1);
1787
1788 header->id = SVGA_3D_CMD_DX_BIND_STREAMOUTPUT;
1789 header->size = sizeof(*bcmd);
1790 bcmd = (SVGA3dCmdDXBindStreamOutput *)(header + 1);
1791
1792 bcmd->soid = soid;
1793 bcmd->offsetInBytes = 0;
1794 swc->mob_relocation(swc, &bcmd->mobid,
1795 &bcmd->offsetInBytes, declBuf, 0,
1796 SVGA_RELOC_WRITE);
1797
1798 bcmd->sizeInBytes = sizeInBytes;
1799 bcmd->offsetInBytes = 0;
1800
1801
1802 swc->commit(swc);
1803 return PIPE_OK;
1804 }
1805
1806
1807 enum pipe_error
SVGA3D_sm5_DefineRasterizerState_v2(struct svga_winsys_context * swc,SVGA3dRasterizerStateId rasterizerId,uint8 fillMode,SVGA3dCullMode cullMode,uint8 frontCounterClockwise,int32 depthBias,float depthBiasClamp,float slopeScaledDepthBias,uint8 depthClipEnable,uint8 scissorEnable,uint8 multisampleEnable,uint8 antialiasedLineEnable,float lineWidth,uint8 lineStippleEnable,uint8 lineStippleFactor,uint16 lineStipplePattern,uint8 provokingVertexLast,uint32 forcedSampleCount)1808 SVGA3D_sm5_DefineRasterizerState_v2(struct svga_winsys_context *swc,
1809 SVGA3dRasterizerStateId rasterizerId,
1810 uint8 fillMode,
1811 SVGA3dCullMode cullMode,
1812 uint8 frontCounterClockwise,
1813 int32 depthBias,
1814 float depthBiasClamp,
1815 float slopeScaledDepthBias,
1816 uint8 depthClipEnable,
1817 uint8 scissorEnable,
1818 uint8 multisampleEnable,
1819 uint8 antialiasedLineEnable,
1820 float lineWidth,
1821 uint8 lineStippleEnable,
1822 uint8 lineStippleFactor,
1823 uint16 lineStipplePattern,
1824 uint8 provokingVertexLast,
1825 uint32 forcedSampleCount)
1826 {
1827 SVGA3D_CREATE_COMMAND(DefineRasterizerState_v2, DEFINE_RASTERIZER_STATE_V2);
1828
1829 SVGA3D_COPY_BASIC_5(rasterizerId, fillMode,
1830 cullMode, frontCounterClockwise,
1831 depthBias);
1832 SVGA3D_COPY_BASIC_6(depthBiasClamp, slopeScaledDepthBias,
1833 depthClipEnable, scissorEnable,
1834 multisampleEnable, antialiasedLineEnable);
1835 cmd->lineWidth = lineWidth;
1836 cmd->lineStippleEnable = lineStippleEnable;
1837 cmd->lineStippleFactor = lineStippleFactor;
1838 cmd->lineStipplePattern = lineStipplePattern;
1839 cmd->provokingVertexLast = provokingVertexLast;
1840 cmd->forcedSampleCount = forcedSampleCount;
1841
1842 swc->commit(swc);
1843 return PIPE_OK;
1844 }
1845