| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 38 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg() local
50 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex() local
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| /third_party/vixl/examples/aarch32/ |
| D | mandelbrot.cc | 131 __ Subs(r1, r1, 1); in GenerateMandelBrot() local
175 __ Subs(r5, r5, 1); in GenerateMandelBrot() local
188 __ Subs(r4, r4, 1); in GenerateMandelBrot() local
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| D | pi.cc | 73 __ Subs(r0, r0, 1); in GenerateApproximatePi() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/lib/Support/ |
| D | CommandLine.cpp | 1740 SmallVectorImpl<std::pair<const char *, SubCommand *>> &Subs) { in sortSubCommands()
1764 void printSubCommands(StrSubCommandPairVector &Subs, size_t MaxSubLen) { in printSubCommands()
1792 StrSubCommandPairVector Subs; in operator =() local
2085 auto &Subs = GlobalParser->RegisteredSubCommands; in getRegisteredOptions() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/ |
| D | CommandLine.cpp | 2114 SmallVectorImpl<std::pair<const char *, SubCommand *>> &Subs) { in sortSubCommands()
2138 void printSubCommands(StrSubCommandPairVector &Subs, size_t MaxSubLen) { in printSubCommands()
2172 StrSubCommandPairVector Subs; in printHelp() local
2550 auto &Subs = GlobalParser->RegisteredSubCommands; in getRegisteredOptions() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | CommandLine.h | 291 SmallPtrSet<SubCommand *, 1> Subs; // The subcommands this option belongs to. variable
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/include/llvm/Support/ |
| D | CommandLine.h | 260 SmallPtrSet<SubCommand *, 4> Subs; // The subcommands this option belongs to. variable
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ModuloSchedule.cpp | 1596 SmallVector<std::pair<MachineInstr *, Register>, 4> Subs; in filterInstructions() local
1906 SmallVector<std::pair<MachineInstr *, Register>, 4> Subs; in rewriteUsesOf() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | DebugInfo.cpp | 992 auto Subs = unwrap(Builder)->getOrCreateArray({unwrap(Subscripts), in LLVMDIBuilderCreateArrayType() local
1003 auto Subs = unwrap(Builder)->getOrCreateArray({unwrap(Subscripts), in LLVMDIBuilderCreateVectorType() local
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| D | code-generator-arm64.cc | 1402 __ Subs(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local
1411 __ Subs(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Instrumentation/ |
| D | ControlHeightReduction.cpp | 293 SmallVector<CHRScope *, 8> Subs; // Subscopes. member in __anon24a1d1030211::CHRScope
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | macro-assembler-arm64-inl.h | 147 void TurboAssembler::Subs(const Register& rd, const Register& rn, in Subs() function
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| /third_party/node/deps/v8/src/regexp/arm64/ |
| D | regexp-macro-assembler-arm64.cc | 864 __ Subs(x10, sp, x10); in GetCode() local
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| /third_party/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 1523 void MacroAssembler::Subs(const Register& rd, in Emit() function in vixl::aarch64::MacroAssembler
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| /third_party/node/deps/v8/src/builtins/arm64/ |
| D | builtins-arm64.cc | 2537 __ Subs(len, len, kJSArgcReceiverSlots); in Generate_CallOrConstructForwardVarargs() local
2538 __ Subs(len, len, start_index); in Generate_CallOrConstructForwardVarargs() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Demangle/ |
| D | ItaniumDemangle.h | 2302 PODSmallVector<Node *, 32> Subs; member
|
| /third_party/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 3306 __ Subs(r0, r0, 0); in TEST() local
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| /third_party/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 70 __ Subs(x7, x0, 0x18001); in TEST() local
71 __ Subs(w8, w0, 0xffffff1); in TEST() local
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| /third_party/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 5575 void Subs(Condition cond, Register rd, Register rn, const Operand& operand) { in Assembler() function
5589 void Subs(Register rd, Register rn, const Operand& operand) { in Assembler() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5796 SmallVector<SDValue, 4> Subs; in SplitOpsAndApply() local
|