1 2 //===------------ MIRVRegNamerUtils.h - MIR VReg Renaming Utilities -------===// 3 // 4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 5 // See https://llvm.org/LICENSE.txt for license information. 6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // The purpose of these utilities is to abstract out parts of the MIRCanon pass 11 // that are responsible for renaming virtual registers with the purpose of 12 // sharing code with a MIRVRegNamer pass that could be the analog of the 13 // opt -instnamer pass. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_LIB_CODEGEN_MIRVREGNAMERUTILS_H 18 #define LLVM_LIB_CODEGEN_MIRVREGNAMERUTILS_H 19 20 #include "llvm/ADT/PostOrderIterator.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/CodeGen/MachineFunctionPass.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/Passes.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 namespace llvm { 29 /// VRegRenamer - This class is used for renaming vregs in a machine basic 30 /// block according to semantics of the instruction. 31 class VRegRenamer { 32 class NamedVReg { 33 Register Reg; 34 std::string Name; 35 36 public: Reg(Reg)37 NamedVReg(Register Reg, std::string Name = "") : Reg(Reg), Name(Name) {} 38 NamedVReg(std::string Name = "") : Reg(~0U), Name(Name) {} 39 getName()40 const std::string &getName() const { return Name; } 41 getReg()42 Register getReg() const { return Reg; } 43 }; 44 45 MachineRegisterInfo &MRI; 46 47 unsigned CurrentBBNumber = 0; 48 49 /// Given an Instruction, construct a hash of the operands 50 /// of the instructions along with the opcode. 51 /// When dealing with virtual registers, just hash the opcode of 52 /// the instruction defining that vreg. 53 /// Handle immediates, registers (physical and virtual) explicitly, 54 /// and return a common value for the other cases. 55 /// Instruction will be named in the following scheme 56 /// bb<block_no>_hash_<collission_count>. 57 std::string getInstructionOpcodeHash(MachineInstr &MI); 58 59 /// For all the VRegs that are candidates for renaming, 60 /// return a mapping from old vregs to new vregs with names. 61 std::map<unsigned, unsigned> 62 getVRegRenameMap(const std::vector<NamedVReg> &VRegs); 63 64 /// Perform replacing of registers based on the <old,new> vreg map. 65 bool doVRegRenaming(const std::map<unsigned, unsigned> &VRegRenameMap); 66 67 /// createVirtualRegister - Given an existing vreg, create a named vreg to 68 /// take its place. The name is determined by calling 69 /// getInstructionOpcodeHash. 70 unsigned createVirtualRegister(unsigned VReg); 71 72 /// Create a vreg with name and return it. 73 unsigned createVirtualRegisterWithLowerName(unsigned VReg, StringRef Name); 74 /// Linearly traverse the MachineBasicBlock and rename each instruction's 75 /// vreg definition based on the semantics of the instruction. 76 /// Names are as follows bb<BBNum>_hash_[0-9]+ 77 bool renameInstsInMBB(MachineBasicBlock *MBB); 78 79 public: 80 VRegRenamer() = delete; VRegRenamer(MachineRegisterInfo & MRI)81 VRegRenamer(MachineRegisterInfo &MRI) : MRI(MRI) {} 82 83 /// Same as the above, but sets a BBNum depending on BB traversal that 84 /// will be used as prefix for the vreg names. renameVRegs(MachineBasicBlock * MBB,unsigned BBNum)85 bool renameVRegs(MachineBasicBlock *MBB, unsigned BBNum) { 86 CurrentBBNumber = BBNum; 87 return renameInstsInMBB(MBB); 88 } 89 }; 90 91 } // namespace llvm 92 93 #endif 94