| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/ |
| D | aarch64_obj_emitter.cpp | 1244 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadStoreRegInsn() local
1296 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadStoreARInsn() local
1310 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadExclusiveInsn() local
1326 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadExclusivePairInsn() local
1342 Operand *baseReg = memOpnd.GetBaseRegister(); in GenStoreExclusiveInsn() local
1360 Operand *baseReg = memOpnd.GetBaseRegister(); in GenStoreExclusivePairInsn() local
1376 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadPairInsn() local
1413 Operand *baseReg = memOpnd.GetBaseRegister(); in GenStorePairInsn() local
1455 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadPairFloatInsn() local
1492 Operand *baseReg = memOpnd.GetBaseRegister(); in GenStorePairFloatInsn() local
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| D | aarch64_insn.cpp | 127 auto *baseReg = v->GetBaseRegister(); in Visit() local
189 auto *baseReg = v->GetBaseRegister(); in Visit() local
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| D | aarch64_dependence.cpp | 676 RegOperand *baseReg = memOpnd->GetBaseRegister(); in BuildStackPassArgsDeps() local
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| D | aarch64_global.cpp | 1186 RegOperand *baseReg = secondInsnDestMem->GetBaseRegister(); in CheckSecondInsn() local
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| D | aarch64_cgfunc.cpp | 871 MemOperand &AArch64CGFunc::CreateReplacementMemOperand(uint32 bitLen, RegOperand &baseReg, int64 of… in CreateReplacementMemOperand()
922 RegOperand *baseReg = memOpnd.GetBaseRegister(); in ConstraintOffsetToSafeRegion() local
1163 RegOperand &baseReg = LoadIntoRegister(*opnd0, PTY_a64); in SelectAssertNull() local
9748 auto *baseReg = SelectRegread(*static_cast<RegreadNode *>(baseExpr)); in CheckAndCreateExtendMemOpnd() local
10327 RegOperand *baseReg = memOpnd->GetBaseRegister(); in ConvertAdrpl12LdrToLdr() local
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| /arkcompiler/ets_frontend/es2panda/ir/base/ |
| D | classDefinition.cpp | 111 compiler::VReg baseReg = pg->AllocReg(); in CompileHeritageClause() local
393 compiler::VReg baseReg = CompileHeritageClause(pg); in Compile() local
590 compiler::VReg baseReg = CompileHeritageClause(pg); in CompileSendableClass() local
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/ |
| D | operand.cpp | 166 RegOperand *baseReg = GetBaseRegister(); in Less() local
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| D | ebo.cpp | 409 Operand *baseReg = memOpnd->GetBaseRegister(); in ComputeHashVal() local
516 auto *baseReg = static_cast<RegOperand *>(base); in BuildMemOpndInfo() local
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| D | reg_alloc_lsra.cpp | 1202 uint32 baseReg = isInt ? firstIntReg : firstFpReg; in UpdateParamAllocateInfo() local
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/x86_64/ |
| D | x64_proepilog.cpp | 49 RegOperand &baseReg = cgFunc.GetOpndBuilder()->CreatePReg(x64::RBP, k64BitSize, kRegTyInt); in GenerateCalleeSavedRegs() local
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| D | x64_MPIsel.cpp | 934 …RegOperand &baseReg = cgFunc->GetOpndBuilder()->CreatePReg(x64::RBP, GetPrimTypeBitSize(PTY_i64), … in SelectRangeGoto() local
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch32/ |
| D | encode.cpp | 492 auto baseReg = VixlReg(mem.GetBase()); in PrepareMemLdS() local
565 auto baseReg = VixlReg(mem.GetBase()); in PrepareMemLdSForFloat() local
2798 vixl::aarch32::Register baseReg = VixlReg(base); in LoadStoreRegistersMainLoop() local
2839 vixl::aarch32::Register baseReg = VixlReg(base); in LoadStoreRegisters() local
2873 vixl::aarch32::Register baseReg = vixl::aarch32::sp; in LoadStoreRegisters() local
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| D | target.h | 751 auto baseReg = VixlReg(mem.GetBase()); in ConvertMem() local
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/ |
| D | target.h | 219 auto baseReg = Reg(mem.GetBase().GetId(), INT64_TYPE); in ConvertMem() local
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| D | encode.cpp | 1688 [[maybe_unused]] auto baseReg = mem.GetBase(); in EncodeLdr() local
1746 [[maybe_unused]] auto baseReg = mem.GetBase(); in EncodeLdrAcquireInvalid() local
1824 auto baseReg = mem.GetBase(); in CheckAlignment() local
2643 auto baseReg = VixlReg(base); in LoadStoreRegistersMainLoop() local
2734 const vixl::aarch64::Register &baseReg) in LoadStoreRegistersLoop()
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| /arkcompiler/ets_frontend/ets2panda/compiler/core/ |
| D | JSCompiler.cpp | 62 compiler::VReg baseReg = pg->AllocReg(); in CompileHeritageClause() local
371 compiler::VReg baseReg = CompileHeritageClause(pg, node); in Compile() local
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| /arkcompiler/runtime_core/static_core/libllvmbackend/lowering/ |
| D | llvm_ir_constructor.cpp | 599 std::string baseReg = representable ? "sp" : "x16"; in CreateInterpreterReturnRestoreRegs() local
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/amd64/ |
| D | encode.cpp | 2591 auto baseReg = ArchReg(base); in LoadStoreRegisters() local
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/ |
| D | codegen.cpp | 2201 void Codegen::CalculateCardIndex(Reg baseReg, ScopedTmpReg *tmp, ScopedTmpReg *tmp1) in CalculateCardIndex()
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