1 /*
2 * Copyright © 2015-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_compiler.h"
25 #include "brw_shader.h"
26 #include "brw_eu.h"
27 #include "dev/intel_debug.h"
28 #include "compiler/nir/nir.h"
29 #include "main/errors.h"
30 #include "util/debug.h"
31
32 #define COMMON_OPTIONS \
33 .lower_fdiv = true, \
34 .lower_scmp = true, \
35 .lower_flrp16 = true, \
36 .lower_fmod = true, \
37 .lower_bitfield_extract = true, \
38 .lower_bitfield_insert = true, \
39 .lower_uadd_carry = true, \
40 .lower_usub_borrow = true, \
41 .lower_flrp64 = true, \
42 .lower_fisnormal = true, \
43 .lower_isign = true, \
44 .lower_ldexp = true, \
45 .lower_device_index_to_zero = true, \
46 .vectorize_io = true, \
47 .use_interpolated_input_intrinsics = true, \
48 .lower_insert_byte = true, \
49 .lower_insert_word = true, \
50 .vertex_id_zero_based = true, \
51 .lower_base_vertex = true, \
52 .use_scoped_barrier = true, \
53 .support_16bit_alu = true, \
54 .lower_uniforms_to_ubo = true, \
55 .has_txs = true
56
57 #define COMMON_SCALAR_OPTIONS \
58 .lower_to_scalar = true, \
59 .lower_pack_half_2x16 = true, \
60 .lower_pack_snorm_2x16 = true, \
61 .lower_pack_snorm_4x8 = true, \
62 .lower_pack_unorm_2x16 = true, \
63 .lower_pack_unorm_4x8 = true, \
64 .lower_unpack_half_2x16 = true, \
65 .lower_unpack_snorm_2x16 = true, \
66 .lower_unpack_snorm_4x8 = true, \
67 .lower_unpack_unorm_2x16 = true, \
68 .lower_unpack_unorm_4x8 = true, \
69 .lower_hadd64 = true, \
70 .avoid_ternary_with_two_constants = true, \
71 .has_pack_32_4x8 = true, \
72 .max_unroll_iterations = 32, \
73 .force_indirect_unrolling = nir_var_function_temp, \
74 .divergence_analysis_options = \
75 (nir_divergence_single_prim_per_subgroup | \
76 nir_divergence_single_patch_per_tcs_subgroup | \
77 nir_divergence_single_patch_per_tes_subgroup)
78
79 static const struct nir_shader_compiler_options scalar_nir_options = {
80 COMMON_OPTIONS,
81 COMMON_SCALAR_OPTIONS,
82 };
83
84 static const struct nir_shader_compiler_options vector_nir_options = {
85 COMMON_OPTIONS,
86
87 /* In the vec4 backend, our dpN instruction replicates its result to all the
88 * components of a vec4. We would like NIR to give us replicated fdot
89 * instructions because it can optimize better for us.
90 */
91 .fdot_replicates = true,
92
93 .lower_usub_sat = true,
94 .lower_pack_snorm_2x16 = true,
95 .lower_pack_unorm_2x16 = true,
96 .lower_unpack_snorm_2x16 = true,
97 .lower_unpack_unorm_2x16 = true,
98 .lower_extract_byte = true,
99 .lower_extract_word = true,
100 .intel_vec4 = true,
101 .max_unroll_iterations = 32,
102 };
103
104 struct brw_compiler *
brw_compiler_create(void * mem_ctx,const struct intel_device_info * devinfo)105 brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
106 {
107 struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
108
109 compiler->devinfo = devinfo;
110
111 brw_init_isa_info(&compiler->isa, devinfo);
112
113 brw_fs_alloc_reg_sets(compiler);
114 if (devinfo->ver < 8)
115 brw_vec4_alloc_reg_set(compiler);
116
117 compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
118
119 compiler->use_tcs_8_patch =
120 devinfo->ver >= 12 ||
121 (devinfo->ver >= 9 && INTEL_DEBUG(DEBUG_TCS_EIGHT_PATCH));
122
123 /* Default to the sampler since that's what we've done since forever */
124 compiler->indirect_ubos_use_sampler = true;
125
126 /* There is no vec4 mode on Gfx10+, and we don't use it at all on Gfx8+. */
127 for (int i = MESA_SHADER_VERTEX; i < MESA_ALL_SHADER_STAGES; i++) {
128 compiler->scalar_stage[i] = devinfo->ver >= 8 ||
129 i == MESA_SHADER_FRAGMENT || i == MESA_SHADER_COMPUTE;
130 }
131
132 for (int i = MESA_SHADER_TASK; i < MESA_VULKAN_SHADER_STAGES; i++)
133 compiler->scalar_stage[i] = true;
134
135 nir_lower_int64_options int64_options =
136 nir_lower_imul64 |
137 nir_lower_isign64 |
138 nir_lower_divmod64 |
139 nir_lower_imul_high64;
140 nir_lower_doubles_options fp64_options =
141 nir_lower_drcp |
142 nir_lower_dsqrt |
143 nir_lower_drsq |
144 nir_lower_dtrunc |
145 nir_lower_dfloor |
146 nir_lower_dceil |
147 nir_lower_dfract |
148 nir_lower_dround_even |
149 nir_lower_dmod |
150 nir_lower_dsub |
151 nir_lower_ddiv;
152
153 if (!devinfo->has_64bit_float || INTEL_DEBUG(DEBUG_SOFT64))
154 fp64_options |= nir_lower_fp64_full_software;
155 if (!devinfo->has_64bit_int)
156 int64_options |= (nir_lower_int64_options)~0;
157
158 /* The Bspec's section titled "Instruction_multiply[DevBDW+]" claims that
159 * destination type can be Quadword and source type Doubleword for Gfx8 and
160 * Gfx9. So, lower 64 bit multiply instruction on rest of the platforms.
161 */
162 if (devinfo->ver < 8 || devinfo->ver > 9)
163 int64_options |= nir_lower_imul_2x32_64;
164
165 /* We want the GLSL compiler to emit code that uses condition codes */
166 for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
167 struct nir_shader_compiler_options *nir_options =
168 rzalloc(compiler, struct nir_shader_compiler_options);
169 bool is_scalar = compiler->scalar_stage[i];
170 if (is_scalar) {
171 *nir_options = scalar_nir_options;
172 int64_options |= nir_lower_usub_sat64;
173 } else {
174 *nir_options = vector_nir_options;
175 }
176
177 /* Prior to Gfx6, there are no three source operations, and Gfx11 loses
178 * LRP.
179 */
180 nir_options->lower_ffma16 = devinfo->ver < 6;
181 nir_options->lower_ffma32 = devinfo->ver < 6;
182 nir_options->lower_ffma64 = devinfo->ver < 6;
183 nir_options->lower_flrp32 = devinfo->ver < 6 || devinfo->ver >= 11;
184 nir_options->lower_fpow = devinfo->ver >= 12;
185
186 nir_options->lower_rotate = devinfo->ver < 11;
187 nir_options->lower_bitfield_reverse = devinfo->ver < 7;
188 nir_options->has_iadd3 = devinfo->verx10 >= 125;
189
190 nir_options->has_sdot_4x8 = devinfo->ver >= 12;
191 nir_options->has_udot_4x8 = devinfo->ver >= 12;
192 nir_options->has_sudot_4x8 = devinfo->ver >= 12;
193
194 nir_options->lower_int64_options = int64_options;
195 nir_options->lower_doubles_options = fp64_options;
196
197 nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
198
199 nir_options->force_indirect_unrolling |=
200 brw_nir_no_indirect_mask(compiler, i);
201 nir_options->force_indirect_unrolling_sampler = devinfo->ver < 7;
202
203 if (compiler->use_tcs_8_patch) {
204 /* TCS 8_PATCH mode has multiple patches per subgroup */
205 nir_options->divergence_analysis_options &=
206 ~nir_divergence_single_patch_per_tcs_subgroup;
207 }
208
209 compiler->nir_options[i] = nir_options;
210 }
211
212 return compiler;
213 }
214
215 static void
insert_u64_bit(uint64_t * val,bool add)216 insert_u64_bit(uint64_t *val, bool add)
217 {
218 *val = (*val << 1) | !!add;
219 }
220
221 uint64_t
brw_get_compiler_config_value(const struct brw_compiler * compiler)222 brw_get_compiler_config_value(const struct brw_compiler *compiler)
223 {
224 uint64_t config = 0;
225 insert_u64_bit(&config, compiler->precise_trig);
226
227 uint64_t mask = DEBUG_DISK_CACHE_MASK;
228 while (mask != 0) {
229 const uint64_t bit = 1ULL << (ffsll(mask) - 1);
230 insert_u64_bit(&config, INTEL_DEBUG(bit));
231 mask &= ~bit;
232 }
233 return config;
234 }
235
236 unsigned
brw_prog_data_size(gl_shader_stage stage)237 brw_prog_data_size(gl_shader_stage stage)
238 {
239 static const size_t stage_sizes[] = {
240 [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_data),
241 [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_data),
242 [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_data),
243 [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_data),
244 [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_data),
245 [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_data),
246 [MESA_SHADER_TASK] = sizeof(struct brw_task_prog_data),
247 [MESA_SHADER_MESH] = sizeof(struct brw_mesh_prog_data),
248 [MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_data),
249 [MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_data),
250 [MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_data),
251 [MESA_SHADER_MISS] = sizeof(struct brw_bs_prog_data),
252 [MESA_SHADER_INTERSECTION] = sizeof(struct brw_bs_prog_data),
253 [MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_data),
254 [MESA_SHADER_KERNEL] = sizeof(struct brw_cs_prog_data),
255 };
256 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
257 return stage_sizes[stage];
258 }
259
260 unsigned
brw_prog_key_size(gl_shader_stage stage)261 brw_prog_key_size(gl_shader_stage stage)
262 {
263 static const size_t stage_sizes[] = {
264 [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_key),
265 [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_key),
266 [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_key),
267 [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_key),
268 [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_key),
269 [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_key),
270 [MESA_SHADER_TASK] = sizeof(struct brw_task_prog_key),
271 [MESA_SHADER_MESH] = sizeof(struct brw_mesh_prog_key),
272 [MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_key),
273 [MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_key),
274 [MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_key),
275 [MESA_SHADER_MISS] = sizeof(struct brw_bs_prog_key),
276 [MESA_SHADER_INTERSECTION] = sizeof(struct brw_bs_prog_key),
277 [MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_key),
278 [MESA_SHADER_KERNEL] = sizeof(struct brw_cs_prog_key),
279 };
280 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
281 return stage_sizes[stage];
282 }
283
284 void
brw_write_shader_relocs(const struct brw_isa_info * isa,void * program,const struct brw_stage_prog_data * prog_data,struct brw_shader_reloc_value * values,unsigned num_values)285 brw_write_shader_relocs(const struct brw_isa_info *isa,
286 void *program,
287 const struct brw_stage_prog_data *prog_data,
288 struct brw_shader_reloc_value *values,
289 unsigned num_values)
290 {
291 for (unsigned i = 0; i < prog_data->num_relocs; i++) {
292 assert(prog_data->relocs[i].offset % 8 == 0);
293 void *dst = program + prog_data->relocs[i].offset;
294 for (unsigned j = 0; j < num_values; j++) {
295 if (prog_data->relocs[i].id == values[j].id) {
296 uint32_t value = values[j].value + prog_data->relocs[i].delta;
297 switch (prog_data->relocs[i].type) {
298 case BRW_SHADER_RELOC_TYPE_U32:
299 *(uint32_t *)dst = value;
300 break;
301 case BRW_SHADER_RELOC_TYPE_MOV_IMM:
302 brw_update_reloc_imm(isa, dst, value);
303 break;
304 default:
305 unreachable("Invalid relocation type");
306 }
307 break;
308 }
309 }
310 }
311 }
312