1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_visitor.cpp
25 *
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
29 */
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "compiler/glsl_types.h"
33
34 using namespace brw;
35
36 /* Sample from the MCS surface attached to this multisample texture. */
37 fs_reg
emit_mcs_fetch(const fs_reg & coordinate,unsigned components,const fs_reg & texture,const fs_reg & texture_handle)38 fs_visitor::emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
39 const fs_reg &texture,
40 const fs_reg &texture_handle)
41 {
42 const fs_reg dest = vgrf(glsl_type::uvec4_type);
43
44 fs_reg srcs[TEX_LOGICAL_NUM_SRCS];
45 srcs[TEX_LOGICAL_SRC_COORDINATE] = coordinate;
46 srcs[TEX_LOGICAL_SRC_SURFACE] = texture;
47 srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_ud(0);
48 srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE] = texture_handle;
49 srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(components);
50 srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(0);
51
52 fs_inst *inst = bld.emit(SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs,
53 ARRAY_SIZE(srcs));
54
55 /* We only care about one or two regs of response, but the sampler always
56 * writes 4/8.
57 */
58 inst->size_written = 4 * dest.component_size(inst->exec_size);
59
60 return dest;
61 }
62
63 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
64 void
emit_dummy_fs()65 fs_visitor::emit_dummy_fs()
66 {
67 int reg_width = dispatch_width / 8;
68
69 /* Everyone's favorite color. */
70 const float color[4] = { 1.0, 0.0, 1.0, 0.0 };
71 for (int i = 0; i < 4; i++) {
72 bld.MOV(fs_reg(MRF, 2 + i * reg_width, BRW_REGISTER_TYPE_F),
73 brw_imm_f(color[i]));
74 }
75
76 fs_inst *write;
77 write = bld.emit(FS_OPCODE_FB_WRITE);
78 write->eot = true;
79 write->last_rt = true;
80 if (devinfo->ver >= 6) {
81 write->base_mrf = 2;
82 write->mlen = 4 * reg_width;
83 } else {
84 write->header_size = 2;
85 write->base_mrf = 0;
86 write->mlen = 2 + 4 * reg_width;
87 }
88
89 /* Tell the SF we don't have any inputs. Gfx4-5 require at least one
90 * varying to avoid GPU hangs, so set that.
91 */
92 struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data);
93 wm_prog_data->num_varying_inputs = devinfo->ver < 6 ? 1 : 0;
94 memset(wm_prog_data->urb_setup, -1,
95 sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
96 brw_compute_urb_setup_index(wm_prog_data);
97
98 /* We don't have any uniforms. */
99 stage_prog_data->nr_params = 0;
100 stage_prog_data->curb_read_length = 0;
101 stage_prog_data->dispatch_grf_start_reg = 2;
102 wm_prog_data->dispatch_grf_start_reg_16 = 2;
103 wm_prog_data->dispatch_grf_start_reg_32 = 2;
104 grf_used = 1; /* Gfx4-5 don't allow zero GRF blocks */
105
106 calculate_cfg();
107 }
108
109 /* Input data is organized with first the per-primitive values, followed
110 * by per-vertex values. The per-vertex will have interpolation information
111 * associated, so use 4 components for each value.
112 */
113
114 /* The register location here is relative to the start of the URB
115 * data. It will get adjusted to be a real location before
116 * generate_code() time.
117 */
118 fs_reg
interp_reg(int location,int channel)119 fs_visitor::interp_reg(int location, int channel)
120 {
121 assert(stage == MESA_SHADER_FRAGMENT);
122 assert(BITFIELD64_BIT(location) & ~nir->info.per_primitive_inputs);
123
124 const struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
125
126 assert(prog_data->urb_setup[location] >= 0);
127 unsigned nr = prog_data->urb_setup[location];
128
129 /* Adjust so we start counting from the first per_vertex input. */
130 assert(nr >= prog_data->num_per_primitive_inputs);
131 nr -= prog_data->num_per_primitive_inputs;
132
133 const unsigned per_vertex_start = prog_data->num_per_primitive_inputs;
134 const unsigned regnr = per_vertex_start + (nr * 4) + channel;
135
136 return fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F);
137 }
138
139 /* The register location here is relative to the start of the URB
140 * data. It will get adjusted to be a real location before
141 * generate_code() time.
142 */
143 fs_reg
per_primitive_reg(int location)144 fs_visitor::per_primitive_reg(int location)
145 {
146 assert(stage == MESA_SHADER_FRAGMENT);
147 assert(BITFIELD64_BIT(location) & nir->info.per_primitive_inputs);
148
149 const struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
150
151 assert(prog_data->urb_setup[location] >= 0);
152
153 const unsigned regnr = prog_data->urb_setup[location];
154 assert(regnr < prog_data->num_per_primitive_inputs);
155
156 return fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F);
157 }
158
159 /** Emits the interpolation for the varying inputs. */
160 void
emit_interpolation_setup_gfx4()161 fs_visitor::emit_interpolation_setup_gfx4()
162 {
163 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
164
165 fs_builder abld = bld.annotate("compute pixel centers");
166 this->pixel_x = vgrf(glsl_type::uint_type);
167 this->pixel_y = vgrf(glsl_type::uint_type);
168 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
169 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
170 abld.ADD(this->pixel_x,
171 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
172 fs_reg(brw_imm_v(0x10101010)));
173 abld.ADD(this->pixel_y,
174 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
175 fs_reg(brw_imm_v(0x11001100)));
176
177 abld = bld.annotate("compute pixel deltas from v0");
178
179 this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL] =
180 vgrf(glsl_type::vec2_type);
181 const fs_reg &delta_xy = this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL];
182 const fs_reg xstart(negate(brw_vec1_grf(1, 0)));
183 const fs_reg ystart(negate(brw_vec1_grf(1, 1)));
184
185 if (devinfo->has_pln) {
186 for (unsigned i = 0; i < dispatch_width / 8; i++) {
187 abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 0), i),
188 quarter(this->pixel_x, i), xstart);
189 abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 1), i),
190 quarter(this->pixel_y, i), ystart);
191 }
192 } else {
193 abld.ADD(offset(delta_xy, abld, 0), this->pixel_x, xstart);
194 abld.ADD(offset(delta_xy, abld, 1), this->pixel_y, ystart);
195 }
196
197 this->pixel_z = fetch_payload_reg(bld, payload.source_depth_reg);
198
199 /* The SF program automatically handles doing the perspective correction or
200 * not based on wm_prog_data::interp_mode[] so we can use the same pixel
201 * offsets for both perspective and non-perspective.
202 */
203 this->delta_xy[BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL] =
204 this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL];
205
206 abld = bld.annotate("compute pos.w and 1/pos.w");
207 /* Compute wpos.w. It's always in our setup, since it's needed to
208 * interpolate the other attributes.
209 */
210 this->wpos_w = vgrf(glsl_type::float_type);
211 abld.emit(FS_OPCODE_LINTERP, wpos_w, delta_xy,
212 component(interp_reg(VARYING_SLOT_POS, 3), 0));
213 /* Compute the pixel 1/W value from wpos.w. */
214 this->pixel_w = vgrf(glsl_type::float_type);
215 abld.emit(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
216 }
217
218 static unsigned
brw_rnd_mode_from_nir(unsigned mode,unsigned * mask)219 brw_rnd_mode_from_nir(unsigned mode, unsigned *mask)
220 {
221 unsigned brw_mode = 0;
222 *mask = 0;
223
224 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 |
225 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 |
226 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64) &
227 mode) {
228 brw_mode |= BRW_RND_MODE_RTZ << BRW_CR0_RND_MODE_SHIFT;
229 *mask |= BRW_CR0_RND_MODE_MASK;
230 }
231 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 |
232 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 |
233 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64) &
234 mode) {
235 brw_mode |= BRW_RND_MODE_RTNE << BRW_CR0_RND_MODE_SHIFT;
236 *mask |= BRW_CR0_RND_MODE_MASK;
237 }
238 if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP16) {
239 brw_mode |= BRW_CR0_FP16_DENORM_PRESERVE;
240 *mask |= BRW_CR0_FP16_DENORM_PRESERVE;
241 }
242 if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP32) {
243 brw_mode |= BRW_CR0_FP32_DENORM_PRESERVE;
244 *mask |= BRW_CR0_FP32_DENORM_PRESERVE;
245 }
246 if (mode & FLOAT_CONTROLS_DENORM_PRESERVE_FP64) {
247 brw_mode |= BRW_CR0_FP64_DENORM_PRESERVE;
248 *mask |= BRW_CR0_FP64_DENORM_PRESERVE;
249 }
250 if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16)
251 *mask |= BRW_CR0_FP16_DENORM_PRESERVE;
252 if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32)
253 *mask |= BRW_CR0_FP32_DENORM_PRESERVE;
254 if (mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64)
255 *mask |= BRW_CR0_FP64_DENORM_PRESERVE;
256 if (mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE)
257 *mask |= BRW_CR0_FP_MODE_MASK;
258
259 if (*mask != 0)
260 assert((*mask & brw_mode) == brw_mode);
261
262 return brw_mode;
263 }
264
265 void
emit_shader_float_controls_execution_mode()266 fs_visitor::emit_shader_float_controls_execution_mode()
267 {
268 unsigned execution_mode = this->nir->info.float_controls_execution_mode;
269 if (execution_mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE)
270 return;
271
272 fs_builder abld = bld.annotate("shader floats control execution mode");
273 unsigned mask, mode = brw_rnd_mode_from_nir(execution_mode, &mask);
274
275 if (mask == 0)
276 return;
277
278 abld.emit(SHADER_OPCODE_FLOAT_CONTROL_MODE, bld.null_reg_ud(),
279 brw_imm_d(mode), brw_imm_d(mask));
280 }
281
282 /** Emits the interpolation for the varying inputs. */
283 void
emit_interpolation_setup_gfx6()284 fs_visitor::emit_interpolation_setup_gfx6()
285 {
286 fs_builder abld = bld.annotate("compute pixel centers");
287
288 this->pixel_x = vgrf(glsl_type::float_type);
289 this->pixel_y = vgrf(glsl_type::float_type);
290
291 struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(prog_data);
292
293 fs_reg int_pixel_offset_x, int_pixel_offset_y; /* Used on Gen12HP+ */
294 fs_reg int_pixel_offset_xy; /* Used on Gen8+ */
295 fs_reg half_int_pixel_offset_x, half_int_pixel_offset_y;
296 if (!wm_prog_data->per_coarse_pixel_dispatch) {
297 /* The thread payload only delivers subspan locations (ss0, ss1,
298 * ss2, ...). Since subspans covers 2x2 pixels blocks, we need to
299 * generate 4 pixel coordinates out of each subspan location. We do this
300 * by replicating a subspan coordinate 4 times and adding an offset of 1
301 * in each direction from the initial top left (tl) location to generate
302 * top right (tr = +1 in x), bottom left (bl = +1 in y) and bottom right
303 * (br = +1 in x, +1 in y).
304 *
305 * The locations we build look like this in SIMD8 :
306 *
307 * ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
308 *
309 * The value 0x11001010 is a vector of 8 half byte vector. It adds
310 * following to generate the 4 pixels coordinates out of the subspan0:
311 *
312 * 0x
313 * 1 : ss0.y + 1 -> ss0.br.y
314 * 1 : ss0.y + 1 -> ss0.bl.y
315 * 0 : ss0.y + 0 -> ss0.tr.y
316 * 0 : ss0.y + 0 -> ss0.tl.y
317 * 1 : ss0.x + 1 -> ss0.br.x
318 * 0 : ss0.x + 0 -> ss0.bl.x
319 * 1 : ss0.x + 1 -> ss0.tr.x
320 * 0 : ss0.x + 0 -> ss0.tl.x
321 *
322 * By doing a SIMD16 add in a SIMD8 shader, we can generate the 8 pixels
323 * coordinates out of 2 subspans coordinates in a single ADD instruction
324 * (twice the operation above).
325 */
326 int_pixel_offset_xy = fs_reg(brw_imm_v(0x11001010));
327 half_int_pixel_offset_x = fs_reg(brw_imm_uw(0));
328 half_int_pixel_offset_y = fs_reg(brw_imm_uw(0));
329 /* On Gfx12.5, because of regioning restrictions, the interpolation code
330 * is slightly different and works off X & Y only inputs. The ordering
331 * of the half bytes here is a bit odd, with each subspan replicated
332 * twice and every other element is discarded :
333 *
334 * ss0.tl ss0.tl ss0.tr ss0.tr ss0.bl ss0.bl ss0.br ss0.br
335 * X offset: 0 0 1 0 0 0 1 0
336 * Y offset: 0 0 0 0 1 0 1 0
337 */
338 int_pixel_offset_x = fs_reg(brw_imm_v(0x01000100));
339 int_pixel_offset_y = fs_reg(brw_imm_v(0x01010000));
340 } else {
341 /* In coarse pixel dispatch we have to do the same ADD instruction that
342 * we do in normal per pixel dispatch, except this time we're not adding
343 * 1 in each direction, but instead the coarse pixel size.
344 *
345 * The coarse pixel size is delivered as 2 u8 in r1.0
346 */
347 struct brw_reg r1_0 = retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), BRW_REGISTER_TYPE_UB);
348
349 const fs_builder dbld =
350 abld.exec_all().group(MIN2(16, dispatch_width) * 2, 0);
351
352 if (devinfo->verx10 >= 125) {
353 /* To build the array of half bytes we do and AND operation with the
354 * right mask in X.
355 */
356 int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
357 dbld.AND(int_pixel_offset_x, byte_offset(r1_0, 0), brw_imm_v(0x0f000f00));
358
359 /* And the right mask in Y. */
360 int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW);
361 dbld.AND(int_pixel_offset_y, byte_offset(r1_0, 1), brw_imm_v(0x0f0f0000));
362 } else {
363 /* To build the array of half bytes we do and AND operation with the
364 * right mask in X.
365 */
366 int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
367 dbld.AND(int_pixel_offset_x, byte_offset(r1_0, 0), brw_imm_v(0x0000f0f0));
368
369 /* And the right mask in Y. */
370 int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW);
371 dbld.AND(int_pixel_offset_y, byte_offset(r1_0, 1), brw_imm_v(0xff000000));
372
373 /* Finally OR the 2 registers. */
374 int_pixel_offset_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW);
375 dbld.OR(int_pixel_offset_xy, int_pixel_offset_x, int_pixel_offset_y);
376 }
377
378 /* Also compute the half pixel size used to center pixels. */
379 half_int_pixel_offset_x = bld.vgrf(BRW_REGISTER_TYPE_UW);
380 half_int_pixel_offset_y = bld.vgrf(BRW_REGISTER_TYPE_UW);
381
382 bld.SHR(half_int_pixel_offset_x, suboffset(r1_0, 0), brw_imm_ud(1));
383 bld.SHR(half_int_pixel_offset_y, suboffset(r1_0, 1), brw_imm_ud(1));
384 }
385
386 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
387 const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
388 struct brw_reg gi_uw = retype(brw_vec1_grf(1 + i, 0), BRW_REGISTER_TYPE_UW);
389
390 if (devinfo->verx10 >= 125) {
391 const fs_builder dbld =
392 abld.exec_all().group(hbld.dispatch_width() * 2, 0);
393 const fs_reg int_pixel_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
394 const fs_reg int_pixel_y = dbld.vgrf(BRW_REGISTER_TYPE_UW);
395
396 dbld.ADD(int_pixel_x,
397 fs_reg(stride(suboffset(gi_uw, 4), 2, 8, 0)),
398 int_pixel_offset_x);
399 dbld.ADD(int_pixel_y,
400 fs_reg(stride(suboffset(gi_uw, 5), 2, 8, 0)),
401 int_pixel_offset_y);
402
403 if (wm_prog_data->per_coarse_pixel_dispatch) {
404 dbld.ADD(int_pixel_x, int_pixel_x,
405 horiz_stride(half_int_pixel_offset_x, 0));
406 dbld.ADD(int_pixel_y, int_pixel_y,
407 horiz_stride(half_int_pixel_offset_y, 0));
408 }
409
410 hbld.MOV(offset(pixel_x, hbld, i), horiz_stride(int_pixel_x, 2));
411 hbld.MOV(offset(pixel_y, hbld, i), horiz_stride(int_pixel_y, 2));
412
413 } else if (devinfo->ver >= 8 || dispatch_width == 8) {
414 /* The "Register Region Restrictions" page says for BDW (and newer,
415 * presumably):
416 *
417 * "When destination spans two registers, the source may be one or
418 * two registers. The destination elements must be evenly split
419 * between the two registers."
420 *
421 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16
422 * to compute our pixel centers.
423 */
424 const fs_builder dbld =
425 abld.exec_all().group(hbld.dispatch_width() * 2, 0);
426 fs_reg int_pixel_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW);
427
428 dbld.ADD(int_pixel_xy,
429 fs_reg(stride(suboffset(gi_uw, 4), 1, 4, 0)),
430 int_pixel_offset_xy);
431
432 hbld.emit(FS_OPCODE_PIXEL_X, offset(pixel_x, hbld, i), int_pixel_xy,
433 horiz_stride(half_int_pixel_offset_x, 0));
434 hbld.emit(FS_OPCODE_PIXEL_Y, offset(pixel_y, hbld, i), int_pixel_xy,
435 horiz_stride(half_int_pixel_offset_y, 0));
436 } else {
437 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
438 *
439 * "When destination spans two registers, the source MUST span
440 * two registers."
441 *
442 * Since the GRF source of the ADD will only read a single register,
443 * we must do two separate ADDs in SIMD16.
444 */
445 const fs_reg int_pixel_x = hbld.vgrf(BRW_REGISTER_TYPE_UW);
446 const fs_reg int_pixel_y = hbld.vgrf(BRW_REGISTER_TYPE_UW);
447
448 hbld.ADD(int_pixel_x,
449 fs_reg(stride(suboffset(gi_uw, 4), 2, 4, 0)),
450 fs_reg(brw_imm_v(0x10101010)));
451 hbld.ADD(int_pixel_y,
452 fs_reg(stride(suboffset(gi_uw, 5), 2, 4, 0)),
453 fs_reg(brw_imm_v(0x11001100)));
454
455 /* As of gfx6, we can no longer mix float and int sources. We have
456 * to turn the integer pixel centers into floats for their actual
457 * use.
458 */
459 hbld.MOV(offset(pixel_x, hbld, i), int_pixel_x);
460 hbld.MOV(offset(pixel_y, hbld, i), int_pixel_y);
461 }
462 }
463
464 abld = bld.annotate("compute pos.z");
465 if (wm_prog_data->uses_depth_w_coefficients) {
466 assert(!wm_prog_data->uses_src_depth);
467 /* In coarse pixel mode, the HW doesn't interpolate Z coordinate
468 * properly. In the same way we have to add the coarse pixel size to
469 * pixels locations, here we recompute the Z value with 2 coefficients
470 * in X & Y axis.
471 */
472 fs_reg coef_payload = fetch_payload_reg(abld, payload.depth_w_coef_reg, BRW_REGISTER_TYPE_F);
473 const fs_reg x_start = brw_vec1_grf(coef_payload.nr, 2);
474 const fs_reg y_start = brw_vec1_grf(coef_payload.nr, 6);
475 const fs_reg z_cx = brw_vec1_grf(coef_payload.nr, 1);
476 const fs_reg z_cy = brw_vec1_grf(coef_payload.nr, 0);
477 const fs_reg z_c0 = brw_vec1_grf(coef_payload.nr, 3);
478
479 const fs_reg float_pixel_x = abld.vgrf(BRW_REGISTER_TYPE_F);
480 const fs_reg float_pixel_y = abld.vgrf(BRW_REGISTER_TYPE_F);
481
482 abld.ADD(float_pixel_x, this->pixel_x, negate(x_start));
483 abld.ADD(float_pixel_y, this->pixel_y, negate(y_start));
484
485 /* r1.0 - 0:7 ActualCoarsePixelShadingSize.X */
486 const fs_reg u8_cps_width = fs_reg(retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UB));
487 /* r1.0 - 15:8 ActualCoarsePixelShadingSize.Y */
488 const fs_reg u8_cps_height = byte_offset(u8_cps_width, 1);
489 const fs_reg u32_cps_width = abld.vgrf(BRW_REGISTER_TYPE_UD);
490 const fs_reg u32_cps_height = abld.vgrf(BRW_REGISTER_TYPE_UD);
491 abld.MOV(u32_cps_width, u8_cps_width);
492 abld.MOV(u32_cps_height, u8_cps_height);
493
494 const fs_reg f_cps_width = abld.vgrf(BRW_REGISTER_TYPE_F);
495 const fs_reg f_cps_height = abld.vgrf(BRW_REGISTER_TYPE_F);
496 abld.MOV(f_cps_width, u32_cps_width);
497 abld.MOV(f_cps_height, u32_cps_height);
498
499 /* Center in the middle of the coarse pixel. */
500 abld.MAD(float_pixel_x, float_pixel_x, brw_imm_f(0.5f), f_cps_width);
501 abld.MAD(float_pixel_y, float_pixel_y, brw_imm_f(0.5f), f_cps_height);
502
503 this->pixel_z = abld.vgrf(BRW_REGISTER_TYPE_F);
504 abld.MAD(this->pixel_z, z_c0, z_cx, float_pixel_x);
505 abld.MAD(this->pixel_z, this->pixel_z, z_cy, float_pixel_y);
506 }
507
508 if (wm_prog_data->uses_src_depth) {
509 assert(!wm_prog_data->uses_depth_w_coefficients);
510 this->pixel_z = fetch_payload_reg(bld, payload.source_depth_reg);
511 }
512
513 if (wm_prog_data->uses_src_w) {
514 abld = bld.annotate("compute pos.w");
515 this->pixel_w = fetch_payload_reg(abld, payload.source_w_reg);
516 this->wpos_w = vgrf(glsl_type::float_type);
517 abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
518 }
519
520 for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
521 this->delta_xy[i] = fetch_barycentric_reg(
522 bld, payload.barycentric_coord_reg[i]);
523 }
524
525 uint32_t centroid_modes = wm_prog_data->barycentric_interp_modes &
526 (1 << BRW_BARYCENTRIC_PERSPECTIVE_CENTROID |
527 1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID);
528
529 if (devinfo->needs_unlit_centroid_workaround && centroid_modes) {
530 /* Get the pixel/sample mask into f0 so that we know which
531 * pixels are lit. Then, for each channel that is unlit,
532 * replace the centroid data with non-centroid data.
533 */
534 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
535 bld.exec_all().group(1, 0)
536 .MOV(retype(brw_flag_reg(0, i), BRW_REGISTER_TYPE_UW),
537 retype(brw_vec1_grf(1 + i, 7), BRW_REGISTER_TYPE_UW));
538 }
539
540 for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
541 if (!(centroid_modes & (1 << i)))
542 continue;
543
544 const fs_reg centroid_delta_xy = delta_xy[i];
545 const fs_reg &pixel_delta_xy = delta_xy[i - 1];
546
547 delta_xy[i] = bld.vgrf(BRW_REGISTER_TYPE_F, 2);
548
549 for (unsigned c = 0; c < 2; c++) {
550 for (unsigned q = 0; q < dispatch_width / 8; q++) {
551 set_predicate(BRW_PREDICATE_NORMAL,
552 bld.quarter(q).SEL(
553 quarter(offset(delta_xy[i], bld, c), q),
554 quarter(offset(centroid_delta_xy, bld, c), q),
555 quarter(offset(pixel_delta_xy, bld, c), q)));
556 }
557 }
558 }
559 }
560 }
561
562 static enum brw_conditional_mod
cond_for_alpha_func(enum compare_func func)563 cond_for_alpha_func(enum compare_func func)
564 {
565 switch(func) {
566 case COMPARE_FUNC_GREATER:
567 return BRW_CONDITIONAL_G;
568 case COMPARE_FUNC_GEQUAL:
569 return BRW_CONDITIONAL_GE;
570 case COMPARE_FUNC_LESS:
571 return BRW_CONDITIONAL_L;
572 case COMPARE_FUNC_LEQUAL:
573 return BRW_CONDITIONAL_LE;
574 case COMPARE_FUNC_EQUAL:
575 return BRW_CONDITIONAL_EQ;
576 case COMPARE_FUNC_NOTEQUAL:
577 return BRW_CONDITIONAL_NEQ;
578 default:
579 unreachable("Not reached");
580 }
581 }
582
583 /**
584 * Alpha test support for when we compile it into the shader instead
585 * of using the normal fixed-function alpha test.
586 */
587 void
emit_alpha_test()588 fs_visitor::emit_alpha_test()
589 {
590 assert(stage == MESA_SHADER_FRAGMENT);
591 brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
592 const fs_builder abld = bld.annotate("Alpha test");
593
594 fs_inst *cmp;
595 if (key->alpha_test_func == COMPARE_FUNC_ALWAYS)
596 return;
597
598 if (key->alpha_test_func == COMPARE_FUNC_NEVER) {
599 /* f0.1 = 0 */
600 fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
601 BRW_REGISTER_TYPE_UW));
602 cmp = abld.CMP(bld.null_reg_f(), some_reg, some_reg,
603 BRW_CONDITIONAL_NEQ);
604 } else {
605 /* RT0 alpha */
606 fs_reg color = offset(outputs[0], bld, 3);
607
608 /* f0.1 &= func(color, ref) */
609 cmp = abld.CMP(bld.null_reg_f(), color, brw_imm_f(key->alpha_test_ref),
610 cond_for_alpha_func(key->alpha_test_func));
611 }
612 cmp->predicate = BRW_PREDICATE_NORMAL;
613 cmp->flag_subreg = 1;
614 }
615
616 fs_inst *
emit_single_fb_write(const fs_builder & bld,fs_reg color0,fs_reg color1,fs_reg src0_alpha,unsigned components)617 fs_visitor::emit_single_fb_write(const fs_builder &bld,
618 fs_reg color0, fs_reg color1,
619 fs_reg src0_alpha, unsigned components)
620 {
621 assert(stage == MESA_SHADER_FRAGMENT);
622 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
623
624 /* Hand over gl_FragDepth or the payload depth. */
625 const fs_reg dst_depth = fetch_payload_reg(bld, payload.dest_depth_reg);
626 fs_reg src_depth, src_stencil;
627
628 if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
629 src_depth = frag_depth;
630 } else if (source_depth_to_render_target) {
631 /* If we got here, we're in one of those strange Gen4-5 cases where
632 * we're forced to pass the source depth, unmodified, to the FB write.
633 * In this case, we don't want to use pixel_z because we may not have
634 * set up interpolation. It's also perfectly safe because it only
635 * happens on old hardware (no coarse interpolation) and this is
636 * explicitly the pass-through case.
637 */
638 assert(devinfo->ver <= 5);
639 src_depth = fetch_payload_reg(bld, payload.source_depth_reg);
640 }
641
642 if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))
643 src_stencil = frag_stencil;
644
645 const fs_reg sources[] = {
646 color0, color1, src0_alpha, src_depth, dst_depth, src_stencil,
647 (prog_data->uses_omask ? sample_mask : fs_reg()),
648 brw_imm_ud(components)
649 };
650 assert(ARRAY_SIZE(sources) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS);
651 fs_inst *write = bld.emit(FS_OPCODE_FB_WRITE_LOGICAL, fs_reg(),
652 sources, ARRAY_SIZE(sources));
653
654 if (prog_data->uses_kill) {
655 write->predicate = BRW_PREDICATE_NORMAL;
656 write->flag_subreg = sample_mask_flag_subreg(this);
657 }
658
659 return write;
660 }
661
662 void
emit_fb_writes()663 fs_visitor::emit_fb_writes()
664 {
665 assert(stage == MESA_SHADER_FRAGMENT);
666 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
667 brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
668
669 fs_inst *inst = NULL;
670
671 if (source_depth_to_render_target && devinfo->ver == 6) {
672 /* For outputting oDepth on gfx6, SIMD8 writes have to be used. This
673 * would require SIMD8 moves of each half to message regs, e.g. by using
674 * the SIMD lowering pass. Unfortunately this is more difficult than it
675 * sounds because the SIMD8 single-source message lacks channel selects
676 * for the second and third subspans.
677 */
678 limit_dispatch_width(8, "Depth writes unsupported in SIMD16+ mode.\n");
679 }
680
681 if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL)) {
682 /* From the 'Render Target Write message' section of the docs:
683 * "Output Stencil is not supported with SIMD16 Render Target Write
684 * Messages."
685 */
686 limit_dispatch_width(8, "gl_FragStencilRefARB unsupported "
687 "in SIMD16+ mode.\n");
688 }
689
690 /* ANV doesn't know about sample mask output during the wm key creation
691 * so we compute if we need replicate alpha and emit alpha to coverage
692 * workaround here.
693 */
694 const bool replicate_alpha = key->alpha_test_replicate_alpha ||
695 (key->nr_color_regions > 1 && key->alpha_to_coverage &&
696 (sample_mask.file == BAD_FILE || devinfo->ver == 6));
697
698 for (int target = 0; target < key->nr_color_regions; target++) {
699 /* Skip over outputs that weren't written. */
700 if (this->outputs[target].file == BAD_FILE)
701 continue;
702
703 const fs_builder abld = bld.annotate(
704 ralloc_asprintf(this->mem_ctx, "FB write target %d", target));
705
706 fs_reg src0_alpha;
707 if (devinfo->ver >= 6 && replicate_alpha && target != 0)
708 src0_alpha = offset(outputs[0], bld, 3);
709
710 inst = emit_single_fb_write(abld, this->outputs[target],
711 this->dual_src_output, src0_alpha, 4);
712 inst->target = target;
713 }
714
715 prog_data->dual_src_blend = (this->dual_src_output.file != BAD_FILE &&
716 this->outputs[0].file != BAD_FILE);
717 assert(!prog_data->dual_src_blend || key->nr_color_regions == 1);
718
719 if (inst == NULL) {
720 /* Even if there's no color buffers enabled, we still need to send
721 * alpha out the pipeline to our null renderbuffer to support
722 * alpha-testing, alpha-to-coverage, and so on.
723 */
724 /* FINISHME: Factor out this frequently recurring pattern into a
725 * helper function.
726 */
727 const fs_reg srcs[] = { reg_undef, reg_undef,
728 reg_undef, offset(this->outputs[0], bld, 3) };
729 const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 4);
730 bld.LOAD_PAYLOAD(tmp, srcs, 4, 0);
731
732 inst = emit_single_fb_write(bld, tmp, reg_undef, reg_undef, 4);
733 inst->target = 0;
734 }
735
736 inst->last_rt = true;
737 inst->eot = true;
738
739 if (devinfo->ver >= 11 && devinfo->ver <= 12 &&
740 prog_data->dual_src_blend) {
741 /* The dual-source RT write messages fail to release the thread
742 * dependency on ICL and TGL with SIMD32 dispatch, leading to hangs.
743 *
744 * XXX - Emit an extra single-source NULL RT-write marked LastRT in
745 * order to release the thread dependency without disabling
746 * SIMD32.
747 *
748 * The dual-source RT write messages may lead to hangs with SIMD16
749 * dispatch on ICL due some unknown reasons, see
750 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
751 */
752 limit_dispatch_width(8, "Dual source blending unsupported "
753 "in SIMD16 and SIMD32 modes.\n");
754 }
755 }
756
757 void
emit_urb_writes(const fs_reg & gs_vertex_count)758 fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
759 {
760 int slot, urb_offset, length;
761 int starting_urb_offset = 0;
762 const struct brw_vue_prog_data *vue_prog_data =
763 brw_vue_prog_data(this->prog_data);
764 const struct brw_vs_prog_key *vs_key =
765 (const struct brw_vs_prog_key *) this->key;
766 const GLbitfield64 psiz_mask =
767 VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PSIZ | VARYING_BIT_PRIMITIVE_SHADING_RATE;
768 const struct brw_vue_map *vue_map = &vue_prog_data->vue_map;
769 bool flush;
770 fs_reg sources[8];
771 fs_reg urb_handle;
772
773 if (stage == MESA_SHADER_TESS_EVAL)
774 urb_handle = fs_reg(retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD));
775 else
776 urb_handle = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
777
778 int header_size = 1;
779 fs_reg per_slot_offsets;
780
781 if (stage == MESA_SHADER_GEOMETRY) {
782 const struct brw_gs_prog_data *gs_prog_data =
783 brw_gs_prog_data(this->prog_data);
784
785 /* We need to increment the Global Offset to skip over the control data
786 * header and the extra "Vertex Count" field (1 HWord) at the beginning
787 * of the VUE. We're counting in OWords, so the units are doubled.
788 */
789 starting_urb_offset = 2 * gs_prog_data->control_data_header_size_hwords;
790 if (gs_prog_data->static_vertex_count == -1)
791 starting_urb_offset += 2;
792
793 /* We also need to use per-slot offsets. The per-slot offset is the
794 * Vertex Count. SIMD8 mode processes 8 different primitives at a
795 * time; each may output a different number of vertices.
796 */
797 header_size++;
798
799 /* The URB offset is in 128-bit units, so we need to multiply by 2 */
800 const int output_vertex_size_owords =
801 gs_prog_data->output_vertex_size_hwords * 2;
802
803 if (gs_vertex_count.file == IMM) {
804 per_slot_offsets = brw_imm_ud(output_vertex_size_owords *
805 gs_vertex_count.ud);
806 } else {
807 per_slot_offsets = vgrf(glsl_type::uint_type);
808 bld.MUL(per_slot_offsets, gs_vertex_count,
809 brw_imm_ud(output_vertex_size_owords));
810 }
811 }
812
813 length = 0;
814 urb_offset = starting_urb_offset;
815 flush = false;
816
817 /* SSO shaders can have VUE slots allocated which are never actually
818 * written to, so ignore them when looking for the last (written) slot.
819 */
820 int last_slot = vue_map->num_slots - 1;
821 while (last_slot > 0 &&
822 (vue_map->slot_to_varying[last_slot] == BRW_VARYING_SLOT_PAD ||
823 outputs[vue_map->slot_to_varying[last_slot]].file == BAD_FILE)) {
824 last_slot--;
825 }
826
827 bool urb_written = false;
828 for (slot = 0; slot < vue_map->num_slots; slot++) {
829 int varying = vue_map->slot_to_varying[slot];
830 switch (varying) {
831 case VARYING_SLOT_PSIZ: {
832 /* The point size varying slot is the vue header and is always in the
833 * vue map. But often none of the special varyings that live there
834 * are written and in that case we can skip writing to the vue
835 * header, provided the corresponding state properly clamps the
836 * values further down the pipeline. */
837 if ((vue_map->slots_valid & psiz_mask) == 0) {
838 assert(length == 0);
839 urb_offset++;
840 break;
841 }
842
843 fs_reg zero(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
844 bld.MOV(zero, brw_imm_ud(0u));
845
846 if (vue_map->slots_valid & VARYING_BIT_PRIMITIVE_SHADING_RATE &&
847 this->outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE].file != BAD_FILE) {
848 sources[length++] = this->outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE];
849 } else if (devinfo->has_coarse_pixel_primitive_and_cb) {
850 uint32_t one_fp16 = 0x3C00;
851 fs_reg one_by_one_fp16(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
852 bld.MOV(one_by_one_fp16, brw_imm_ud((one_fp16 << 16) | one_fp16));
853 sources[length++] = one_by_one_fp16;
854 } else {
855 sources[length++] = zero;
856 }
857
858 if (vue_map->slots_valid & VARYING_BIT_LAYER)
859 sources[length++] = this->outputs[VARYING_SLOT_LAYER];
860 else
861 sources[length++] = zero;
862
863 if (vue_map->slots_valid & VARYING_BIT_VIEWPORT)
864 sources[length++] = this->outputs[VARYING_SLOT_VIEWPORT];
865 else
866 sources[length++] = zero;
867
868 if (vue_map->slots_valid & VARYING_BIT_PSIZ)
869 sources[length++] = this->outputs[VARYING_SLOT_PSIZ];
870 else
871 sources[length++] = zero;
872 break;
873 }
874 case BRW_VARYING_SLOT_NDC:
875 case VARYING_SLOT_EDGE:
876 unreachable("unexpected scalar vs output");
877 break;
878
879 default:
880 /* gl_Position is always in the vue map, but isn't always written by
881 * the shader. Other varyings (clip distances) get added to the vue
882 * map but don't always get written. In those cases, the
883 * corresponding this->output[] slot will be invalid we and can skip
884 * the urb write for the varying. If we've already queued up a vue
885 * slot for writing we flush a mlen 5 urb write, otherwise we just
886 * advance the urb_offset.
887 */
888 if (varying == BRW_VARYING_SLOT_PAD ||
889 this->outputs[varying].file == BAD_FILE) {
890 if (length > 0)
891 flush = true;
892 else
893 urb_offset++;
894 break;
895 }
896
897 if (stage == MESA_SHADER_VERTEX && vs_key->clamp_vertex_color &&
898 (varying == VARYING_SLOT_COL0 ||
899 varying == VARYING_SLOT_COL1 ||
900 varying == VARYING_SLOT_BFC0 ||
901 varying == VARYING_SLOT_BFC1)) {
902 /* We need to clamp these guys, so do a saturating MOV into a
903 * temp register and use that for the payload.
904 */
905 for (int i = 0; i < 4; i++) {
906 fs_reg reg = fs_reg(VGRF, alloc.allocate(1), outputs[varying].type);
907 fs_reg src = offset(this->outputs[varying], bld, i);
908 set_saturate(true, bld.MOV(reg, src));
909 sources[length++] = reg;
910 }
911 } else {
912 int slot_offset = 0;
913
914 /* When using Primitive Replication, there may be multiple slots
915 * assigned to POS.
916 */
917 if (varying == VARYING_SLOT_POS)
918 slot_offset = slot - vue_map->varying_to_slot[VARYING_SLOT_POS];
919
920 for (unsigned i = 0; i < 4; i++) {
921 sources[length++] = offset(this->outputs[varying], bld,
922 i + (slot_offset * 4));
923 }
924 }
925 break;
926 }
927
928 const fs_builder abld = bld.annotate("URB write");
929
930 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
931 * the last slot or if we need to flush (see BAD_FILE varying case
932 * above), emit a URB write send now to flush out the data.
933 */
934 if (length == 8 || (length > 0 && slot == last_slot))
935 flush = true;
936 if (flush) {
937 fs_reg srcs[URB_LOGICAL_NUM_SRCS];
938
939 srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle;
940 srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = per_slot_offsets;
941 srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, alloc.allocate(length),
942 BRW_REGISTER_TYPE_F);
943 abld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, length, 0);
944
945 fs_inst *inst = abld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef,
946 srcs, ARRAY_SIZE(srcs));
947
948 /* For ICL Wa_1805992985 one needs additional write in the end. */
949 if (devinfo->ver == 11 && stage == MESA_SHADER_TESS_EVAL)
950 inst->eot = false;
951 else
952 inst->eot = slot == last_slot && stage != MESA_SHADER_GEOMETRY;
953
954 inst->mlen = length + header_size;
955 inst->offset = urb_offset;
956 urb_offset = starting_urb_offset + slot + 1;
957 length = 0;
958 flush = false;
959 urb_written = true;
960 }
961 }
962
963 /* If we don't have any valid slots to write, just do a minimal urb write
964 * send to terminate the shader. This includes 1 slot of undefined data,
965 * because it's invalid to write 0 data:
966 *
967 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
968 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
969 * Write Data Payload:
970 *
971 * "The write data payload can be between 1 and 8 message phases long."
972 */
973 if (!urb_written) {
974 /* For GS, just turn EmitVertex() into a no-op. We don't want it to
975 * end the thread, and emit_gs_thread_end() already emits a SEND with
976 * EOT at the end of the program for us.
977 */
978 if (stage == MESA_SHADER_GEOMETRY)
979 return;
980
981 fs_reg uniform_urb_handle = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
982 fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
983
984 bld.exec_all().MOV(uniform_urb_handle, urb_handle);
985
986 fs_reg srcs[URB_LOGICAL_NUM_SRCS];
987 srcs[URB_LOGICAL_SRC_HANDLE] = uniform_urb_handle;
988 srcs[URB_LOGICAL_SRC_DATA] = payload;
989
990 fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef,
991 srcs, ARRAY_SIZE(srcs));
992 inst->eot = true;
993 inst->mlen = 2;
994 inst->offset = 1;
995 return;
996 }
997
998 /* ICL Wa_1805992985:
999 *
1000 * ICLLP GPU hangs on one of tessellation vkcts tests with DS not done. The
1001 * send cycle, which is a urb write with an eot must be 4 phases long and
1002 * all 8 lanes must valid.
1003 */
1004 if (devinfo->ver == 11 && stage == MESA_SHADER_TESS_EVAL) {
1005 fs_reg uniform_urb_handle = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
1006 fs_reg uniform_mask = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
1007 fs_reg payload = fs_reg(VGRF, alloc.allocate(4), BRW_REGISTER_TYPE_UD);
1008
1009 /* Workaround requires all 8 channels (lanes) to be valid. This is
1010 * understood to mean they all need to be alive. First trick is to find
1011 * a live channel and copy its urb handle for all the other channels to
1012 * make sure all handles are valid.
1013 */
1014 bld.exec_all().MOV(uniform_urb_handle, bld.emit_uniformize(urb_handle));
1015
1016 /* Second trick is to use masked URB write where one can tell the HW to
1017 * actually write data only for selected channels even though all are
1018 * active.
1019 * Third trick is to take advantage of the must-be-zero (MBZ) area in
1020 * the very beginning of the URB.
1021 *
1022 * One masks data to be written only for the first channel and uses
1023 * offset zero explicitly to land data to the MBZ area avoiding trashing
1024 * any other part of the URB.
1025 *
1026 * Since the WA says that the write needs to be 4 phases long one uses
1027 * 4 slots data. All are explicitly zeros in order to to keep the MBZ
1028 * area written as zeros.
1029 */
1030 bld.exec_all().MOV(uniform_mask, brw_imm_ud(0x10000u));
1031 bld.exec_all().MOV(offset(payload, bld, 0), brw_imm_ud(0u));
1032 bld.exec_all().MOV(offset(payload, bld, 1), brw_imm_ud(0u));
1033 bld.exec_all().MOV(offset(payload, bld, 2), brw_imm_ud(0u));
1034 bld.exec_all().MOV(offset(payload, bld, 3), brw_imm_ud(0u));
1035
1036 fs_reg srcs[URB_LOGICAL_NUM_SRCS];
1037 srcs[URB_LOGICAL_SRC_HANDLE] = uniform_urb_handle;
1038 srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = uniform_mask;
1039 srcs[URB_LOGICAL_SRC_DATA] = payload;
1040
1041 fs_inst *inst = bld.exec_all().emit(SHADER_OPCODE_URB_WRITE_LOGICAL,
1042 reg_undef, srcs, ARRAY_SIZE(srcs));
1043 inst->eot = true;
1044 inst->mlen = 6;
1045 inst->offset = 0;
1046 }
1047 }
1048
1049 void
emit_urb_fence()1050 fs_visitor::emit_urb_fence()
1051 {
1052 fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD);
1053 fs_inst *fence = bld.emit(SHADER_OPCODE_MEMORY_FENCE, dst,
1054 brw_vec8_grf(0, 0),
1055 brw_imm_ud(true),
1056 brw_imm_ud(0));
1057 fence->sfid = BRW_SFID_URB;
1058 fence->desc = lsc_fence_msg_desc(devinfo, LSC_FENCE_LOCAL,
1059 LSC_FLUSH_TYPE_NONE, true);
1060
1061 bld.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE,
1062 bld.null_reg_ud(),
1063 &dst,
1064 1);
1065 }
1066
1067 void
emit_cs_terminate()1068 fs_visitor::emit_cs_terminate()
1069 {
1070 assert(devinfo->ver >= 7);
1071
1072 /* We can't directly send from g0, since sends with EOT have to use
1073 * g112-127. So, copy it to a virtual register, The register allocator will
1074 * make sure it uses the appropriate register range.
1075 */
1076 struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD);
1077 fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
1078 bld.group(8, 0).exec_all().MOV(payload, g0);
1079
1080 /* Send a message to the thread spawner to terminate the thread. */
1081 fs_inst *inst = bld.exec_all()
1082 .emit(CS_OPCODE_CS_TERMINATE, reg_undef, payload);
1083 inst->eot = true;
1084 }
1085
1086 void
emit_barrier()1087 fs_visitor::emit_barrier()
1088 {
1089 /* We are getting the barrier ID from the compute shader header */
1090 assert(gl_shader_stage_uses_workgroup(stage));
1091
1092 fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
1093
1094 /* Clear the message payload */
1095 bld.exec_all().group(8, 0).MOV(payload, brw_imm_ud(0u));
1096
1097 if (devinfo->verx10 >= 125) {
1098 /* mov r0.2[31:24] into m0.2[31:24] and m0.2[23:16] */
1099 fs_reg m0_10ub = component(retype(payload, BRW_REGISTER_TYPE_UB), 10);
1100 fs_reg r0_11ub =
1101 stride(suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UB), 11),
1102 0, 1, 0);
1103 bld.exec_all().group(2, 0).MOV(m0_10ub, r0_11ub);
1104 } else {
1105 assert(gl_shader_stage_is_compute(stage));
1106
1107 uint32_t barrier_id_mask;
1108 switch (devinfo->ver) {
1109 case 7:
1110 case 8:
1111 barrier_id_mask = 0x0f000000u; break;
1112 case 9:
1113 barrier_id_mask = 0x8f000000u; break;
1114 case 11:
1115 case 12:
1116 barrier_id_mask = 0x7f000000u; break;
1117 default:
1118 unreachable("barrier is only available on gen >= 7");
1119 }
1120
1121 /* Copy the barrier id from r0.2 to the message payload reg.2 */
1122 fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD));
1123 bld.exec_all().group(1, 0).AND(component(payload, 2), r0_2,
1124 brw_imm_ud(barrier_id_mask));
1125 }
1126
1127 /* Emit a gateway "barrier" message using the payload we set up, followed
1128 * by a wait instruction.
1129 */
1130 bld.exec_all().emit(SHADER_OPCODE_BARRIER, reg_undef, payload);
1131 }
1132
fs_visitor(const struct brw_compiler * compiler,void * log_data,void * mem_ctx,const brw_base_prog_key * key,struct brw_stage_prog_data * prog_data,const nir_shader * shader,unsigned dispatch_width,bool debug_enabled)1133 fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
1134 void *mem_ctx,
1135 const brw_base_prog_key *key,
1136 struct brw_stage_prog_data *prog_data,
1137 const nir_shader *shader,
1138 unsigned dispatch_width,
1139 bool debug_enabled)
1140 : backend_shader(compiler, log_data, mem_ctx, shader, prog_data,
1141 debug_enabled),
1142 key(key), gs_compile(NULL), prog_data(prog_data),
1143 live_analysis(this), regpressure_analysis(this),
1144 performance_analysis(this),
1145 dispatch_width(dispatch_width),
1146 bld(fs_builder(this, dispatch_width).at_end())
1147 {
1148 init();
1149 }
1150
fs_visitor(const struct brw_compiler * compiler,void * log_data,void * mem_ctx,struct brw_gs_compile * c,struct brw_gs_prog_data * prog_data,const nir_shader * shader,bool debug_enabled)1151 fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
1152 void *mem_ctx,
1153 struct brw_gs_compile *c,
1154 struct brw_gs_prog_data *prog_data,
1155 const nir_shader *shader,
1156 bool debug_enabled)
1157 : backend_shader(compiler, log_data, mem_ctx, shader,
1158 &prog_data->base.base, debug_enabled),
1159 key(&c->key.base), gs_compile(c),
1160 prog_data(&prog_data->base.base),
1161 live_analysis(this), regpressure_analysis(this),
1162 performance_analysis(this),
1163 dispatch_width(8),
1164 bld(fs_builder(this, dispatch_width).at_end())
1165 {
1166 init();
1167 }
1168
1169
1170 void
init()1171 fs_visitor::init()
1172 {
1173 if (key)
1174 this->key_tex = &key->tex;
1175 else
1176 this->key_tex = NULL;
1177
1178 this->max_dispatch_width = 32;
1179 this->prog_data = this->stage_prog_data;
1180
1181 this->failed = false;
1182 this->fail_msg = NULL;
1183
1184 this->nir_locals = NULL;
1185 this->nir_ssa_values = NULL;
1186 this->nir_system_values = NULL;
1187
1188 memset(&this->payload, 0, sizeof(this->payload));
1189 this->source_depth_to_render_target = false;
1190 this->runtime_check_aads_emit = false;
1191 this->first_non_payload_grf = 0;
1192 this->max_grf = devinfo->ver >= 7 ? GFX7_MRF_HACK_START : BRW_MAX_GRF;
1193
1194 this->uniforms = 0;
1195 this->last_scratch = 0;
1196 this->push_constant_loc = NULL;
1197
1198 this->shader_stats.scheduler_mode = NULL;
1199 this->shader_stats.promoted_constants = 0,
1200 this->shader_stats.spill_count = 0,
1201 this->shader_stats.fill_count = 0,
1202
1203 this->grf_used = 0;
1204 this->spilled_any_registers = false;
1205 }
1206
~fs_visitor()1207 fs_visitor::~fs_visitor()
1208 {
1209 }
1210