| /third_party/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 472 __ fmls(z7.VnH(), z11.VnH(), z7.VnH(), 4); in TEST() local
475 __ fmls(z3.VnS(), z10.VnS(), z3.VnS(), 3); in TEST() local
478 __ fmls(z5.VnD(), z16.VnD(), z5.VnD(), 1); in TEST() local
481 __ fmls(z31.VnD(), z31.VnD(), z8.VnD(), 1); in TEST() local
484 __ fmls(z5.VnH(), p3.Merging(), z5.VnH(), z2.VnH()); in TEST() local
487 __ fmls(z22.VnS(), p3.Merging(), z21.VnS(), z22.VnS()); in TEST() local
490 __ fmls(z17.VnH(), z17.VnH(), z2.VnH(), 4); in TEST() local
493 __ fmls(z28.VnS(), z28.VnS(), z0.VnS(), 3); in TEST() local
976 __ fmls(z15.VnH(), p1.Merging(), z28.VnH(), z20.VnH()); in TEST() local
1308 __ fmls(z19.VnD(), z27.VnD(), z13.VnD(), 1); in TEST() local
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| D | test-trace-aarch64.cc | 2658 __ fmls(d27, d30, v6.D(), 0); in GenerateTestSequenceNEONFP() local
2659 __ fmls(s21, s16, v2.S(), 0); in GenerateTestSequenceNEONFP() local
2660 __ fmls(v5.V2D(), v19.V2D(), v21.V2D()); in GenerateTestSequenceNEONFP() local
2661 __ fmls(v18.V2D(), v30.V2D(), v12.D(), 0); in GenerateTestSequenceNEONFP() local
2662 __ fmls(v5.V2S(), v16.V2S(), v7.V2S()); in GenerateTestSequenceNEONFP() local
2663 __ fmls(v3.V2S(), v18.V2S(), v11.S(), 1); in GenerateTestSequenceNEONFP() local
2664 __ fmls(v27.V4S(), v5.V4S(), v30.V4S()); in GenerateTestSequenceNEONFP() local
2665 __ fmls(v26.V4S(), v20.V4S(), v4.S(), 3); in GenerateTestSequenceNEONFP() local
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-logic-arm64.cc | 3505 LogicVRegister Simulator::fmls(VectorFormat vform, LogicVRegister dst, in fmls() function in v8::internal::Simulator
3519 LogicVRegister Simulator::fmls(VectorFormat vform, LogicVRegister dst, in fmls() function in v8::internal::Simulator
3697 LogicVRegister Simulator::fmls(VectorFormat vform, LogicVRegister dst, in fmls() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 5242 LogicVRegister Simulator::fmls(VectorFormat vform, in fmls() function in vixl::aarch64::Simulator
5259 LogicVRegister Simulator::fmls(VectorFormat vform, in fmls() function in vixl::aarch64::Simulator
5725 LogicVRegister Simulator::fmls(VectorFormat vform, in fmls() function in vixl::aarch64::Simulator
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| D | assembler-sve-aarch64.cc | 1433 void Assembler::fmls(const ZRegister& zda, in fmls() function in vixl::aarch64::Assembler
1626 void Assembler::fmls(const ZRegister& zda, in fmls() function in vixl::aarch64::Assembler
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