/third_party/ltp/tools/sparse/sparse-src/validation/ |
D | fp-ops.c | 5 double fneg(double x) { return -x; } in fneg() function
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/third_party/ltp/tools/sparse/sparse-src/validation/backend/ |
D | arithmetic-ops.c | 101 static float fneg(float x) in fneg() function
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/third_party/mesa3d/src/amd/compiler/tests/ |
D | helpers.cpp | 271 Temp fneg(Temp src, Builder b) in fneg() function
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/third_party/vixl/test/aarch64/ |
D | test-trace-aarch64.cc | 547 __ fneg(d15, d0); in GenerateTestSequenceFP() local 548 __ fneg(s14, s15); in GenerateTestSequenceFP() local 2687 __ fneg(v1.V2D(), v25.V2D()); in GenerateTestSequenceNEONFP() local 2688 __ fneg(v14.V2S(), v31.V2S()); in GenerateTestSequenceNEONFP() local 2689 __ fneg(v5.V4S(), v4.V4S()); in GenerateTestSequenceNEONFP() local
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D | test-api-movprfx-aarch64.cc | 508 __ fneg(z17.VnH(), p1.Merging(), z17.VnH()); in TEST() local 997 __ fneg(z6.VnS(), p2.Merging(), z28.VnS()); in TEST() local 1859 __ fneg(z5.VnH(), p0.Merging(), z1.VnH()); in TEST() local
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D | test-assembler-fp-aarch64.cc | 2106 TEST(fneg) { in TEST() argument
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/third_party/mesa3d/src/amd/compiler/ |
D | aco_optimizer.cpp | 3479 VOP3P_instruction* fneg = &info.instr->vop3p(); in combine_vop3p() local
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/third_party/node/deps/v8/src/execution/arm64/ |
D | simulator-logic-arm64.cc | 3532 LogicVRegister Simulator::fneg(VectorFormat vform, LogicVRegister dst, in fneg() function in v8::internal::Simulator 3543 LogicVRegister Simulator::fneg(VectorFormat vform, LogicVRegister dst, in fneg() function in v8::internal::Simulator
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/third_party/node/deps/v8/src/codegen/ppc/ |
D | assembler-ppc.cc | 1854 void Assembler::fneg(const DoubleRegister frt, const DoubleRegister frb, in fneg() function in v8::internal::Assembler
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/third_party/vixl/src/aarch64/ |
D | logic-aarch64.cc | 5421 LogicVRegister Simulator::fneg(VectorFormat vform, in fneg() function in vixl::aarch64::Simulator 5434 LogicVRegister Simulator::fneg(VectorFormat vform, in fneg() function in vixl::aarch64::Simulator
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D | assembler-sve-aarch64.cc | 3432 void Assembler::fneg(const ZRegister& zd, in fneg() function in vixl::aarch64::Assembler
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