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Searched defs:fneg (Results 1 – 11 of 11) sorted by relevance

/third_party/ltp/tools/sparse/sparse-src/validation/
Dfp-ops.c5 double fneg(double x) { return -x; } in fneg() function
/third_party/ltp/tools/sparse/sparse-src/validation/backend/
Darithmetic-ops.c101 static float fneg(float x) in fneg() function
/third_party/mesa3d/src/amd/compiler/tests/
Dhelpers.cpp271 Temp fneg(Temp src, Builder b) in fneg() function
/third_party/vixl/test/aarch64/
Dtest-trace-aarch64.cc547 __ fneg(d15, d0); in GenerateTestSequenceFP() local
548 __ fneg(s14, s15); in GenerateTestSequenceFP() local
2687 __ fneg(v1.V2D(), v25.V2D()); in GenerateTestSequenceNEONFP() local
2688 __ fneg(v14.V2S(), v31.V2S()); in GenerateTestSequenceNEONFP() local
2689 __ fneg(v5.V4S(), v4.V4S()); in GenerateTestSequenceNEONFP() local
Dtest-api-movprfx-aarch64.cc508 __ fneg(z17.VnH(), p1.Merging(), z17.VnH()); in TEST() local
997 __ fneg(z6.VnS(), p2.Merging(), z28.VnS()); in TEST() local
1859 __ fneg(z5.VnH(), p0.Merging(), z1.VnH()); in TEST() local
Dtest-assembler-fp-aarch64.cc2106 TEST(fneg) { in TEST() argument
/third_party/mesa3d/src/amd/compiler/
Daco_optimizer.cpp3479 VOP3P_instruction* fneg = &info.instr->vop3p(); in combine_vop3p() local
/third_party/node/deps/v8/src/execution/arm64/
Dsimulator-logic-arm64.cc3532 LogicVRegister Simulator::fneg(VectorFormat vform, LogicVRegister dst, in fneg() function in v8::internal::Simulator
3543 LogicVRegister Simulator::fneg(VectorFormat vform, LogicVRegister dst, in fneg() function in v8::internal::Simulator
/third_party/node/deps/v8/src/codegen/ppc/
Dassembler-ppc.cc1854 void Assembler::fneg(const DoubleRegister frt, const DoubleRegister frb, in fneg() function in v8::internal::Assembler
/third_party/vixl/src/aarch64/
Dlogic-aarch64.cc5421 LogicVRegister Simulator::fneg(VectorFormat vform, in fneg() function in vixl::aarch64::Simulator
5434 LogicVRegister Simulator::fneg(VectorFormat vform, in fneg() function in vixl::aarch64::Simulator
Dassembler-sve-aarch64.cc3432 void Assembler::fneg(const ZRegister& zd, in fneg() function in vixl::aarch64::Assembler