1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/ISDOpcodes.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/RuntimeLibcalls.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/CodeGen/TargetLowering.h"
33 #include "llvm/CodeGen/TargetOpcodes.h"
34 #include "llvm/CodeGen/TargetRegisterInfo.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalValue.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/IRBuilder.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
46 #include "llvm/Support/BranchProbability.h"
47 #include "llvm/Support/Casting.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MachineValueType.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include <algorithm>
55 #include <cassert>
56 #include <cstddef>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <tuple>
62 #include <utility>
63
64 using namespace llvm;
65
66 static cl::opt<bool> JumpIsExpensiveOverride(
67 "jump-is-expensive", cl::init(false),
68 cl::desc("Do not create extra branches to split comparison logic."),
69 cl::Hidden);
70
71 static cl::opt<unsigned> MinimumJumpTableEntries
72 ("min-jump-table-entries", cl::init(4), cl::Hidden,
73 cl::desc("Set minimum number of entries to use a jump table."));
74
75 static cl::opt<unsigned> MaximumJumpTableSize
76 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
77 cl::desc("Set maximum size of jump tables."));
78
79 /// Minimum jump table density for normal functions.
80 static cl::opt<unsigned>
81 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
82 cl::desc("Minimum density for building a jump table in "
83 "a normal function"));
84
85 /// Minimum jump table density for -Os or -Oz functions.
86 static cl::opt<unsigned> OptsizeJumpTableDensity(
87 "optsize-jump-table-density", cl::init(40), cl::Hidden,
88 cl::desc("Minimum density for building a jump table in "
89 "an optsize function"));
90
91 // FIXME: This option is only to test if the strict fp operation processed
92 // correctly by preventing mutating strict fp operation to normal fp operation
93 // during development. When the backend supports strict float operation, this
94 // option will be meaningless.
95 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
96 cl::desc("Don't mutate strict-float node to a legalize node"),
97 cl::init(false), cl::Hidden);
98
darwinHasSinCos(const Triple & TT)99 static bool darwinHasSinCos(const Triple &TT) {
100 assert(TT.isOSDarwin() && "should be called with darwin triple");
101 // Don't bother with 32 bit x86.
102 if (TT.getArch() == Triple::x86)
103 return false;
104 // Macos < 10.9 has no sincos_stret.
105 if (TT.isMacOSX())
106 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
107 // iOS < 7.0 has no sincos_stret.
108 if (TT.isiOS())
109 return !TT.isOSVersionLT(7, 0);
110 // Any other darwin such as WatchOS/TvOS is new enough.
111 return true;
112 }
113
114 // Although this default value is arbitrary, it is not random. It is assumed
115 // that a condition that evaluates the same way by a higher percentage than this
116 // is best represented as control flow. Therefore, the default value N should be
117 // set such that the win from N% correct executions is greater than the loss
118 // from (100 - N)% mispredicted executions for the majority of intended targets.
119 static cl::opt<int> MinPercentageForPredictableBranch(
120 "min-predictable-branch", cl::init(99),
121 cl::desc("Minimum percentage (0-100) that a condition must be either true "
122 "or false to assume that the condition is predictable"),
123 cl::Hidden);
124
InitLibcalls(const Triple & TT)125 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
126 #define HANDLE_LIBCALL(code, name) \
127 setLibcallName(RTLIB::code, name);
128 #include "llvm/IR/RuntimeLibcalls.def"
129 #undef HANDLE_LIBCALL
130 // Initialize calling conventions to their default.
131 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
132 setLibcallCallingConv((RTLIB::Libcall)LC, CallingConv::C);
133
134 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
135 if (TT.getArch() == Triple::ppc || TT.isPPC64()) {
136 setLibcallName(RTLIB::ADD_F128, "__addkf3");
137 setLibcallName(RTLIB::SUB_F128, "__subkf3");
138 setLibcallName(RTLIB::MUL_F128, "__mulkf3");
139 setLibcallName(RTLIB::DIV_F128, "__divkf3");
140 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
141 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
142 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
143 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
144 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
145 setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
146 setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
147 setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
148 setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
149 setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
150 setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
151 setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
152 setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
153 setLibcallName(RTLIB::UNE_F128, "__nekf2");
154 setLibcallName(RTLIB::OGE_F128, "__gekf2");
155 setLibcallName(RTLIB::OLT_F128, "__ltkf2");
156 setLibcallName(RTLIB::OLE_F128, "__lekf2");
157 setLibcallName(RTLIB::OGT_F128, "__gtkf2");
158 setLibcallName(RTLIB::UO_F128, "__unordkf2");
159 }
160
161 // A few names are different on particular architectures or environments.
162 if (TT.isOSDarwin()) {
163 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
164 // of the gnueabi-style __gnu_*_ieee.
165 // FIXME: What about other targets?
166 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
167 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
168
169 // Some darwins have an optimized __bzero/bzero function.
170 switch (TT.getArch()) {
171 case Triple::x86:
172 case Triple::x86_64:
173 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
174 setLibcallName(RTLIB::BZERO, "__bzero");
175 break;
176 case Triple::aarch64:
177 case Triple::aarch64_32:
178 setLibcallName(RTLIB::BZERO, "bzero");
179 break;
180 default:
181 break;
182 }
183
184 if (darwinHasSinCos(TT)) {
185 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
186 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
187 if (TT.isWatchABI()) {
188 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
189 CallingConv::ARM_AAPCS_VFP);
190 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
191 CallingConv::ARM_AAPCS_VFP);
192 }
193 }
194 } else {
195 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
196 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
197 }
198
199 if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
200 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
201 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
202 setLibcallName(RTLIB::SINCOS_F64, "sincos");
203 setLibcallName(RTLIB::SINCOS_F80, "sincosl");
204 setLibcallName(RTLIB::SINCOS_F128, "sincosl");
205 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
206 }
207
208 if (TT.isPS4CPU()) {
209 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
210 setLibcallName(RTLIB::SINCOS_F64, "sincos");
211 }
212
213 if (TT.isOSOpenBSD()) {
214 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
215 }
216 }
217
218 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
219 /// UNKNOWN_LIBCALL if there is none.
getFPEXT(EVT OpVT,EVT RetVT)220 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
221 if (OpVT == MVT::f16) {
222 if (RetVT == MVT::f32)
223 return FPEXT_F16_F32;
224 } else if (OpVT == MVT::f32) {
225 if (RetVT == MVT::f64)
226 return FPEXT_F32_F64;
227 if (RetVT == MVT::f128)
228 return FPEXT_F32_F128;
229 if (RetVT == MVT::ppcf128)
230 return FPEXT_F32_PPCF128;
231 } else if (OpVT == MVT::f64) {
232 if (RetVT == MVT::f128)
233 return FPEXT_F64_F128;
234 else if (RetVT == MVT::ppcf128)
235 return FPEXT_F64_PPCF128;
236 } else if (OpVT == MVT::f80) {
237 if (RetVT == MVT::f128)
238 return FPEXT_F80_F128;
239 }
240
241 return UNKNOWN_LIBCALL;
242 }
243
244 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
245 /// UNKNOWN_LIBCALL if there is none.
getFPROUND(EVT OpVT,EVT RetVT)246 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
247 if (RetVT == MVT::f16) {
248 if (OpVT == MVT::f32)
249 return FPROUND_F32_F16;
250 if (OpVT == MVT::f64)
251 return FPROUND_F64_F16;
252 if (OpVT == MVT::f80)
253 return FPROUND_F80_F16;
254 if (OpVT == MVT::f128)
255 return FPROUND_F128_F16;
256 if (OpVT == MVT::ppcf128)
257 return FPROUND_PPCF128_F16;
258 } else if (RetVT == MVT::f32) {
259 if (OpVT == MVT::f64)
260 return FPROUND_F64_F32;
261 if (OpVT == MVT::f80)
262 return FPROUND_F80_F32;
263 if (OpVT == MVT::f128)
264 return FPROUND_F128_F32;
265 if (OpVT == MVT::ppcf128)
266 return FPROUND_PPCF128_F32;
267 } else if (RetVT == MVT::f64) {
268 if (OpVT == MVT::f80)
269 return FPROUND_F80_F64;
270 if (OpVT == MVT::f128)
271 return FPROUND_F128_F64;
272 if (OpVT == MVT::ppcf128)
273 return FPROUND_PPCF128_F64;
274 } else if (RetVT == MVT::f80) {
275 if (OpVT == MVT::f128)
276 return FPROUND_F128_F80;
277 }
278
279 return UNKNOWN_LIBCALL;
280 }
281
282 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
283 /// UNKNOWN_LIBCALL if there is none.
getFPTOSINT(EVT OpVT,EVT RetVT)284 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
285 if (OpVT == MVT::f32) {
286 if (RetVT == MVT::i32)
287 return FPTOSINT_F32_I32;
288 if (RetVT == MVT::i64)
289 return FPTOSINT_F32_I64;
290 if (RetVT == MVT::i128)
291 return FPTOSINT_F32_I128;
292 } else if (OpVT == MVT::f64) {
293 if (RetVT == MVT::i32)
294 return FPTOSINT_F64_I32;
295 if (RetVT == MVT::i64)
296 return FPTOSINT_F64_I64;
297 if (RetVT == MVT::i128)
298 return FPTOSINT_F64_I128;
299 } else if (OpVT == MVT::f80) {
300 if (RetVT == MVT::i32)
301 return FPTOSINT_F80_I32;
302 if (RetVT == MVT::i64)
303 return FPTOSINT_F80_I64;
304 if (RetVT == MVT::i128)
305 return FPTOSINT_F80_I128;
306 } else if (OpVT == MVT::f128) {
307 if (RetVT == MVT::i32)
308 return FPTOSINT_F128_I32;
309 if (RetVT == MVT::i64)
310 return FPTOSINT_F128_I64;
311 if (RetVT == MVT::i128)
312 return FPTOSINT_F128_I128;
313 } else if (OpVT == MVT::ppcf128) {
314 if (RetVT == MVT::i32)
315 return FPTOSINT_PPCF128_I32;
316 if (RetVT == MVT::i64)
317 return FPTOSINT_PPCF128_I64;
318 if (RetVT == MVT::i128)
319 return FPTOSINT_PPCF128_I128;
320 }
321 return UNKNOWN_LIBCALL;
322 }
323
324 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
325 /// UNKNOWN_LIBCALL if there is none.
getFPTOUINT(EVT OpVT,EVT RetVT)326 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
327 if (OpVT == MVT::f32) {
328 if (RetVT == MVT::i32)
329 return FPTOUINT_F32_I32;
330 if (RetVT == MVT::i64)
331 return FPTOUINT_F32_I64;
332 if (RetVT == MVT::i128)
333 return FPTOUINT_F32_I128;
334 } else if (OpVT == MVT::f64) {
335 if (RetVT == MVT::i32)
336 return FPTOUINT_F64_I32;
337 if (RetVT == MVT::i64)
338 return FPTOUINT_F64_I64;
339 if (RetVT == MVT::i128)
340 return FPTOUINT_F64_I128;
341 } else if (OpVT == MVT::f80) {
342 if (RetVT == MVT::i32)
343 return FPTOUINT_F80_I32;
344 if (RetVT == MVT::i64)
345 return FPTOUINT_F80_I64;
346 if (RetVT == MVT::i128)
347 return FPTOUINT_F80_I128;
348 } else if (OpVT == MVT::f128) {
349 if (RetVT == MVT::i32)
350 return FPTOUINT_F128_I32;
351 if (RetVT == MVT::i64)
352 return FPTOUINT_F128_I64;
353 if (RetVT == MVT::i128)
354 return FPTOUINT_F128_I128;
355 } else if (OpVT == MVT::ppcf128) {
356 if (RetVT == MVT::i32)
357 return FPTOUINT_PPCF128_I32;
358 if (RetVT == MVT::i64)
359 return FPTOUINT_PPCF128_I64;
360 if (RetVT == MVT::i128)
361 return FPTOUINT_PPCF128_I128;
362 }
363 return UNKNOWN_LIBCALL;
364 }
365
366 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
367 /// UNKNOWN_LIBCALL if there is none.
getSINTTOFP(EVT OpVT,EVT RetVT)368 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
369 if (OpVT == MVT::i32) {
370 if (RetVT == MVT::f32)
371 return SINTTOFP_I32_F32;
372 if (RetVT == MVT::f64)
373 return SINTTOFP_I32_F64;
374 if (RetVT == MVT::f80)
375 return SINTTOFP_I32_F80;
376 if (RetVT == MVT::f128)
377 return SINTTOFP_I32_F128;
378 if (RetVT == MVT::ppcf128)
379 return SINTTOFP_I32_PPCF128;
380 } else if (OpVT == MVT::i64) {
381 if (RetVT == MVT::f32)
382 return SINTTOFP_I64_F32;
383 if (RetVT == MVT::f64)
384 return SINTTOFP_I64_F64;
385 if (RetVT == MVT::f80)
386 return SINTTOFP_I64_F80;
387 if (RetVT == MVT::f128)
388 return SINTTOFP_I64_F128;
389 if (RetVT == MVT::ppcf128)
390 return SINTTOFP_I64_PPCF128;
391 } else if (OpVT == MVT::i128) {
392 if (RetVT == MVT::f32)
393 return SINTTOFP_I128_F32;
394 if (RetVT == MVT::f64)
395 return SINTTOFP_I128_F64;
396 if (RetVT == MVT::f80)
397 return SINTTOFP_I128_F80;
398 if (RetVT == MVT::f128)
399 return SINTTOFP_I128_F128;
400 if (RetVT == MVT::ppcf128)
401 return SINTTOFP_I128_PPCF128;
402 }
403 return UNKNOWN_LIBCALL;
404 }
405
406 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
407 /// UNKNOWN_LIBCALL if there is none.
getUINTTOFP(EVT OpVT,EVT RetVT)408 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
409 if (OpVT == MVT::i32) {
410 if (RetVT == MVT::f32)
411 return UINTTOFP_I32_F32;
412 if (RetVT == MVT::f64)
413 return UINTTOFP_I32_F64;
414 if (RetVT == MVT::f80)
415 return UINTTOFP_I32_F80;
416 if (RetVT == MVT::f128)
417 return UINTTOFP_I32_F128;
418 if (RetVT == MVT::ppcf128)
419 return UINTTOFP_I32_PPCF128;
420 } else if (OpVT == MVT::i64) {
421 if (RetVT == MVT::f32)
422 return UINTTOFP_I64_F32;
423 if (RetVT == MVT::f64)
424 return UINTTOFP_I64_F64;
425 if (RetVT == MVT::f80)
426 return UINTTOFP_I64_F80;
427 if (RetVT == MVT::f128)
428 return UINTTOFP_I64_F128;
429 if (RetVT == MVT::ppcf128)
430 return UINTTOFP_I64_PPCF128;
431 } else if (OpVT == MVT::i128) {
432 if (RetVT == MVT::f32)
433 return UINTTOFP_I128_F32;
434 if (RetVT == MVT::f64)
435 return UINTTOFP_I128_F64;
436 if (RetVT == MVT::f80)
437 return UINTTOFP_I128_F80;
438 if (RetVT == MVT::f128)
439 return UINTTOFP_I128_F128;
440 if (RetVT == MVT::ppcf128)
441 return UINTTOFP_I128_PPCF128;
442 }
443 return UNKNOWN_LIBCALL;
444 }
445
getSYNC(unsigned Opc,MVT VT)446 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
447 #define OP_TO_LIBCALL(Name, Enum) \
448 case Name: \
449 switch (VT.SimpleTy) { \
450 default: \
451 return UNKNOWN_LIBCALL; \
452 case MVT::i8: \
453 return Enum##_1; \
454 case MVT::i16: \
455 return Enum##_2; \
456 case MVT::i32: \
457 return Enum##_4; \
458 case MVT::i64: \
459 return Enum##_8; \
460 case MVT::i128: \
461 return Enum##_16; \
462 }
463
464 switch (Opc) {
465 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
466 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
467 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
468 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
469 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
470 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
471 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
472 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
473 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
474 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
475 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
476 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
477 }
478
479 #undef OP_TO_LIBCALL
480
481 return UNKNOWN_LIBCALL;
482 }
483
getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)484 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
485 switch (ElementSize) {
486 case 1:
487 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
488 case 2:
489 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
490 case 4:
491 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
492 case 8:
493 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
494 case 16:
495 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
496 default:
497 return UNKNOWN_LIBCALL;
498 }
499 }
500
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)501 RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
502 switch (ElementSize) {
503 case 1:
504 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
505 case 2:
506 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
507 case 4:
508 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
509 case 8:
510 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
511 case 16:
512 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
513 default:
514 return UNKNOWN_LIBCALL;
515 }
516 }
517
getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)518 RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
519 switch (ElementSize) {
520 case 1:
521 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
522 case 2:
523 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
524 case 4:
525 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
526 case 8:
527 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
528 case 16:
529 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
530 default:
531 return UNKNOWN_LIBCALL;
532 }
533 }
534
535 /// InitCmpLibcallCCs - Set default comparison libcall CC.
InitCmpLibcallCCs(ISD::CondCode * CCs)536 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
537 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
538 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
539 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
540 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
541 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
542 CCs[RTLIB::UNE_F32] = ISD::SETNE;
543 CCs[RTLIB::UNE_F64] = ISD::SETNE;
544 CCs[RTLIB::UNE_F128] = ISD::SETNE;
545 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
546 CCs[RTLIB::OGE_F32] = ISD::SETGE;
547 CCs[RTLIB::OGE_F64] = ISD::SETGE;
548 CCs[RTLIB::OGE_F128] = ISD::SETGE;
549 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
550 CCs[RTLIB::OLT_F32] = ISD::SETLT;
551 CCs[RTLIB::OLT_F64] = ISD::SETLT;
552 CCs[RTLIB::OLT_F128] = ISD::SETLT;
553 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
554 CCs[RTLIB::OLE_F32] = ISD::SETLE;
555 CCs[RTLIB::OLE_F64] = ISD::SETLE;
556 CCs[RTLIB::OLE_F128] = ISD::SETLE;
557 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
558 CCs[RTLIB::OGT_F32] = ISD::SETGT;
559 CCs[RTLIB::OGT_F64] = ISD::SETGT;
560 CCs[RTLIB::OGT_F128] = ISD::SETGT;
561 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
562 CCs[RTLIB::UO_F32] = ISD::SETNE;
563 CCs[RTLIB::UO_F64] = ISD::SETNE;
564 CCs[RTLIB::UO_F128] = ISD::SETNE;
565 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
566 }
567
568 /// NOTE: The TargetMachine owns TLOF.
TargetLoweringBase(const TargetMachine & tm)569 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
570 initActions();
571
572 // Perform these initializations only once.
573 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
574 MaxLoadsPerMemcmp = 8;
575 MaxGluedStoresPerMemcpy = 0;
576 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
577 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
578 HasMultipleConditionRegisters = false;
579 HasExtractBitsInsn = false;
580 JumpIsExpensive = JumpIsExpensiveOverride;
581 PredictableSelectIsExpensive = false;
582 EnableExtLdPromotion = false;
583 StackPointerRegisterToSaveRestore = 0;
584 BooleanContents = UndefinedBooleanContent;
585 BooleanFloatContents = UndefinedBooleanContent;
586 BooleanVectorContents = UndefinedBooleanContent;
587 SchedPreferenceInfo = Sched::ILP;
588 GatherAllAliasesMaxDepth = 18;
589 IsStrictFPEnabled = DisableStrictNodeMutation;
590 // TODO: the default will be switched to 0 in the next commit, along
591 // with the Target-specific changes necessary.
592 MaxAtomicSizeInBitsSupported = 1024;
593
594 MinCmpXchgSizeInBits = 0;
595 SupportsUnalignedAtomics = false;
596
597 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
598
599 InitLibcalls(TM.getTargetTriple());
600 InitCmpLibcallCCs(CmpLibcallCCs);
601 }
602
initActions()603 void TargetLoweringBase::initActions() {
604 // All operations default to being supported.
605 memset(OpActions, 0, sizeof(OpActions));
606 memset(LoadExtActions, 0, sizeof(LoadExtActions));
607 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
608 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
609 memset(CondCodeActions, 0, sizeof(CondCodeActions));
610 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
611 std::fill(std::begin(TargetDAGCombineArray),
612 std::end(TargetDAGCombineArray), 0);
613
614 for (MVT VT : MVT::fp_valuetypes()) {
615 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
616 if (IntVT.isValid()) {
617 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote);
618 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT);
619 }
620 }
621
622 // Set default actions for various operations.
623 for (MVT VT : MVT::all_valuetypes()) {
624 // Default all indexed load / store to expand.
625 for (unsigned IM = (unsigned)ISD::PRE_INC;
626 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
627 setIndexedLoadAction(IM, VT, Expand);
628 setIndexedStoreAction(IM, VT, Expand);
629 setIndexedMaskedLoadAction(IM, VT, Expand);
630 setIndexedMaskedStoreAction(IM, VT, Expand);
631 }
632
633 // Most backends expect to see the node which just returns the value loaded.
634 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
635
636 // These operations default to expand.
637 setOperationAction(ISD::FGETSIGN, VT, Expand);
638 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
639 setOperationAction(ISD::FMINNUM, VT, Expand);
640 setOperationAction(ISD::FMAXNUM, VT, Expand);
641 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand);
642 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand);
643 setOperationAction(ISD::FMINIMUM, VT, Expand);
644 setOperationAction(ISD::FMAXIMUM, VT, Expand);
645 setOperationAction(ISD::FMAD, VT, Expand);
646 setOperationAction(ISD::SMIN, VT, Expand);
647 setOperationAction(ISD::SMAX, VT, Expand);
648 setOperationAction(ISD::UMIN, VT, Expand);
649 setOperationAction(ISD::UMAX, VT, Expand);
650 setOperationAction(ISD::ABS, VT, Expand);
651 setOperationAction(ISD::FSHL, VT, Expand);
652 setOperationAction(ISD::FSHR, VT, Expand);
653 setOperationAction(ISD::SADDSAT, VT, Expand);
654 setOperationAction(ISD::UADDSAT, VT, Expand);
655 setOperationAction(ISD::SSUBSAT, VT, Expand);
656 setOperationAction(ISD::USUBSAT, VT, Expand);
657 setOperationAction(ISD::SMULFIX, VT, Expand);
658 setOperationAction(ISD::SMULFIXSAT, VT, Expand);
659 setOperationAction(ISD::UMULFIX, VT, Expand);
660 setOperationAction(ISD::UMULFIXSAT, VT, Expand);
661 setOperationAction(ISD::SDIVFIX, VT, Expand);
662 setOperationAction(ISD::UDIVFIX, VT, Expand);
663
664 // Overflow operations default to expand
665 setOperationAction(ISD::SADDO, VT, Expand);
666 setOperationAction(ISD::SSUBO, VT, Expand);
667 setOperationAction(ISD::UADDO, VT, Expand);
668 setOperationAction(ISD::USUBO, VT, Expand);
669 setOperationAction(ISD::SMULO, VT, Expand);
670 setOperationAction(ISD::UMULO, VT, Expand);
671
672 // ADDCARRY operations default to expand
673 setOperationAction(ISD::ADDCARRY, VT, Expand);
674 setOperationAction(ISD::SUBCARRY, VT, Expand);
675 setOperationAction(ISD::SETCCCARRY, VT, Expand);
676
677 // ADDC/ADDE/SUBC/SUBE default to expand.
678 setOperationAction(ISD::ADDC, VT, Expand);
679 setOperationAction(ISD::ADDE, VT, Expand);
680 setOperationAction(ISD::SUBC, VT, Expand);
681 setOperationAction(ISD::SUBE, VT, Expand);
682
683 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
684 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
685 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
686
687 setOperationAction(ISD::BITREVERSE, VT, Expand);
688
689 // These library functions default to expand.
690 setOperationAction(ISD::FROUND, VT, Expand);
691 setOperationAction(ISD::FPOWI, VT, Expand);
692
693 // These operations default to expand for vector types.
694 if (VT.isVector()) {
695 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
696 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
697 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
698 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
699 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
700 setOperationAction(ISD::SPLAT_VECTOR, VT, Expand);
701 }
702
703 // Constrained floating-point operations default to expand.
704 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
705 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
706 #include "llvm/IR/ConstrainedOps.def"
707
708 // For most targets @llvm.get.dynamic.area.offset just returns 0.
709 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
710
711 // Vector reduction default to expand.
712 setOperationAction(ISD::VECREDUCE_FADD, VT, Expand);
713 setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand);
714 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand);
715 setOperationAction(ISD::VECREDUCE_MUL, VT, Expand);
716 setOperationAction(ISD::VECREDUCE_AND, VT, Expand);
717 setOperationAction(ISD::VECREDUCE_OR, VT, Expand);
718 setOperationAction(ISD::VECREDUCE_XOR, VT, Expand);
719 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand);
720 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand);
721 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand);
722 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand);
723 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand);
724 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand);
725 }
726
727 // Most targets ignore the @llvm.prefetch intrinsic.
728 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
729
730 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
731 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
732
733 // ConstantFP nodes default to expand. Targets can either change this to
734 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
735 // to optimize expansions for certain constants.
736 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
737 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
738 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
739 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
740 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
741
742 // These library functions default to expand.
743 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
744 setOperationAction(ISD::FCBRT, VT, Expand);
745 setOperationAction(ISD::FLOG , VT, Expand);
746 setOperationAction(ISD::FLOG2, VT, Expand);
747 setOperationAction(ISD::FLOG10, VT, Expand);
748 setOperationAction(ISD::FEXP , VT, Expand);
749 setOperationAction(ISD::FEXP2, VT, Expand);
750 setOperationAction(ISD::FFLOOR, VT, Expand);
751 setOperationAction(ISD::FNEARBYINT, VT, Expand);
752 setOperationAction(ISD::FCEIL, VT, Expand);
753 setOperationAction(ISD::FRINT, VT, Expand);
754 setOperationAction(ISD::FTRUNC, VT, Expand);
755 setOperationAction(ISD::FROUND, VT, Expand);
756 setOperationAction(ISD::LROUND, VT, Expand);
757 setOperationAction(ISD::LLROUND, VT, Expand);
758 setOperationAction(ISD::LRINT, VT, Expand);
759 setOperationAction(ISD::LLRINT, VT, Expand);
760 }
761
762 // Default ISD::TRAP to expand (which turns it into abort).
763 setOperationAction(ISD::TRAP, MVT::Other, Expand);
764
765 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
766 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
767 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
768 }
769
getScalarShiftAmountTy(const DataLayout & DL,EVT) const770 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
771 EVT) const {
772 return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
773 }
774
getShiftAmountTy(EVT LHSTy,const DataLayout & DL,bool LegalTypes) const775 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
776 bool LegalTypes) const {
777 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
778 if (LHSTy.isVector())
779 return LHSTy;
780 return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
781 : getPointerTy(DL);
782 }
783
canOpTrap(unsigned Op,EVT VT) const784 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
785 assert(isTypeLegal(VT));
786 switch (Op) {
787 default:
788 return false;
789 case ISD::SDIV:
790 case ISD::UDIV:
791 case ISD::SREM:
792 case ISD::UREM:
793 return true;
794 }
795 }
796
setJumpIsExpensive(bool isExpensive)797 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
798 // If the command-line option was specified, ignore this request.
799 if (!JumpIsExpensiveOverride.getNumOccurrences())
800 JumpIsExpensive = isExpensive;
801 }
802
803 TargetLoweringBase::LegalizeKind
getTypeConversion(LLVMContext & Context,EVT VT) const804 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
805 // If this is a simple type, use the ComputeRegisterProp mechanism.
806 if (VT.isSimple()) {
807 MVT SVT = VT.getSimpleVT();
808 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
809 MVT NVT = TransformToType[SVT.SimpleTy];
810 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
811
812 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
813 (NVT.isVector() ||
814 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
815 "Promote may not follow Expand or Promote");
816
817 if (LA == TypeSplitVector)
818 return LegalizeKind(LA,
819 EVT::getVectorVT(Context, SVT.getVectorElementType(),
820 SVT.getVectorNumElements() / 2));
821 if (LA == TypeScalarizeVector)
822 return LegalizeKind(LA, SVT.getVectorElementType());
823 return LegalizeKind(LA, NVT);
824 }
825
826 // Handle Extended Scalar Types.
827 if (!VT.isVector()) {
828 assert(VT.isInteger() && "Float types must be simple");
829 unsigned BitSize = VT.getSizeInBits();
830 // First promote to a power-of-two size, then expand if necessary.
831 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
832 EVT NVT = VT.getRoundIntegerType(Context);
833 assert(NVT != VT && "Unable to round integer VT");
834 LegalizeKind NextStep = getTypeConversion(Context, NVT);
835 // Avoid multi-step promotion.
836 if (NextStep.first == TypePromoteInteger)
837 return NextStep;
838 // Return rounded integer type.
839 return LegalizeKind(TypePromoteInteger, NVT);
840 }
841
842 return LegalizeKind(TypeExpandInteger,
843 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
844 }
845
846 // Handle vector types.
847 unsigned NumElts = VT.getVectorNumElements();
848 EVT EltVT = VT.getVectorElementType();
849
850 // Vectors with only one element are always scalarized.
851 if (NumElts == 1)
852 return LegalizeKind(TypeScalarizeVector, EltVT);
853
854 // Try to widen vector elements until the element type is a power of two and
855 // promote it to a legal type later on, for example:
856 // <3 x i8> -> <4 x i8> -> <4 x i32>
857 if (EltVT.isInteger()) {
858 // Vectors with a number of elements that is not a power of two are always
859 // widened, for example <3 x i8> -> <4 x i8>.
860 if (!VT.isPow2VectorType()) {
861 NumElts = (unsigned)NextPowerOf2(NumElts);
862 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
863 return LegalizeKind(TypeWidenVector, NVT);
864 }
865
866 // Examine the element type.
867 LegalizeKind LK = getTypeConversion(Context, EltVT);
868
869 // If type is to be expanded, split the vector.
870 // <4 x i140> -> <2 x i140>
871 if (LK.first == TypeExpandInteger)
872 return LegalizeKind(TypeSplitVector,
873 EVT::getVectorVT(Context, EltVT, NumElts / 2));
874
875 // Promote the integer element types until a legal vector type is found
876 // or until the element integer type is too big. If a legal type was not
877 // found, fallback to the usual mechanism of widening/splitting the
878 // vector.
879 EVT OldEltVT = EltVT;
880 while (true) {
881 // Increase the bitwidth of the element to the next pow-of-two
882 // (which is greater than 8 bits).
883 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
884 .getRoundIntegerType(Context);
885
886 // Stop trying when getting a non-simple element type.
887 // Note that vector elements may be greater than legal vector element
888 // types. Example: X86 XMM registers hold 64bit element on 32bit
889 // systems.
890 if (!EltVT.isSimple())
891 break;
892
893 // Build a new vector type and check if it is legal.
894 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
895 // Found a legal promoted vector type.
896 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
897 return LegalizeKind(TypePromoteInteger,
898 EVT::getVectorVT(Context, EltVT, NumElts));
899 }
900
901 // Reset the type to the unexpanded type if we did not find a legal vector
902 // type with a promoted vector element type.
903 EltVT = OldEltVT;
904 }
905
906 // Try to widen the vector until a legal type is found.
907 // If there is no wider legal type, split the vector.
908 while (true) {
909 // Round up to the next power of 2.
910 NumElts = (unsigned)NextPowerOf2(NumElts);
911
912 // If there is no simple vector type with this many elements then there
913 // cannot be a larger legal vector type. Note that this assumes that
914 // there are no skipped intermediate vector types in the simple types.
915 if (!EltVT.isSimple())
916 break;
917 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
918 if (LargerVector == MVT())
919 break;
920
921 // If this type is legal then widen the vector.
922 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
923 return LegalizeKind(TypeWidenVector, LargerVector);
924 }
925
926 // Widen odd vectors to next power of two.
927 if (!VT.isPow2VectorType()) {
928 EVT NVT = VT.getPow2VectorType(Context);
929 return LegalizeKind(TypeWidenVector, NVT);
930 }
931
932 // Vectors with illegal element types are expanded.
933 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
934 return LegalizeKind(TypeSplitVector, NVT);
935 }
936
getVectorTypeBreakdownMVT(MVT VT,MVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT,TargetLoweringBase * TLI)937 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
938 unsigned &NumIntermediates,
939 MVT &RegisterVT,
940 TargetLoweringBase *TLI) {
941 // Figure out the right, legal destination reg to copy into.
942 unsigned NumElts = VT.getVectorNumElements();
943 MVT EltTy = VT.getVectorElementType();
944
945 unsigned NumVectorRegs = 1;
946
947 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
948 // could break down into LHS/RHS like LegalizeDAG does.
949 if (!isPowerOf2_32(NumElts)) {
950 NumVectorRegs = NumElts;
951 NumElts = 1;
952 }
953
954 // Divide the input until we get to a supported size. This will always
955 // end with a scalar if the target doesn't support vectors.
956 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
957 NumElts >>= 1;
958 NumVectorRegs <<= 1;
959 }
960
961 NumIntermediates = NumVectorRegs;
962
963 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
964 if (!TLI->isTypeLegal(NewVT))
965 NewVT = EltTy;
966 IntermediateVT = NewVT;
967
968 unsigned NewVTSize = NewVT.getSizeInBits();
969
970 // Convert sizes such as i33 to i64.
971 if (!isPowerOf2_32(NewVTSize))
972 NewVTSize = NextPowerOf2(NewVTSize);
973
974 MVT DestVT = TLI->getRegisterType(NewVT);
975 RegisterVT = DestVT;
976 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
977 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
978
979 // Otherwise, promotion or legal types use the same number of registers as
980 // the vector decimated to the appropriate level.
981 return NumVectorRegs;
982 }
983
984 /// isLegalRC - Return true if the value types that can be represented by the
985 /// specified register class are all legal.
isLegalRC(const TargetRegisterInfo & TRI,const TargetRegisterClass & RC) const986 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
987 const TargetRegisterClass &RC) const {
988 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
989 if (isTypeLegal(*I))
990 return true;
991 return false;
992 }
993
994 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
995 /// sequence of memory operands that is recognized by PrologEpilogInserter.
996 MachineBasicBlock *
emitPatchPoint(MachineInstr & InitialMI,MachineBasicBlock * MBB) const997 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
998 MachineBasicBlock *MBB) const {
999 MachineInstr *MI = &InitialMI;
1000 MachineFunction &MF = *MI->getMF();
1001 MachineFrameInfo &MFI = MF.getFrameInfo();
1002
1003 // We're handling multiple types of operands here:
1004 // PATCHPOINT MetaArgs - live-in, read only, direct
1005 // STATEPOINT Deopt Spill - live-through, read only, indirect
1006 // STATEPOINT Deopt Alloca - live-through, read only, direct
1007 // (We're currently conservative and mark the deopt slots read/write in
1008 // practice.)
1009 // STATEPOINT GC Spill - live-through, read/write, indirect
1010 // STATEPOINT GC Alloca - live-through, read/write, direct
1011 // The live-in vs live-through is handled already (the live through ones are
1012 // all stack slots), but we need to handle the different type of stackmap
1013 // operands and memory effects here.
1014
1015 // MI changes inside this loop as we grow operands.
1016 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1017 MachineOperand &MO = MI->getOperand(OperIdx);
1018 if (!MO.isFI())
1019 continue;
1020
1021 // foldMemoryOperand builds a new MI after replacing a single FI operand
1022 // with the canonical set of five x86 addressing-mode operands.
1023 int FI = MO.getIndex();
1024 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1025
1026 // Copy operands before the frame-index.
1027 for (unsigned i = 0; i < OperIdx; ++i)
1028 MIB.add(MI->getOperand(i));
1029 // Add frame index operands recognized by stackmaps.cpp
1030 if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1031 // indirect-mem-ref tag, size, #FI, offset.
1032 // Used for spills inserted by StatepointLowering. This codepath is not
1033 // used for patchpoints/stackmaps at all, for these spilling is done via
1034 // foldMemoryOperand callback only.
1035 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1036 MIB.addImm(StackMaps::IndirectMemRefOp);
1037 MIB.addImm(MFI.getObjectSize(FI));
1038 MIB.add(MI->getOperand(OperIdx));
1039 MIB.addImm(0);
1040 } else {
1041 // direct-mem-ref tag, #FI, offset.
1042 // Used by patchpoint, and direct alloca arguments to statepoints
1043 MIB.addImm(StackMaps::DirectMemRefOp);
1044 MIB.add(MI->getOperand(OperIdx));
1045 MIB.addImm(0);
1046 }
1047 // Copy the operands after the frame index.
1048 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1049 MIB.add(MI->getOperand(i));
1050
1051 // Inherit previous memory operands.
1052 MIB.cloneMemRefs(*MI);
1053 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1054
1055 // Add a new memory operand for this FI.
1056 assert(MFI.getObjectOffset(FI) != -1);
1057
1058 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1059 // PATCHPOINT should be updated to do the same. (TODO)
1060 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1061 auto Flags = MachineMemOperand::MOLoad;
1062 MachineMemOperand *MMO = MF.getMachineMemOperand(
1063 MachinePointerInfo::getFixedStack(MF, FI), Flags,
1064 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
1065 MIB->addMemOperand(MF, MMO);
1066 }
1067
1068 // Replace the instruction and update the operand index.
1069 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1070 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1071 MI->eraseFromParent();
1072 MI = MIB;
1073 }
1074 return MBB;
1075 }
1076
1077 MachineBasicBlock *
emitXRayCustomEvent(MachineInstr & MI,MachineBasicBlock * MBB) const1078 TargetLoweringBase::emitXRayCustomEvent(MachineInstr &MI,
1079 MachineBasicBlock *MBB) const {
1080 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1081 "Called emitXRayCustomEvent on the wrong MI!");
1082 auto &MF = *MI.getMF();
1083 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1084 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1085 MIB.add(MI.getOperand(OpIdx));
1086
1087 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1088 MI.eraseFromParent();
1089 return MBB;
1090 }
1091
1092 MachineBasicBlock *
emitXRayTypedEvent(MachineInstr & MI,MachineBasicBlock * MBB) const1093 TargetLoweringBase::emitXRayTypedEvent(MachineInstr &MI,
1094 MachineBasicBlock *MBB) const {
1095 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1096 "Called emitXRayTypedEvent on the wrong MI!");
1097 auto &MF = *MI.getMF();
1098 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1099 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1100 MIB.add(MI.getOperand(OpIdx));
1101
1102 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1103 MI.eraseFromParent();
1104 return MBB;
1105 }
1106
1107 /// findRepresentativeClass - Return the largest legal super-reg register class
1108 /// of the register class for the specified type and its associated "cost".
1109 // This function is in TargetLowering because it uses RegClassForVT which would
1110 // need to be moved to TargetRegisterInfo and would necessitate moving
1111 // isTypeLegal over as well - a massive change that would just require
1112 // TargetLowering having a TargetRegisterInfo class member that it would use.
1113 std::pair<const TargetRegisterClass *, uint8_t>
findRepresentativeClass(const TargetRegisterInfo * TRI,MVT VT) const1114 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1115 MVT VT) const {
1116 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1117 if (!RC)
1118 return std::make_pair(RC, 0);
1119
1120 // Compute the set of all super-register classes.
1121 BitVector SuperRegRC(TRI->getNumRegClasses());
1122 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1123 SuperRegRC.setBitsInMask(RCI.getMask());
1124
1125 // Find the first legal register class with the largest spill size.
1126 const TargetRegisterClass *BestRC = RC;
1127 for (unsigned i : SuperRegRC.set_bits()) {
1128 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1129 // We want the largest possible spill size.
1130 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1131 continue;
1132 if (!isLegalRC(*TRI, *SuperRC))
1133 continue;
1134 BestRC = SuperRC;
1135 }
1136 return std::make_pair(BestRC, 1);
1137 }
1138
1139 /// computeRegisterProperties - Once all of the register classes are added,
1140 /// this allows us to compute derived properties we expose.
computeRegisterProperties(const TargetRegisterInfo * TRI)1141 void TargetLoweringBase::computeRegisterProperties(
1142 const TargetRegisterInfo *TRI) {
1143 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1144 "Too many value types for ValueTypeActions to hold!");
1145
1146 // Everything defaults to needing one register.
1147 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1148 NumRegistersForVT[i] = 1;
1149 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1150 }
1151 // ...except isVoid, which doesn't need any registers.
1152 NumRegistersForVT[MVT::isVoid] = 0;
1153
1154 // Find the largest integer register class.
1155 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1156 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1157 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1158
1159 // Every integer value type larger than this largest register takes twice as
1160 // many registers to represent as the previous ValueType.
1161 for (unsigned ExpandedReg = LargestIntReg + 1;
1162 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1163 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1164 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1165 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1166 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1167 TypeExpandInteger);
1168 }
1169
1170 // Inspect all of the ValueType's smaller than the largest integer
1171 // register to see which ones need promotion.
1172 unsigned LegalIntReg = LargestIntReg;
1173 for (unsigned IntReg = LargestIntReg - 1;
1174 IntReg >= (unsigned)MVT::i1; --IntReg) {
1175 MVT IVT = (MVT::SimpleValueType)IntReg;
1176 if (isTypeLegal(IVT)) {
1177 LegalIntReg = IntReg;
1178 } else {
1179 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1180 (MVT::SimpleValueType)LegalIntReg;
1181 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1182 }
1183 }
1184
1185 // ppcf128 type is really two f64's.
1186 if (!isTypeLegal(MVT::ppcf128)) {
1187 if (isTypeLegal(MVT::f64)) {
1188 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1189 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1190 TransformToType[MVT::ppcf128] = MVT::f64;
1191 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1192 } else {
1193 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1194 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1195 TransformToType[MVT::ppcf128] = MVT::i128;
1196 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1197 }
1198 }
1199
1200 // Decide how to handle f128. If the target does not have native f128 support,
1201 // expand it to i128 and we will be generating soft float library calls.
1202 if (!isTypeLegal(MVT::f128)) {
1203 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1204 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1205 TransformToType[MVT::f128] = MVT::i128;
1206 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1207 }
1208
1209 // Decide how to handle f64. If the target does not have native f64 support,
1210 // expand it to i64 and we will be generating soft float library calls.
1211 if (!isTypeLegal(MVT::f64)) {
1212 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1213 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1214 TransformToType[MVT::f64] = MVT::i64;
1215 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1216 }
1217
1218 // Decide how to handle f32. If the target does not have native f32 support,
1219 // expand it to i32 and we will be generating soft float library calls.
1220 if (!isTypeLegal(MVT::f32)) {
1221 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1222 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1223 TransformToType[MVT::f32] = MVT::i32;
1224 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1225 }
1226
1227 // Decide how to handle f16. If the target does not have native f16 support,
1228 // promote it to f32, because there are no f16 library calls (except for
1229 // conversions).
1230 if (!isTypeLegal(MVT::f16)) {
1231 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1232 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1233 TransformToType[MVT::f16] = MVT::f32;
1234 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1235 }
1236
1237 // Loop over all of the vector value types to see which need transformations.
1238 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1239 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1240 MVT VT = (MVT::SimpleValueType) i;
1241 if (isTypeLegal(VT))
1242 continue;
1243
1244 MVT EltVT = VT.getVectorElementType();
1245 unsigned NElts = VT.getVectorNumElements();
1246 bool IsLegalWiderType = false;
1247 bool IsScalable = VT.isScalableVector();
1248 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1249 switch (PreferredAction) {
1250 case TypePromoteInteger: {
1251 MVT::SimpleValueType EndVT = IsScalable ?
1252 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1253 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1254 // Try to promote the elements of integer vectors. If no legal
1255 // promotion was found, fall through to the widen-vector method.
1256 for (unsigned nVT = i + 1;
1257 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1258 MVT SVT = (MVT::SimpleValueType) nVT;
1259 // Promote vectors of integers to vectors with the same number
1260 // of elements, with a wider element type.
1261 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1262 SVT.getVectorNumElements() == NElts &&
1263 SVT.isScalableVector() == IsScalable && isTypeLegal(SVT)) {
1264 TransformToType[i] = SVT;
1265 RegisterTypeForVT[i] = SVT;
1266 NumRegistersForVT[i] = 1;
1267 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1268 IsLegalWiderType = true;
1269 break;
1270 }
1271 }
1272 if (IsLegalWiderType)
1273 break;
1274 LLVM_FALLTHROUGH;
1275 }
1276
1277 case TypeWidenVector:
1278 if (isPowerOf2_32(NElts)) {
1279 // Try to widen the vector.
1280 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1281 MVT SVT = (MVT::SimpleValueType) nVT;
1282 if (SVT.getVectorElementType() == EltVT
1283 && SVT.getVectorNumElements() > NElts
1284 && SVT.isScalableVector() == IsScalable && isTypeLegal(SVT)) {
1285 TransformToType[i] = SVT;
1286 RegisterTypeForVT[i] = SVT;
1287 NumRegistersForVT[i] = 1;
1288 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1289 IsLegalWiderType = true;
1290 break;
1291 }
1292 }
1293 if (IsLegalWiderType)
1294 break;
1295 } else {
1296 // Only widen to the next power of 2 to keep consistency with EVT.
1297 MVT NVT = VT.getPow2VectorType();
1298 if (isTypeLegal(NVT)) {
1299 TransformToType[i] = NVT;
1300 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1301 RegisterTypeForVT[i] = NVT;
1302 NumRegistersForVT[i] = 1;
1303 break;
1304 }
1305 }
1306 LLVM_FALLTHROUGH;
1307
1308 case TypeSplitVector:
1309 case TypeScalarizeVector: {
1310 MVT IntermediateVT;
1311 MVT RegisterVT;
1312 unsigned NumIntermediates;
1313 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1314 NumIntermediates, RegisterVT, this);
1315 NumRegistersForVT[i] = NumRegisters;
1316 assert(NumRegistersForVT[i] == NumRegisters &&
1317 "NumRegistersForVT size cannot represent NumRegisters!");
1318 RegisterTypeForVT[i] = RegisterVT;
1319
1320 MVT NVT = VT.getPow2VectorType();
1321 if (NVT == VT) {
1322 // Type is already a power of 2. The default action is to split.
1323 TransformToType[i] = MVT::Other;
1324 if (PreferredAction == TypeScalarizeVector)
1325 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1326 else if (PreferredAction == TypeSplitVector)
1327 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1328 else
1329 // Set type action according to the number of elements.
1330 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1331 : TypeSplitVector);
1332 } else {
1333 TransformToType[i] = NVT;
1334 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1335 }
1336 break;
1337 }
1338 default:
1339 llvm_unreachable("Unknown vector legalization action!");
1340 }
1341 }
1342
1343 // Determine the 'representative' register class for each value type.
1344 // An representative register class is the largest (meaning one which is
1345 // not a sub-register class / subreg register class) legal register class for
1346 // a group of value types. For example, on i386, i8, i16, and i32
1347 // representative would be GR32; while on x86_64 it's GR64.
1348 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1349 const TargetRegisterClass* RRC;
1350 uint8_t Cost;
1351 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1352 RepRegClassForVT[i] = RRC;
1353 RepRegClassCostForVT[i] = Cost;
1354 }
1355 }
1356
getSetCCResultType(const DataLayout & DL,LLVMContext &,EVT VT) const1357 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1358 EVT VT) const {
1359 assert(!VT.isVector() && "No default SetCC type for vectors!");
1360 return getPointerTy(DL).SimpleTy;
1361 }
1362
getCmpLibcallReturnType() const1363 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1364 return MVT::i32; // return the default value
1365 }
1366
1367 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1368 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1369 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1370 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1371 ///
1372 /// This method returns the number of registers needed, and the VT for each
1373 /// register. It also returns the VT and quantity of the intermediate values
1374 /// before they are promoted/expanded.
getVectorTypeBreakdown(LLVMContext & Context,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) const1375 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1376 EVT &IntermediateVT,
1377 unsigned &NumIntermediates,
1378 MVT &RegisterVT) const {
1379 unsigned NumElts = VT.getVectorNumElements();
1380
1381 // If there is a wider vector type with the same element type as this one,
1382 // or a promoted vector type that has the same number of elements which
1383 // are wider, then we should convert to that legal vector type.
1384 // This handles things like <2 x float> -> <4 x float> and
1385 // <4 x i1> -> <4 x i32>.
1386 LegalizeTypeAction TA = getTypeAction(Context, VT);
1387 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1388 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1389 if (isTypeLegal(RegisterEVT)) {
1390 IntermediateVT = RegisterEVT;
1391 RegisterVT = RegisterEVT.getSimpleVT();
1392 NumIntermediates = 1;
1393 return 1;
1394 }
1395 }
1396
1397 // Figure out the right, legal destination reg to copy into.
1398 EVT EltTy = VT.getVectorElementType();
1399
1400 unsigned NumVectorRegs = 1;
1401
1402 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1403 // could break down into LHS/RHS like LegalizeDAG does.
1404 if (!isPowerOf2_32(NumElts)) {
1405 NumVectorRegs = NumElts;
1406 NumElts = 1;
1407 }
1408
1409 // Divide the input until we get to a supported size. This will always
1410 // end with a scalar if the target doesn't support vectors.
1411 while (NumElts > 1 && !isTypeLegal(
1412 EVT::getVectorVT(Context, EltTy, NumElts))) {
1413 NumElts >>= 1;
1414 NumVectorRegs <<= 1;
1415 }
1416
1417 NumIntermediates = NumVectorRegs;
1418
1419 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1420 if (!isTypeLegal(NewVT))
1421 NewVT = EltTy;
1422 IntermediateVT = NewVT;
1423
1424 MVT DestVT = getRegisterType(Context, NewVT);
1425 RegisterVT = DestVT;
1426 unsigned NewVTSize = NewVT.getSizeInBits();
1427
1428 // Convert sizes such as i33 to i64.
1429 if (!isPowerOf2_32(NewVTSize))
1430 NewVTSize = NextPowerOf2(NewVTSize);
1431
1432 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1433 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1434
1435 // Otherwise, promotion or legal types use the same number of registers as
1436 // the vector decimated to the appropriate level.
1437 return NumVectorRegs;
1438 }
1439
isSuitableForJumpTable(const SwitchInst * SI,uint64_t NumCases,uint64_t Range,ProfileSummaryInfo * PSI,BlockFrequencyInfo * BFI) const1440 bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI,
1441 uint64_t NumCases,
1442 uint64_t Range,
1443 ProfileSummaryInfo *PSI,
1444 BlockFrequencyInfo *BFI) const {
1445 // FIXME: This function check the maximum table size and density, but the
1446 // minimum size is not checked. It would be nice if the minimum size is
1447 // also combined within this function. Currently, the minimum size check is
1448 // performed in findJumpTable() in SelectionDAGBuiler and
1449 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1450 const bool OptForSize =
1451 SI->getParent()->getParent()->hasOptSize() ||
1452 llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1453 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1454 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1455
1456 // Check whether the number of cases is small enough and
1457 // the range is dense enough for a jump table.
1458 return (OptForSize || Range <= MaxJumpTableSize) &&
1459 (NumCases * 100 >= Range * MinDensity);
1460 }
1461
1462 /// Get the EVTs and ArgFlags collections that represent the legalized return
1463 /// type of the given function. This does not require a DAG or a return value,
1464 /// and is suitable for use before any DAGs for the function are constructed.
1465 /// TODO: Move this out of TargetLowering.cpp.
GetReturnInfo(CallingConv::ID CC,Type * ReturnType,AttributeList attr,SmallVectorImpl<ISD::OutputArg> & Outs,const TargetLowering & TLI,const DataLayout & DL)1466 void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
1467 AttributeList attr,
1468 SmallVectorImpl<ISD::OutputArg> &Outs,
1469 const TargetLowering &TLI, const DataLayout &DL) {
1470 SmallVector<EVT, 4> ValueVTs;
1471 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1472 unsigned NumValues = ValueVTs.size();
1473 if (NumValues == 0) return;
1474
1475 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1476 EVT VT = ValueVTs[j];
1477 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1478
1479 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1480 ExtendKind = ISD::SIGN_EXTEND;
1481 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1482 ExtendKind = ISD::ZERO_EXTEND;
1483
1484 // FIXME: C calling convention requires the return type to be promoted to
1485 // at least 32-bit. But this is not necessary for non-C calling
1486 // conventions. The frontend should mark functions whose return values
1487 // require promoting with signext or zeroext attributes.
1488 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1489 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1490 if (VT.bitsLT(MinVT))
1491 VT = MinVT;
1492 }
1493
1494 unsigned NumParts =
1495 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1496 MVT PartVT =
1497 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1498
1499 // 'inreg' on function refers to return value
1500 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1501 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1502 Flags.setInReg();
1503
1504 // Propagate extension type if any
1505 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1506 Flags.setSExt();
1507 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1508 Flags.setZExt();
1509
1510 for (unsigned i = 0; i < NumParts; ++i)
1511 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1512 }
1513 }
1514
1515 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1516 /// function arguments in the caller parameter area. This is the actual
1517 /// alignment, not its logarithm.
getByValTypeAlignment(Type * Ty,const DataLayout & DL) const1518 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1519 const DataLayout &DL) const {
1520 return DL.getABITypeAlignment(Ty);
1521 }
1522
allowsMemoryAccessForAlignment(LLVMContext & Context,const DataLayout & DL,EVT VT,unsigned AddrSpace,unsigned Alignment,MachineMemOperand::Flags Flags,bool * Fast) const1523 bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1524 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1525 unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1526 // Check if the specified alignment is sufficient based on the data layout.
1527 // TODO: While using the data layout works in practice, a better solution
1528 // would be to implement this check directly (make this a virtual function).
1529 // For example, the ABI alignment may change based on software platform while
1530 // this function should only be affected by hardware implementation.
1531 Type *Ty = VT.getTypeForEVT(Context);
1532 if (Alignment >= DL.getABITypeAlignment(Ty)) {
1533 // Assume that an access that meets the ABI-specified alignment is fast.
1534 if (Fast != nullptr)
1535 *Fast = true;
1536 return true;
1537 }
1538
1539 // This is a misaligned access.
1540 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1541 }
1542
allowsMemoryAccessForAlignment(LLVMContext & Context,const DataLayout & DL,EVT VT,const MachineMemOperand & MMO,bool * Fast) const1543 bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1544 LLVMContext &Context, const DataLayout &DL, EVT VT,
1545 const MachineMemOperand &MMO, bool *Fast) const {
1546 return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(),
1547 MMO.getAlignment(), MMO.getFlags(),
1548 Fast);
1549 }
1550
allowsMemoryAccess(LLVMContext & Context,const DataLayout & DL,EVT VT,unsigned AddrSpace,unsigned Alignment,MachineMemOperand::Flags Flags,bool * Fast) const1551 bool TargetLoweringBase::allowsMemoryAccess(
1552 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1553 unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1554 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1555 Flags, Fast);
1556 }
1557
allowsMemoryAccess(LLVMContext & Context,const DataLayout & DL,EVT VT,const MachineMemOperand & MMO,bool * Fast) const1558 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1559 const DataLayout &DL, EVT VT,
1560 const MachineMemOperand &MMO,
1561 bool *Fast) const {
1562 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(),
1563 MMO.getAlignment(), MMO.getFlags(), Fast);
1564 }
1565
getPredictableBranchThreshold() const1566 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const {
1567 return BranchProbability(MinPercentageForPredictableBranch, 100);
1568 }
1569
1570 //===----------------------------------------------------------------------===//
1571 // TargetTransformInfo Helpers
1572 //===----------------------------------------------------------------------===//
1573
InstructionOpcodeToISD(unsigned Opcode) const1574 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1575 enum InstructionOpcodes {
1576 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1577 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1578 #include "llvm/IR/Instruction.def"
1579 };
1580 switch (static_cast<InstructionOpcodes>(Opcode)) {
1581 case Ret: return 0;
1582 case Br: return 0;
1583 case Switch: return 0;
1584 case IndirectBr: return 0;
1585 case Invoke: return 0;
1586 case CallBr: return 0;
1587 case Resume: return 0;
1588 case Unreachable: return 0;
1589 case CleanupRet: return 0;
1590 case CatchRet: return 0;
1591 case CatchPad: return 0;
1592 case CatchSwitch: return 0;
1593 case CleanupPad: return 0;
1594 case FNeg: return ISD::FNEG;
1595 case Add: return ISD::ADD;
1596 case FAdd: return ISD::FADD;
1597 case Sub: return ISD::SUB;
1598 case FSub: return ISD::FSUB;
1599 case Mul: return ISD::MUL;
1600 case FMul: return ISD::FMUL;
1601 case UDiv: return ISD::UDIV;
1602 case SDiv: return ISD::SDIV;
1603 case FDiv: return ISD::FDIV;
1604 case URem: return ISD::UREM;
1605 case SRem: return ISD::SREM;
1606 case FRem: return ISD::FREM;
1607 case Shl: return ISD::SHL;
1608 case LShr: return ISD::SRL;
1609 case AShr: return ISD::SRA;
1610 case And: return ISD::AND;
1611 case Or: return ISD::OR;
1612 case Xor: return ISD::XOR;
1613 case Alloca: return 0;
1614 case Load: return ISD::LOAD;
1615 case Store: return ISD::STORE;
1616 case GetElementPtr: return 0;
1617 case Fence: return 0;
1618 case AtomicCmpXchg: return 0;
1619 case AtomicRMW: return 0;
1620 case Trunc: return ISD::TRUNCATE;
1621 case ZExt: return ISD::ZERO_EXTEND;
1622 case SExt: return ISD::SIGN_EXTEND;
1623 case FPToUI: return ISD::FP_TO_UINT;
1624 case FPToSI: return ISD::FP_TO_SINT;
1625 case UIToFP: return ISD::UINT_TO_FP;
1626 case SIToFP: return ISD::SINT_TO_FP;
1627 case FPTrunc: return ISD::FP_ROUND;
1628 case FPExt: return ISD::FP_EXTEND;
1629 case PtrToInt: return ISD::BITCAST;
1630 case IntToPtr: return ISD::BITCAST;
1631 case BitCast: return ISD::BITCAST;
1632 case AddrSpaceCast: return ISD::ADDRSPACECAST;
1633 case ICmp: return ISD::SETCC;
1634 case FCmp: return ISD::SETCC;
1635 case PHI: return 0;
1636 case Call: return 0;
1637 case Select: return ISD::SELECT;
1638 case UserOp1: return 0;
1639 case UserOp2: return 0;
1640 case VAArg: return 0;
1641 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1642 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1643 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1644 case ExtractValue: return ISD::MERGE_VALUES;
1645 case InsertValue: return ISD::MERGE_VALUES;
1646 case LandingPad: return 0;
1647 case Freeze: return 0;
1648 }
1649
1650 llvm_unreachable("Unknown instruction type encountered!");
1651 }
1652
1653 std::pair<int, MVT>
getTypeLegalizationCost(const DataLayout & DL,Type * Ty) const1654 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1655 Type *Ty) const {
1656 LLVMContext &C = Ty->getContext();
1657 EVT MTy = getValueType(DL, Ty);
1658
1659 int Cost = 1;
1660 // We keep legalizing the type until we find a legal kind. We assume that
1661 // the only operation that costs anything is the split. After splitting
1662 // we need to handle two types.
1663 while (true) {
1664 LegalizeKind LK = getTypeConversion(C, MTy);
1665
1666 if (LK.first == TypeLegal)
1667 return std::make_pair(Cost, MTy.getSimpleVT());
1668
1669 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1670 Cost *= 2;
1671
1672 // Do not loop with f128 type.
1673 if (MTy == LK.second)
1674 return std::make_pair(Cost, MTy.getSimpleVT());
1675
1676 // Keep legalizing the type.
1677 MTy = LK.second;
1678 }
1679 }
1680
getDefaultSafeStackPointerLocation(IRBuilder<> & IRB,bool UseTLS) const1681 Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1682 bool UseTLS) const {
1683 // compiler-rt provides a variable with a magic name. Targets that do not
1684 // link with compiler-rt may also provide such a variable.
1685 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1686 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1687 auto UnsafeStackPtr =
1688 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1689
1690 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1691
1692 if (!UnsafeStackPtr) {
1693 auto TLSModel = UseTLS ?
1694 GlobalValue::InitialExecTLSModel :
1695 GlobalValue::NotThreadLocal;
1696 // The global variable is not defined yet, define it ourselves.
1697 // We use the initial-exec TLS model because we do not support the
1698 // variable living anywhere other than in the main executable.
1699 UnsafeStackPtr = new GlobalVariable(
1700 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1701 UnsafeStackPtrVar, nullptr, TLSModel);
1702 } else {
1703 // The variable exists, check its type and attributes.
1704 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1705 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1706 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1707 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1708 (UseTLS ? "" : "not ") + "be thread-local");
1709 }
1710 return UnsafeStackPtr;
1711 }
1712
getSafeStackPointerLocation(IRBuilder<> & IRB) const1713 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1714 if (!TM.getTargetTriple().isAndroid())
1715 return getDefaultSafeStackPointerLocation(IRB, true);
1716
1717 // Android provides a libc function to retrieve the address of the current
1718 // thread's unsafe stack pointer.
1719 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1720 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1721 FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1722 StackPtrTy->getPointerTo(0));
1723 return IRB.CreateCall(Fn);
1724 }
1725
1726 //===----------------------------------------------------------------------===//
1727 // Loop Strength Reduction hooks
1728 //===----------------------------------------------------------------------===//
1729
1730 /// isLegalAddressingMode - Return true if the addressing mode represented
1731 /// by AM is legal for this target, for a load/store of the specified type.
isLegalAddressingMode(const DataLayout & DL,const AddrMode & AM,Type * Ty,unsigned AS,Instruction * I) const1732 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1733 const AddrMode &AM, Type *Ty,
1734 unsigned AS, Instruction *I) const {
1735 // The default implementation of this implements a conservative RISCy, r+r and
1736 // r+i addr mode.
1737
1738 // Allows a sign-extended 16-bit immediate field.
1739 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1740 return false;
1741
1742 // No global is ever allowed as a base.
1743 if (AM.BaseGV)
1744 return false;
1745
1746 // Only support r+r,
1747 switch (AM.Scale) {
1748 case 0: // "r+i" or just "i", depending on HasBaseReg.
1749 break;
1750 case 1:
1751 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1752 return false;
1753 // Otherwise we have r+r or r+i.
1754 break;
1755 case 2:
1756 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1757 return false;
1758 // Allow 2*r as r+r.
1759 break;
1760 default: // Don't allow n * r
1761 return false;
1762 }
1763
1764 return true;
1765 }
1766
1767 //===----------------------------------------------------------------------===//
1768 // Stack Protector
1769 //===----------------------------------------------------------------------===//
1770
1771 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1772 // so that SelectionDAG handle SSP.
getIRStackGuard(IRBuilder<> & IRB) const1773 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
1774 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1775 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1776 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1777 return M.getOrInsertGlobal("__guard_local", PtrTy);
1778 }
1779 return nullptr;
1780 }
1781
1782 // Currently only support "standard" __stack_chk_guard.
1783 // TODO: add LOAD_STACK_GUARD support.
insertSSPDeclarations(Module & M) const1784 void TargetLoweringBase::insertSSPDeclarations(Module &M) const {
1785 if (!M.getNamedValue("__stack_chk_guard"))
1786 new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1787 GlobalVariable::ExternalLinkage,
1788 nullptr, "__stack_chk_guard");
1789 }
1790
1791 // Currently only support "standard" __stack_chk_guard.
1792 // TODO: add LOAD_STACK_GUARD support.
getSDagStackGuard(const Module & M) const1793 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const {
1794 return M.getNamedValue("__stack_chk_guard");
1795 }
1796
getSSPStackGuardCheck(const Module & M) const1797 Function *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const {
1798 return nullptr;
1799 }
1800
getMinimumJumpTableEntries() const1801 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
1802 return MinimumJumpTableEntries;
1803 }
1804
setMinimumJumpTableEntries(unsigned Val)1805 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
1806 MinimumJumpTableEntries = Val;
1807 }
1808
getMinimumJumpTableDensity(bool OptForSize) const1809 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1810 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1811 }
1812
getMaximumJumpTableSize() const1813 unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
1814 return MaximumJumpTableSize;
1815 }
1816
setMaximumJumpTableSize(unsigned Val)1817 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
1818 MaximumJumpTableSize = Val;
1819 }
1820
1821 //===----------------------------------------------------------------------===//
1822 // Reciprocal Estimates
1823 //===----------------------------------------------------------------------===//
1824
1825 /// Get the reciprocal estimate attribute string for a function that will
1826 /// override the target defaults.
getRecipEstimateForFunc(MachineFunction & MF)1827 static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
1828 const Function &F = MF.getFunction();
1829 return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1830 }
1831
1832 /// Construct a string for the given reciprocal operation of the given type.
1833 /// This string should match the corresponding option to the front-end's
1834 /// "-mrecip" flag assuming those strings have been passed through in an
1835 /// attribute string. For example, "vec-divf" for a division of a vXf32.
getReciprocalOpName(bool IsSqrt,EVT VT)1836 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1837 std::string Name = VT.isVector() ? "vec-" : "";
1838
1839 Name += IsSqrt ? "sqrt" : "div";
1840
1841 // TODO: Handle "half" or other float types?
1842 if (VT.getScalarType() == MVT::f64) {
1843 Name += "d";
1844 } else {
1845 assert(VT.getScalarType() == MVT::f32 &&
1846 "Unexpected FP type for reciprocal estimate");
1847 Name += "f";
1848 }
1849
1850 return Name;
1851 }
1852
1853 /// Return the character position and value (a single numeric character) of a
1854 /// customized refinement operation in the input string if it exists. Return
1855 /// false if there is no customized refinement step count.
parseRefinementStep(StringRef In,size_t & Position,uint8_t & Value)1856 static bool parseRefinementStep(StringRef In, size_t &Position,
1857 uint8_t &Value) {
1858 const char RefStepToken = ':';
1859 Position = In.find(RefStepToken);
1860 if (Position == StringRef::npos)
1861 return false;
1862
1863 StringRef RefStepString = In.substr(Position + 1);
1864 // Allow exactly one numeric character for the additional refinement
1865 // step parameter.
1866 if (RefStepString.size() == 1) {
1867 char RefStepChar = RefStepString[0];
1868 if (RefStepChar >= '0' && RefStepChar <= '9') {
1869 Value = RefStepChar - '0';
1870 return true;
1871 }
1872 }
1873 report_fatal_error("Invalid refinement step for -recip.");
1874 }
1875
1876 /// For the input attribute string, return one of the ReciprocalEstimate enum
1877 /// status values (enabled, disabled, or not specified) for this operation on
1878 /// the specified data type.
getOpEnabled(bool IsSqrt,EVT VT,StringRef Override)1879 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1880 if (Override.empty())
1881 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1882
1883 SmallVector<StringRef, 4> OverrideVector;
1884 Override.split(OverrideVector, ',');
1885 unsigned NumArgs = OverrideVector.size();
1886
1887 // Check if "all", "none", or "default" was specified.
1888 if (NumArgs == 1) {
1889 // Look for an optional setting of the number of refinement steps needed
1890 // for this type of reciprocal operation.
1891 size_t RefPos;
1892 uint8_t RefSteps;
1893 if (parseRefinementStep(Override, RefPos, RefSteps)) {
1894 // Split the string for further processing.
1895 Override = Override.substr(0, RefPos);
1896 }
1897
1898 // All reciprocal types are enabled.
1899 if (Override == "all")
1900 return TargetLoweringBase::ReciprocalEstimate::Enabled;
1901
1902 // All reciprocal types are disabled.
1903 if (Override == "none")
1904 return TargetLoweringBase::ReciprocalEstimate::Disabled;
1905
1906 // Target defaults for enablement are used.
1907 if (Override == "default")
1908 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1909 }
1910
1911 // The attribute string may omit the size suffix ('f'/'d').
1912 std::string VTName = getReciprocalOpName(IsSqrt, VT);
1913 std::string VTNameNoSize = VTName;
1914 VTNameNoSize.pop_back();
1915 static const char DisabledPrefix = '!';
1916
1917 for (StringRef RecipType : OverrideVector) {
1918 size_t RefPos;
1919 uint8_t RefSteps;
1920 if (parseRefinementStep(RecipType, RefPos, RefSteps))
1921 RecipType = RecipType.substr(0, RefPos);
1922
1923 // Ignore the disablement token for string matching.
1924 bool IsDisabled = RecipType[0] == DisabledPrefix;
1925 if (IsDisabled)
1926 RecipType = RecipType.substr(1);
1927
1928 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1929 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1930 : TargetLoweringBase::ReciprocalEstimate::Enabled;
1931 }
1932
1933 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1934 }
1935
1936 /// For the input attribute string, return the customized refinement step count
1937 /// for this operation on the specified data type. If the step count does not
1938 /// exist, return the ReciprocalEstimate enum value for unspecified.
getOpRefinementSteps(bool IsSqrt,EVT VT,StringRef Override)1939 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1940 if (Override.empty())
1941 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1942
1943 SmallVector<StringRef, 4> OverrideVector;
1944 Override.split(OverrideVector, ',');
1945 unsigned NumArgs = OverrideVector.size();
1946
1947 // Check if "all", "default", or "none" was specified.
1948 if (NumArgs == 1) {
1949 // Look for an optional setting of the number of refinement steps needed
1950 // for this type of reciprocal operation.
1951 size_t RefPos;
1952 uint8_t RefSteps;
1953 if (!parseRefinementStep(Override, RefPos, RefSteps))
1954 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1955
1956 // Split the string for further processing.
1957 Override = Override.substr(0, RefPos);
1958 assert(Override != "none" &&
1959 "Disabled reciprocals, but specifed refinement steps?");
1960
1961 // If this is a general override, return the specified number of steps.
1962 if (Override == "all" || Override == "default")
1963 return RefSteps;
1964 }
1965
1966 // The attribute string may omit the size suffix ('f'/'d').
1967 std::string VTName = getReciprocalOpName(IsSqrt, VT);
1968 std::string VTNameNoSize = VTName;
1969 VTNameNoSize.pop_back();
1970
1971 for (StringRef RecipType : OverrideVector) {
1972 size_t RefPos;
1973 uint8_t RefSteps;
1974 if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1975 continue;
1976
1977 RecipType = RecipType.substr(0, RefPos);
1978 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1979 return RefSteps;
1980 }
1981
1982 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1983 }
1984
getRecipEstimateSqrtEnabled(EVT VT,MachineFunction & MF) const1985 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
1986 MachineFunction &MF) const {
1987 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1988 }
1989
getRecipEstimateDivEnabled(EVT VT,MachineFunction & MF) const1990 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
1991 MachineFunction &MF) const {
1992 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1993 }
1994
getSqrtRefinementSteps(EVT VT,MachineFunction & MF) const1995 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
1996 MachineFunction &MF) const {
1997 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1998 }
1999
getDivRefinementSteps(EVT VT,MachineFunction & MF) const2000 int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2001 MachineFunction &MF) const {
2002 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2003 }
2004
finalizeLowering(MachineFunction & MF) const2005 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2006 MF.getRegInfo().freezeReservedRegs(MF);
2007 }
2008