1 /*
2 * Copyright © 2021 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 #ifndef AC_SURFACE_TEST_COMMON_H
28 #define AC_SURFACE_TEST_COMMON_H
29
30 #include "ac_gpu_info.h"
31 #include "amdgfxregs.h"
32
33 typedef void (*gpu_init_func)(struct radeon_info *info);
34
init_vega10(struct radeon_info * info)35 static void init_vega10(struct radeon_info *info)
36 {
37 info->family = CHIP_VEGA10;
38 info->gfx_level = GFX9;
39 info->family_id = AMDGPU_FAMILY_AI;
40 info->chip_external_rev = 0x01;
41 info->use_display_dcc_unaligned = false;
42 info->use_display_dcc_with_retile_blit = false;
43 info->has_graphics = true;
44 info->tcc_cache_line_size = 64;
45 info->max_render_backends = 16;
46
47 info->gb_addr_config = 0x2a114042;
48 }
49
init_vega20(struct radeon_info * info)50 static void init_vega20(struct radeon_info *info)
51 {
52 info->family = CHIP_VEGA20;
53 info->gfx_level = GFX9;
54 info->family_id = AMDGPU_FAMILY_AI;
55 info->chip_external_rev = 0x30;
56 info->use_display_dcc_unaligned = false;
57 info->use_display_dcc_with_retile_blit = false;
58 info->has_graphics = true;
59 info->tcc_cache_line_size = 64;
60 info->max_render_backends = 16;
61
62 info->gb_addr_config = 0x2a114042;
63 }
64
65
init_raven(struct radeon_info * info)66 static void init_raven(struct radeon_info *info)
67 {
68 info->family = CHIP_RAVEN;
69 info->gfx_level = GFX9;
70 info->family_id = AMDGPU_FAMILY_RV;
71 info->chip_external_rev = 0x01;
72 info->use_display_dcc_unaligned = false;
73 info->use_display_dcc_with_retile_blit = true;
74 info->has_graphics = true;
75 info->tcc_cache_line_size = 64;
76 info->max_render_backends = 2;
77
78 info->gb_addr_config = 0x24000042;
79 }
80
init_raven2(struct radeon_info * info)81 static void init_raven2(struct radeon_info *info)
82 {
83 info->family = CHIP_RAVEN2;
84 info->gfx_level = GFX9;
85 info->family_id = AMDGPU_FAMILY_RV;
86 info->chip_external_rev = 0x82;
87 info->use_display_dcc_unaligned = true;
88 info->use_display_dcc_with_retile_blit = false;
89 info->has_graphics = true;
90 info->tcc_cache_line_size = 64;
91 info->max_render_backends = 1;
92
93 info->gb_addr_config = 0x26013041;
94 }
95
init_navi10(struct radeon_info * info)96 static void init_navi10(struct radeon_info *info)
97 {
98 info->family = CHIP_NAVI10;
99 info->gfx_level = GFX10;
100 info->family_id = AMDGPU_FAMILY_NV;
101 info->chip_external_rev = 3;
102 info->use_display_dcc_unaligned = false;
103 info->use_display_dcc_with_retile_blit = false;
104 info->has_graphics = true;
105 info->tcc_cache_line_size = 128;
106
107 info->gb_addr_config = 0x00100044;
108 }
109
init_navi14(struct radeon_info * info)110 static void init_navi14(struct radeon_info *info)
111 {
112 info->family = CHIP_NAVI14;
113 info->gfx_level = GFX10;
114 info->family_id = AMDGPU_FAMILY_NV;
115 info->chip_external_rev = 0x15;
116 info->use_display_dcc_unaligned = false;
117 info->use_display_dcc_with_retile_blit = false;
118 info->has_graphics = true;
119 info->tcc_cache_line_size = 128;
120
121 info->gb_addr_config = 0x00000043;
122 }
123
init_gfx103(struct radeon_info * info)124 static void init_gfx103(struct radeon_info *info)
125 {
126 info->family = CHIP_NAVI21; /* This doesn't affect tests. */
127 info->gfx_level = GFX10_3;
128 info->family_id = AMDGPU_FAMILY_NV;
129 info->chip_external_rev = 0x28;
130 info->use_display_dcc_unaligned = false;
131 info->use_display_dcc_with_retile_blit = true;
132 info->has_graphics = true;
133 info->tcc_cache_line_size = 128;
134 info->has_rbplus = true;
135 info->rbplus_allowed = true;
136
137 info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
138 }
139
init_gfx11(struct radeon_info * info)140 static void init_gfx11(struct radeon_info *info)
141 {
142 info->family = CHIP_UNKNOWN;
143 info->gfx_level = GFX11;
144 info->family_id = 0x00;
145 info->chip_external_rev = 0x01;
146 info->use_display_dcc_unaligned = false;
147 info->use_display_dcc_with_retile_blit = true;
148 info->has_graphics = true;
149 info->tcc_cache_line_size = 128;
150 info->has_rbplus = true;
151 info->rbplus_allowed = true;
152
153 info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
154 }
155
156 struct testcase {
157 const char *name;
158 gpu_init_func init;
159 int banks_or_pkrs;
160 int pipes;
161 int se;
162 int rb_per_se;
163 };
164
165 static struct testcase testcases[] = {
166 {"vega10", init_vega10, 4, 2, 2, 2},
167 {"vega10_diff_bank", init_vega10, 3, 2, 2, 2},
168 {"vega10_diff_rb", init_vega10, 4, 2, 2, 0},
169 {"vega10_diff_pipe", init_vega10, 4, 0, 2, 2},
170 {"vega10_diff_se", init_vega10, 4, 2, 1, 2},
171 {"vega20", init_vega20, 4, 2, 2, 2},
172 {"raven", init_raven, 0, 2, 0, 1},
173 {"raven2", init_raven2, 3, 1, 0, 1},
174 /* Just test a bunch of different numbers. (packers, pipes) */
175 {"navi10", init_navi10, 0, 4},
176 {"navi10_diff_pipe", init_navi10, 0, 3},
177 {"navi10_diff_pkr", init_navi10, 1, 4},
178 {"navi14", init_navi14, 1, 3},
179 {"gfx103_16pipe", init_gfx103, 4, 4},
180 {"gfx103_16pipe_8pkr", init_gfx103, 3, 4},
181 {"gfx103_8pipe", init_gfx103, 3, 3},
182 {"gfx103_4pipe", init_gfx103, 2, 2},
183 {"gfx103_4pipe_2pkr", init_gfx103, 1, 2},
184 };
185
get_radeon_info(struct testcase * testcase)186 static struct radeon_info get_radeon_info(struct testcase *testcase)
187 {
188 struct radeon_info info = {
189 .drm_major = 3,
190 .drm_minor = 30,
191 };
192
193 testcase->init(&info);
194
195 switch(info.gfx_level) {
196 case GFX9:
197 info.gb_addr_config = (info.gb_addr_config &
198 C_0098F8_NUM_PIPES &
199 C_0098F8_NUM_BANKS &
200 C_0098F8_NUM_SHADER_ENGINES_GFX9 &
201 C_0098F8_NUM_RB_PER_SE) |
202 S_0098F8_NUM_PIPES(testcase->pipes) |
203 S_0098F8_NUM_BANKS(testcase->banks_or_pkrs) |
204 S_0098F8_NUM_SHADER_ENGINES_GFX9(testcase->se) |
205 S_0098F8_NUM_RB_PER_SE(testcase->rb_per_se);
206 break;
207 case GFX10:
208 case GFX10_3:
209 case GFX11:
210 info.gb_addr_config = (info.gb_addr_config &
211 C_0098F8_NUM_PIPES &
212 C_0098F8_NUM_PKRS) |
213 S_0098F8_NUM_PIPES(testcase->pipes) |
214 S_0098F8_NUM_PKRS(testcase->banks_or_pkrs);
215 /* 1 packer implies 1 RB except gfx10 where the field is ignored. */
216 info.max_render_backends = info.gfx_level == GFX10 || testcase->banks_or_pkrs ? 2 : 1;
217 break;
218 default:
219 unreachable("Unhandled generation");
220 }
221
222 return info;
223 }
224
225 #endif
226