1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/netdevice.h>
9 #include <linux/u64_stats_sync.h>
10 #include <linux/errno.h>
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
17 #include <linux/skbuff.h>
18 #include <linux/smp.h>
19 #include <asm/byteorder.h>
20 #include <linux/ip.h>
21 #include <linux/tcp.h>
22 #include <linux/sctp.h>
23 #include <linux/ipv6.h>
24 #include <net/ipv6.h>
25 #include <net/checksum.h>
26 #include <net/ip6_checksum.h>
27
28 #include "hinic_common.h"
29 #include "hinic_hw_if.h"
30 #include "hinic_hw_wqe.h"
31 #include "hinic_hw_wq.h"
32 #include "hinic_hw_qp.h"
33 #include "hinic_hw_dev.h"
34 #include "hinic_dev.h"
35 #include "hinic_tx.h"
36
37 #define TX_IRQ_NO_PENDING 0
38 #define TX_IRQ_NO_COALESC 0
39 #define TX_IRQ_NO_LLI_TIMER 0
40 #define TX_IRQ_NO_CREDIT 0
41 #define TX_IRQ_NO_RESEND_TIMER 0
42
43 #define CI_UPDATE_NO_PENDING 0
44 #define CI_UPDATE_NO_COALESC 0
45
46 #define HW_CONS_IDX(sq) be16_to_cpu(*(u16 *)((sq)->hw_ci_addr))
47
48 #define MIN_SKB_LEN 32
49
50 #define MAX_PAYLOAD_OFFSET 221
51 #define TRANSPORT_OFFSET(l4_hdr, skb) ((u32)((l4_hdr) - (skb)->data))
52
53 union hinic_l3 {
54 struct iphdr *v4;
55 struct ipv6hdr *v6;
56 unsigned char *hdr;
57 };
58
59 union hinic_l4 {
60 struct tcphdr *tcp;
61 struct udphdr *udp;
62 unsigned char *hdr;
63 };
64
65 enum hinic_offload_type {
66 TX_OFFLOAD_TSO = BIT(0),
67 TX_OFFLOAD_CSUM = BIT(1),
68 TX_OFFLOAD_VLAN = BIT(2),
69 TX_OFFLOAD_INVALID = BIT(3),
70 };
71
72 /**
73 * hinic_txq_clean_stats - Clean the statistics of specific queue
74 * @txq: Logical Tx Queue
75 **/
hinic_txq_clean_stats(struct hinic_txq * txq)76 void hinic_txq_clean_stats(struct hinic_txq *txq)
77 {
78 struct hinic_txq_stats *txq_stats = &txq->txq_stats;
79
80 u64_stats_update_begin(&txq_stats->syncp);
81 txq_stats->pkts = 0;
82 txq_stats->bytes = 0;
83 txq_stats->tx_busy = 0;
84 txq_stats->tx_wake = 0;
85 txq_stats->tx_dropped = 0;
86 txq_stats->big_frags_pkts = 0;
87 u64_stats_update_end(&txq_stats->syncp);
88 }
89
90 /**
91 * hinic_txq_get_stats - get statistics of Tx Queue
92 * @txq: Logical Tx Queue
93 * @stats: return updated stats here
94 **/
hinic_txq_get_stats(struct hinic_txq * txq,struct hinic_txq_stats * stats)95 void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats)
96 {
97 struct hinic_txq_stats *txq_stats = &txq->txq_stats;
98 unsigned int start;
99
100 do {
101 start = u64_stats_fetch_begin_irq(&txq_stats->syncp);
102 stats->pkts = txq_stats->pkts;
103 stats->bytes = txq_stats->bytes;
104 stats->tx_busy = txq_stats->tx_busy;
105 stats->tx_wake = txq_stats->tx_wake;
106 stats->tx_dropped = txq_stats->tx_dropped;
107 stats->big_frags_pkts = txq_stats->big_frags_pkts;
108 } while (u64_stats_fetch_retry_irq(&txq_stats->syncp, start));
109 }
110
111 /**
112 * txq_stats_init - Initialize the statistics of specific queue
113 * @txq: Logical Tx Queue
114 **/
txq_stats_init(struct hinic_txq * txq)115 static void txq_stats_init(struct hinic_txq *txq)
116 {
117 struct hinic_txq_stats *txq_stats = &txq->txq_stats;
118
119 u64_stats_init(&txq_stats->syncp);
120 hinic_txq_clean_stats(txq);
121 }
122
123 /**
124 * tx_map_skb - dma mapping for skb and return sges
125 * @nic_dev: nic device
126 * @skb: the skb
127 * @sges: returned sges
128 *
129 * Return 0 - Success, negative - Failure
130 **/
tx_map_skb(struct hinic_dev * nic_dev,struct sk_buff * skb,struct hinic_sge * sges)131 static int tx_map_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
132 struct hinic_sge *sges)
133 {
134 struct hinic_hwdev *hwdev = nic_dev->hwdev;
135 struct hinic_hwif *hwif = hwdev->hwif;
136 struct pci_dev *pdev = hwif->pdev;
137 skb_frag_t *frag;
138 dma_addr_t dma_addr;
139 int i, j;
140
141 dma_addr = dma_map_single(&pdev->dev, skb->data, skb_headlen(skb),
142 DMA_TO_DEVICE);
143 if (dma_mapping_error(&pdev->dev, dma_addr)) {
144 dev_err(&pdev->dev, "Failed to map Tx skb data\n");
145 return -EFAULT;
146 }
147
148 hinic_set_sge(&sges[0], dma_addr, skb_headlen(skb));
149
150 for (i = 0 ; i < skb_shinfo(skb)->nr_frags; i++) {
151 frag = &skb_shinfo(skb)->frags[i];
152
153 dma_addr = skb_frag_dma_map(&pdev->dev, frag, 0,
154 skb_frag_size(frag),
155 DMA_TO_DEVICE);
156 if (dma_mapping_error(&pdev->dev, dma_addr)) {
157 dev_err(&pdev->dev, "Failed to map Tx skb frag\n");
158 goto err_tx_map;
159 }
160
161 hinic_set_sge(&sges[i + 1], dma_addr, skb_frag_size(frag));
162 }
163
164 return 0;
165
166 err_tx_map:
167 for (j = 0; j < i; j++)
168 dma_unmap_page(&pdev->dev, hinic_sge_to_dma(&sges[j + 1]),
169 sges[j + 1].len, DMA_TO_DEVICE);
170
171 dma_unmap_single(&pdev->dev, hinic_sge_to_dma(&sges[0]), sges[0].len,
172 DMA_TO_DEVICE);
173 return -EFAULT;
174 }
175
176 /**
177 * tx_unmap_skb - unmap the dma address of the skb
178 * @nic_dev: nic device
179 * @skb: the skb
180 * @sges: the sges that are connected to the skb
181 **/
tx_unmap_skb(struct hinic_dev * nic_dev,struct sk_buff * skb,struct hinic_sge * sges)182 static void tx_unmap_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
183 struct hinic_sge *sges)
184 {
185 struct hinic_hwdev *hwdev = nic_dev->hwdev;
186 struct hinic_hwif *hwif = hwdev->hwif;
187 struct pci_dev *pdev = hwif->pdev;
188 int i;
189
190 for (i = 0; i < skb_shinfo(skb)->nr_frags ; i++)
191 dma_unmap_page(&pdev->dev, hinic_sge_to_dma(&sges[i + 1]),
192 sges[i + 1].len, DMA_TO_DEVICE);
193
194 dma_unmap_single(&pdev->dev, hinic_sge_to_dma(&sges[0]), sges[0].len,
195 DMA_TO_DEVICE);
196 }
197
get_inner_l3_l4_type(struct sk_buff * skb,union hinic_l3 * ip,union hinic_l4 * l4,enum hinic_offload_type offload_type,enum hinic_l3_offload_type * l3_type,u8 * l4_proto)198 static void get_inner_l3_l4_type(struct sk_buff *skb, union hinic_l3 *ip,
199 union hinic_l4 *l4,
200 enum hinic_offload_type offload_type,
201 enum hinic_l3_offload_type *l3_type,
202 u8 *l4_proto)
203 {
204 u8 *exthdr;
205
206 if (ip->v4->version == 4) {
207 *l3_type = (offload_type == TX_OFFLOAD_CSUM) ?
208 IPV4_PKT_NO_CHKSUM_OFFLOAD :
209 IPV4_PKT_WITH_CHKSUM_OFFLOAD;
210 *l4_proto = ip->v4->protocol;
211 } else if (ip->v4->version == 6) {
212 *l3_type = IPV6_PKT;
213 exthdr = ip->hdr + sizeof(*ip->v6);
214 *l4_proto = ip->v6->nexthdr;
215 if (exthdr != l4->hdr) {
216 int start = exthdr - skb->data;
217 __be16 frag_off;
218
219 ipv6_skip_exthdr(skb, start, l4_proto, &frag_off);
220 }
221 } else {
222 *l3_type = L3TYPE_UNKNOWN;
223 *l4_proto = 0;
224 }
225 }
226
get_inner_l4_info(struct sk_buff * skb,union hinic_l4 * l4,enum hinic_offload_type offload_type,u8 l4_proto,enum hinic_l4_offload_type * l4_offload,u32 * l4_len,u32 * offset)227 static void get_inner_l4_info(struct sk_buff *skb, union hinic_l4 *l4,
228 enum hinic_offload_type offload_type, u8 l4_proto,
229 enum hinic_l4_offload_type *l4_offload,
230 u32 *l4_len, u32 *offset)
231 {
232 *l4_offload = OFFLOAD_DISABLE;
233 *offset = 0;
234 *l4_len = 0;
235
236 switch (l4_proto) {
237 case IPPROTO_TCP:
238 *l4_offload = TCP_OFFLOAD_ENABLE;
239 /* doff in unit of 4B */
240 *l4_len = l4->tcp->doff * 4;
241 *offset = *l4_len + TRANSPORT_OFFSET(l4->hdr, skb);
242 break;
243
244 case IPPROTO_UDP:
245 *l4_offload = UDP_OFFLOAD_ENABLE;
246 *l4_len = sizeof(struct udphdr);
247 *offset = TRANSPORT_OFFSET(l4->hdr, skb);
248 break;
249
250 case IPPROTO_SCTP:
251 /* only csum offload support sctp */
252 if (offload_type != TX_OFFLOAD_CSUM)
253 break;
254
255 *l4_offload = SCTP_OFFLOAD_ENABLE;
256 *l4_len = sizeof(struct sctphdr);
257 *offset = TRANSPORT_OFFSET(l4->hdr, skb);
258 break;
259
260 default:
261 break;
262 }
263 }
264
csum_magic(union hinic_l3 * ip,unsigned short proto)265 static __sum16 csum_magic(union hinic_l3 *ip, unsigned short proto)
266 {
267 return (ip->v4->version == 4) ?
268 csum_tcpudp_magic(ip->v4->saddr, ip->v4->daddr, 0, proto, 0) :
269 csum_ipv6_magic(&ip->v6->saddr, &ip->v6->daddr, 0, proto, 0);
270 }
271
offload_tso(struct hinic_sq_task * task,u32 * queue_info,struct sk_buff * skb)272 static int offload_tso(struct hinic_sq_task *task, u32 *queue_info,
273 struct sk_buff *skb)
274 {
275 u32 offset, l4_len, ip_identify, network_hdr_len;
276 enum hinic_l3_offload_type l3_offload;
277 enum hinic_l4_offload_type l4_offload;
278 union hinic_l3 ip;
279 union hinic_l4 l4;
280 u8 l4_proto;
281
282 if (!skb_is_gso(skb))
283 return 0;
284
285 if (skb_cow_head(skb, 0) < 0)
286 return -EPROTONOSUPPORT;
287
288 if (skb->encapsulation) {
289 u32 gso_type = skb_shinfo(skb)->gso_type;
290 u32 tunnel_type = 0;
291 u32 l4_tunnel_len;
292
293 ip.hdr = skb_network_header(skb);
294 l4.hdr = skb_transport_header(skb);
295 network_hdr_len = skb_inner_network_header_len(skb);
296
297 if (ip.v4->version == 4) {
298 ip.v4->tot_len = 0;
299 l3_offload = IPV4_PKT_WITH_CHKSUM_OFFLOAD;
300 } else if (ip.v4->version == 6) {
301 l3_offload = IPV6_PKT;
302 } else {
303 l3_offload = 0;
304 }
305
306 hinic_task_set_outter_l3(task, l3_offload,
307 skb_network_header_len(skb));
308
309 if (gso_type & SKB_GSO_UDP_TUNNEL_CSUM) {
310 l4.udp->check = ~csum_magic(&ip, IPPROTO_UDP);
311 tunnel_type = TUNNEL_UDP_CSUM;
312 } else if (gso_type & SKB_GSO_UDP_TUNNEL) {
313 tunnel_type = TUNNEL_UDP_NO_CSUM;
314 }
315
316 l4_tunnel_len = skb_inner_network_offset(skb) -
317 skb_transport_offset(skb);
318 hinic_task_set_tunnel_l4(task, tunnel_type, l4_tunnel_len);
319
320 ip.hdr = skb_inner_network_header(skb);
321 l4.hdr = skb_inner_transport_header(skb);
322 } else {
323 ip.hdr = skb_network_header(skb);
324 l4.hdr = skb_transport_header(skb);
325 network_hdr_len = skb_network_header_len(skb);
326 }
327
328 /* initialize inner IP header fields */
329 if (ip.v4->version == 4)
330 ip.v4->tot_len = 0;
331 else
332 ip.v6->payload_len = 0;
333
334 get_inner_l3_l4_type(skb, &ip, &l4, TX_OFFLOAD_TSO, &l3_offload,
335 &l4_proto);
336
337 hinic_task_set_inner_l3(task, l3_offload, network_hdr_len);
338
339 ip_identify = 0;
340 if (l4_proto == IPPROTO_TCP)
341 l4.tcp->check = ~csum_magic(&ip, IPPROTO_TCP);
342
343 get_inner_l4_info(skb, &l4, TX_OFFLOAD_TSO, l4_proto, &l4_offload,
344 &l4_len, &offset);
345
346 hinic_set_tso_inner_l4(task, queue_info, l4_offload, l4_len, offset,
347 ip_identify, skb_shinfo(skb)->gso_size);
348
349 return 1;
350 }
351
offload_csum(struct hinic_sq_task * task,u32 * queue_info,struct sk_buff * skb)352 static int offload_csum(struct hinic_sq_task *task, u32 *queue_info,
353 struct sk_buff *skb)
354 {
355 enum hinic_l4_offload_type l4_offload;
356 u32 offset, l4_len, network_hdr_len;
357 enum hinic_l3_offload_type l3_type;
358 u32 tunnel_type = NOT_TUNNEL;
359 union hinic_l3 ip;
360 union hinic_l4 l4;
361 u8 l4_proto;
362
363 if (skb->ip_summed != CHECKSUM_PARTIAL)
364 return 0;
365
366 if (skb->encapsulation) {
367 u32 l4_tunnel_len;
368
369 tunnel_type = TUNNEL_UDP_NO_CSUM;
370 ip.hdr = skb_network_header(skb);
371
372 if (ip.v4->version == 4) {
373 l3_type = IPV4_PKT_NO_CHKSUM_OFFLOAD;
374 l4_proto = ip.v4->protocol;
375 } else if (ip.v4->version == 6) {
376 unsigned char *exthdr;
377 __be16 frag_off;
378 l3_type = IPV6_PKT;
379 tunnel_type = TUNNEL_UDP_CSUM;
380 exthdr = ip.hdr + sizeof(*ip.v6);
381 l4_proto = ip.v6->nexthdr;
382 l4.hdr = skb_transport_header(skb);
383 if (l4.hdr != exthdr)
384 ipv6_skip_exthdr(skb, exthdr - skb->data,
385 &l4_proto, &frag_off);
386 } else {
387 l3_type = L3TYPE_UNKNOWN;
388 l4_proto = IPPROTO_RAW;
389 }
390
391 hinic_task_set_outter_l3(task, l3_type,
392 skb_network_header_len(skb));
393
394 switch (l4_proto) {
395 case IPPROTO_UDP:
396 l4_tunnel_len = skb_inner_network_offset(skb) -
397 skb_transport_offset(skb);
398 ip.hdr = skb_inner_network_header(skb);
399 l4.hdr = skb_inner_transport_header(skb);
400 network_hdr_len = skb_inner_network_header_len(skb);
401 break;
402 case IPPROTO_IPIP:
403 case IPPROTO_IPV6:
404 tunnel_type = NOT_TUNNEL;
405 l4_tunnel_len = 0;
406
407 ip.hdr = skb_inner_network_header(skb);
408 l4.hdr = skb_transport_header(skb);
409 network_hdr_len = skb_network_header_len(skb);
410 break;
411 default:
412 /* Unsupported tunnel packet, disable csum offload */
413 skb_checksum_help(skb);
414 return 0;
415 }
416
417 hinic_task_set_tunnel_l4(task, tunnel_type, l4_tunnel_len);
418 } else {
419 ip.hdr = skb_network_header(skb);
420 l4.hdr = skb_transport_header(skb);
421 network_hdr_len = skb_network_header_len(skb);
422 }
423
424 get_inner_l3_l4_type(skb, &ip, &l4, TX_OFFLOAD_CSUM, &l3_type,
425 &l4_proto);
426
427 hinic_task_set_inner_l3(task, l3_type, network_hdr_len);
428
429 get_inner_l4_info(skb, &l4, TX_OFFLOAD_CSUM, l4_proto, &l4_offload,
430 &l4_len, &offset);
431
432 hinic_set_cs_inner_l4(task, queue_info, l4_offload, l4_len, offset);
433
434 return 1;
435 }
436
offload_vlan(struct hinic_sq_task * task,u32 * queue_info,u16 vlan_tag,u16 vlan_pri)437 static void offload_vlan(struct hinic_sq_task *task, u32 *queue_info,
438 u16 vlan_tag, u16 vlan_pri)
439 {
440 task->pkt_info0 |= HINIC_SQ_TASK_INFO0_SET(vlan_tag, VLAN_TAG) |
441 HINIC_SQ_TASK_INFO0_SET(1U, VLAN_OFFLOAD);
442
443 *queue_info |= HINIC_SQ_CTRL_SET(vlan_pri, QUEUE_INFO_PRI);
444 }
445
hinic_tx_offload(struct sk_buff * skb,struct hinic_sq_task * task,u32 * queue_info)446 static int hinic_tx_offload(struct sk_buff *skb, struct hinic_sq_task *task,
447 u32 *queue_info)
448 {
449 enum hinic_offload_type offload = 0;
450 u16 vlan_tag;
451 int enabled;
452
453 enabled = offload_tso(task, queue_info, skb);
454 if (enabled > 0) {
455 offload |= TX_OFFLOAD_TSO;
456 } else if (enabled == 0) {
457 enabled = offload_csum(task, queue_info, skb);
458 if (enabled)
459 offload |= TX_OFFLOAD_CSUM;
460 } else {
461 return -EPROTONOSUPPORT;
462 }
463
464 if (unlikely(skb_vlan_tag_present(skb))) {
465 vlan_tag = skb_vlan_tag_get(skb);
466 offload_vlan(task, queue_info, vlan_tag,
467 vlan_tag >> VLAN_PRIO_SHIFT);
468 offload |= TX_OFFLOAD_VLAN;
469 }
470
471 if (offload)
472 hinic_task_set_l2hdr(task, skb_network_offset(skb));
473
474 /* payload offset should not more than 221 */
475 if (HINIC_SQ_CTRL_GET(*queue_info, QUEUE_INFO_PLDOFF) >
476 MAX_PAYLOAD_OFFSET) {
477 return -EPROTONOSUPPORT;
478 }
479
480 /* mss should not less than 80 */
481 if (HINIC_SQ_CTRL_GET(*queue_info, QUEUE_INFO_MSS) < HINIC_MSS_MIN) {
482 *queue_info = HINIC_SQ_CTRL_CLEAR(*queue_info, QUEUE_INFO_MSS);
483 *queue_info |= HINIC_SQ_CTRL_SET(HINIC_MSS_MIN, QUEUE_INFO_MSS);
484 }
485
486 return 0;
487 }
488
hinic_lb_xmit_frame(struct sk_buff * skb,struct net_device * netdev)489 netdev_tx_t hinic_lb_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
490 {
491 struct hinic_dev *nic_dev = netdev_priv(netdev);
492 u16 prod_idx, q_id = skb->queue_mapping;
493 struct netdev_queue *netdev_txq;
494 int nr_sges, err = NETDEV_TX_OK;
495 struct hinic_sq_wqe *sq_wqe;
496 unsigned int wqe_size;
497 struct hinic_txq *txq;
498 struct hinic_qp *qp;
499
500 txq = &nic_dev->txqs[q_id];
501 qp = container_of(txq->sq, struct hinic_qp, sq);
502 nr_sges = skb_shinfo(skb)->nr_frags + 1;
503
504 err = tx_map_skb(nic_dev, skb, txq->sges);
505 if (err)
506 goto skb_error;
507
508 wqe_size = HINIC_SQ_WQE_SIZE(nr_sges);
509
510 sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
511 if (!sq_wqe) {
512 netif_stop_subqueue(netdev, qp->q_id);
513
514 sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
515 if (sq_wqe) {
516 netif_wake_subqueue(nic_dev->netdev, qp->q_id);
517 goto process_sq_wqe;
518 }
519
520 tx_unmap_skb(nic_dev, skb, txq->sges);
521
522 u64_stats_update_begin(&txq->txq_stats.syncp);
523 txq->txq_stats.tx_busy++;
524 u64_stats_update_end(&txq->txq_stats.syncp);
525 err = NETDEV_TX_BUSY;
526 wqe_size = 0;
527 goto flush_skbs;
528 }
529
530 process_sq_wqe:
531 hinic_sq_prepare_wqe(txq->sq, prod_idx, sq_wqe, txq->sges, nr_sges);
532 hinic_sq_write_wqe(txq->sq, prod_idx, sq_wqe, skb, wqe_size);
533
534 flush_skbs:
535 netdev_txq = netdev_get_tx_queue(netdev, q_id);
536 if ((!netdev_xmit_more()) || (netif_xmit_stopped(netdev_txq)))
537 hinic_sq_write_db(txq->sq, prod_idx, wqe_size, 0);
538
539 return err;
540
541 skb_error:
542 dev_kfree_skb_any(skb);
543 u64_stats_update_begin(&txq->txq_stats.syncp);
544 txq->txq_stats.tx_dropped++;
545 u64_stats_update_end(&txq->txq_stats.syncp);
546
547 return NETDEV_TX_OK;
548 }
549
hinic_xmit_frame(struct sk_buff * skb,struct net_device * netdev)550 netdev_tx_t hinic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
551 {
552 struct hinic_dev *nic_dev = netdev_priv(netdev);
553 u16 prod_idx, q_id = skb->queue_mapping;
554 struct netdev_queue *netdev_txq;
555 int nr_sges, err = NETDEV_TX_OK;
556 struct hinic_sq_wqe *sq_wqe;
557 unsigned int wqe_size;
558 struct hinic_txq *txq;
559 struct hinic_qp *qp;
560
561 txq = &nic_dev->txqs[q_id];
562 qp = container_of(txq->sq, struct hinic_qp, sq);
563
564 if (skb->len < MIN_SKB_LEN) {
565 if (skb_pad(skb, MIN_SKB_LEN - skb->len)) {
566 netdev_err(netdev, "Failed to pad skb\n");
567 goto update_error_stats;
568 }
569
570 skb->len = MIN_SKB_LEN;
571 }
572
573 nr_sges = skb_shinfo(skb)->nr_frags + 1;
574 if (nr_sges > 17) {
575 u64_stats_update_begin(&txq->txq_stats.syncp);
576 txq->txq_stats.big_frags_pkts++;
577 u64_stats_update_end(&txq->txq_stats.syncp);
578 }
579
580 if (nr_sges > txq->max_sges) {
581 netdev_err(netdev, "Too many Tx sges\n");
582 goto skb_error;
583 }
584
585 err = tx_map_skb(nic_dev, skb, txq->sges);
586 if (err)
587 goto skb_error;
588
589 wqe_size = HINIC_SQ_WQE_SIZE(nr_sges);
590
591 sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
592 if (!sq_wqe) {
593 netif_stop_subqueue(netdev, qp->q_id);
594
595 /* Check for the case free_tx_poll is called in another cpu
596 * and we stopped the subqueue after free_tx_poll check.
597 */
598 sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
599 if (sq_wqe) {
600 netif_wake_subqueue(nic_dev->netdev, qp->q_id);
601 goto process_sq_wqe;
602 }
603
604 tx_unmap_skb(nic_dev, skb, txq->sges);
605
606 u64_stats_update_begin(&txq->txq_stats.syncp);
607 txq->txq_stats.tx_busy++;
608 u64_stats_update_end(&txq->txq_stats.syncp);
609 err = NETDEV_TX_BUSY;
610 wqe_size = 0;
611 goto flush_skbs;
612 }
613
614 process_sq_wqe:
615 hinic_sq_prepare_wqe(txq->sq, prod_idx, sq_wqe, txq->sges, nr_sges);
616
617 err = hinic_tx_offload(skb, &sq_wqe->task, &sq_wqe->ctrl.queue_info);
618 if (err)
619 goto offload_error;
620
621 hinic_sq_write_wqe(txq->sq, prod_idx, sq_wqe, skb, wqe_size);
622
623 flush_skbs:
624 netdev_txq = netdev_get_tx_queue(netdev, q_id);
625 if ((!netdev_xmit_more()) || (netif_xmit_stopped(netdev_txq)))
626 hinic_sq_write_db(txq->sq, prod_idx, wqe_size, 0);
627
628 return err;
629
630 offload_error:
631 hinic_sq_return_wqe(txq->sq, wqe_size);
632 tx_unmap_skb(nic_dev, skb, txq->sges);
633
634 skb_error:
635 dev_kfree_skb_any(skb);
636
637 update_error_stats:
638 u64_stats_update_begin(&txq->txq_stats.syncp);
639 txq->txq_stats.tx_dropped++;
640 u64_stats_update_end(&txq->txq_stats.syncp);
641
642 return NETDEV_TX_OK;
643 }
644
645 /**
646 * tx_free_skb - unmap and free skb
647 * @nic_dev: nic device
648 * @skb: the skb
649 * @sges: the sges that are connected to the skb
650 **/
tx_free_skb(struct hinic_dev * nic_dev,struct sk_buff * skb,struct hinic_sge * sges)651 static void tx_free_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
652 struct hinic_sge *sges)
653 {
654 tx_unmap_skb(nic_dev, skb, sges);
655
656 dev_kfree_skb_any(skb);
657 }
658
659 /**
660 * free_all_rx_skbs - free all skbs in tx queue
661 * @txq: tx queue
662 **/
free_all_tx_skbs(struct hinic_txq * txq)663 static void free_all_tx_skbs(struct hinic_txq *txq)
664 {
665 struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
666 struct hinic_sq *sq = txq->sq;
667 struct hinic_sq_wqe *sq_wqe;
668 unsigned int wqe_size;
669 struct sk_buff *skb;
670 int nr_sges;
671 u16 ci;
672
673 while ((sq_wqe = hinic_sq_read_wqebb(sq, &skb, &wqe_size, &ci))) {
674 sq_wqe = hinic_sq_read_wqe(sq, &skb, wqe_size, &ci);
675 if (!sq_wqe)
676 break;
677
678 nr_sges = skb_shinfo(skb)->nr_frags + 1;
679
680 hinic_sq_get_sges(sq_wqe, txq->free_sges, nr_sges);
681
682 hinic_sq_put_wqe(sq, wqe_size);
683
684 tx_free_skb(nic_dev, skb, txq->free_sges);
685 }
686 }
687
688 /**
689 * free_tx_poll - free finished tx skbs in tx queue that connected to napi
690 * @napi: napi
691 * @budget: number of tx
692 *
693 * Return 0 - Success, negative - Failure
694 **/
free_tx_poll(struct napi_struct * napi,int budget)695 static int free_tx_poll(struct napi_struct *napi, int budget)
696 {
697 struct hinic_txq *txq = container_of(napi, struct hinic_txq, napi);
698 struct hinic_qp *qp = container_of(txq->sq, struct hinic_qp, sq);
699 struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
700 struct netdev_queue *netdev_txq;
701 struct hinic_sq *sq = txq->sq;
702 struct hinic_wq *wq = sq->wq;
703 struct hinic_sq_wqe *sq_wqe;
704 unsigned int wqe_size;
705 int nr_sges, pkts = 0;
706 struct sk_buff *skb;
707 u64 tx_bytes = 0;
708 u16 hw_ci, sw_ci;
709
710 do {
711 hw_ci = HW_CONS_IDX(sq) & wq->mask;
712
713 dma_rmb();
714
715 /* Reading a WQEBB to get real WQE size and consumer index. */
716 sq_wqe = hinic_sq_read_wqebb(sq, &skb, &wqe_size, &sw_ci);
717 if ((!sq_wqe) ||
718 (((hw_ci - sw_ci) & wq->mask) * wq->wqebb_size < wqe_size))
719 break;
720
721 /* If this WQE have multiple WQEBBs, we will read again to get
722 * full size WQE.
723 */
724 if (wqe_size > wq->wqebb_size) {
725 sq_wqe = hinic_sq_read_wqe(sq, &skb, wqe_size, &sw_ci);
726 if (unlikely(!sq_wqe))
727 break;
728 }
729
730 tx_bytes += skb->len;
731 pkts++;
732
733 nr_sges = skb_shinfo(skb)->nr_frags + 1;
734
735 hinic_sq_get_sges(sq_wqe, txq->free_sges, nr_sges);
736
737 hinic_sq_put_wqe(sq, wqe_size);
738
739 tx_free_skb(nic_dev, skb, txq->free_sges);
740 } while (pkts < budget);
741
742 if (__netif_subqueue_stopped(nic_dev->netdev, qp->q_id) &&
743 hinic_get_sq_free_wqebbs(sq) >= HINIC_MIN_TX_NUM_WQEBBS(sq)) {
744 netdev_txq = netdev_get_tx_queue(txq->netdev, qp->q_id);
745
746 __netif_tx_lock(netdev_txq, smp_processor_id());
747 if (!netif_testing(nic_dev->netdev))
748 netif_wake_subqueue(nic_dev->netdev, qp->q_id);
749
750 __netif_tx_unlock(netdev_txq);
751
752 u64_stats_update_begin(&txq->txq_stats.syncp);
753 txq->txq_stats.tx_wake++;
754 u64_stats_update_end(&txq->txq_stats.syncp);
755 }
756
757 u64_stats_update_begin(&txq->txq_stats.syncp);
758 txq->txq_stats.bytes += tx_bytes;
759 txq->txq_stats.pkts += pkts;
760 u64_stats_update_end(&txq->txq_stats.syncp);
761
762 if (pkts < budget) {
763 napi_complete(napi);
764 if (!HINIC_IS_VF(nic_dev->hwdev->hwif))
765 hinic_hwdev_set_msix_state(nic_dev->hwdev,
766 sq->msix_entry,
767 HINIC_MSIX_ENABLE);
768
769 return pkts;
770 }
771
772 return budget;
773 }
774
tx_irq(int irq,void * data)775 static irqreturn_t tx_irq(int irq, void *data)
776 {
777 struct hinic_txq *txq = data;
778 struct hinic_dev *nic_dev;
779
780 nic_dev = netdev_priv(txq->netdev);
781
782 if (!HINIC_IS_VF(nic_dev->hwdev->hwif))
783 /* Disable the interrupt until napi will be completed */
784 hinic_hwdev_set_msix_state(nic_dev->hwdev,
785 txq->sq->msix_entry,
786 HINIC_MSIX_DISABLE);
787
788 hinic_hwdev_msix_cnt_set(nic_dev->hwdev, txq->sq->msix_entry);
789
790 napi_schedule(&txq->napi);
791 return IRQ_HANDLED;
792 }
793
tx_request_irq(struct hinic_txq * txq)794 static int tx_request_irq(struct hinic_txq *txq)
795 {
796 struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
797 struct hinic_msix_config interrupt_info = {0};
798 struct hinic_intr_coal_info *intr_coal = NULL;
799 struct hinic_hwdev *hwdev = nic_dev->hwdev;
800 struct hinic_hwif *hwif = hwdev->hwif;
801 struct pci_dev *pdev = hwif->pdev;
802 struct hinic_sq *sq = txq->sq;
803 struct hinic_qp *qp;
804 int err;
805
806 qp = container_of(sq, struct hinic_qp, sq);
807
808 netif_napi_add(txq->netdev, &txq->napi, free_tx_poll, nic_dev->tx_weight);
809
810 hinic_hwdev_msix_set(nic_dev->hwdev, sq->msix_entry,
811 TX_IRQ_NO_PENDING, TX_IRQ_NO_COALESC,
812 TX_IRQ_NO_LLI_TIMER, TX_IRQ_NO_CREDIT,
813 TX_IRQ_NO_RESEND_TIMER);
814
815 intr_coal = &nic_dev->tx_intr_coalesce[qp->q_id];
816 interrupt_info.msix_index = sq->msix_entry;
817 interrupt_info.coalesce_timer_cnt = intr_coal->coalesce_timer_cfg;
818 interrupt_info.pending_cnt = intr_coal->pending_limt;
819 interrupt_info.resend_timer_cnt = intr_coal->resend_timer_cfg;
820
821 err = hinic_set_interrupt_cfg(hwdev, &interrupt_info);
822 if (err) {
823 netif_err(nic_dev, drv, txq->netdev,
824 "Failed to set TX interrupt coalescing attribute\n");
825 netif_napi_del(&txq->napi);
826 return err;
827 }
828
829 err = request_irq(sq->irq, tx_irq, 0, txq->irq_name, txq);
830 if (err) {
831 dev_err(&pdev->dev, "Failed to request Tx irq\n");
832 netif_napi_del(&txq->napi);
833 return err;
834 }
835
836 return 0;
837 }
838
tx_free_irq(struct hinic_txq * txq)839 static void tx_free_irq(struct hinic_txq *txq)
840 {
841 struct hinic_sq *sq = txq->sq;
842
843 free_irq(sq->irq, txq);
844 netif_napi_del(&txq->napi);
845 }
846
847 /**
848 * hinic_init_txq - Initialize the Tx Queue
849 * @txq: Logical Tx Queue
850 * @sq: Hardware Tx Queue to connect the Logical queue with
851 * @netdev: network device to connect the Logical queue with
852 *
853 * Return 0 - Success, negative - Failure
854 **/
hinic_init_txq(struct hinic_txq * txq,struct hinic_sq * sq,struct net_device * netdev)855 int hinic_init_txq(struct hinic_txq *txq, struct hinic_sq *sq,
856 struct net_device *netdev)
857 {
858 struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq);
859 struct hinic_dev *nic_dev = netdev_priv(netdev);
860 struct hinic_hwdev *hwdev = nic_dev->hwdev;
861 int err, irqname_len;
862
863 txq->netdev = netdev;
864 txq->sq = sq;
865
866 txq_stats_init(txq);
867
868 txq->max_sges = HINIC_MAX_SQ_BUFDESCS;
869
870 txq->sges = devm_kcalloc(&netdev->dev, txq->max_sges,
871 sizeof(*txq->sges), GFP_KERNEL);
872 if (!txq->sges)
873 return -ENOMEM;
874
875 txq->free_sges = devm_kcalloc(&netdev->dev, txq->max_sges,
876 sizeof(*txq->free_sges), GFP_KERNEL);
877 if (!txq->free_sges) {
878 err = -ENOMEM;
879 goto err_alloc_free_sges;
880 }
881
882 irqname_len = snprintf(NULL, 0, "%s_txq%d", netdev->name, qp->q_id) + 1;
883 txq->irq_name = devm_kzalloc(&netdev->dev, irqname_len, GFP_KERNEL);
884 if (!txq->irq_name) {
885 err = -ENOMEM;
886 goto err_alloc_irqname;
887 }
888
889 sprintf(txq->irq_name, "%s_txq%d", netdev->name, qp->q_id);
890
891 err = hinic_hwdev_hw_ci_addr_set(hwdev, sq, CI_UPDATE_NO_PENDING,
892 CI_UPDATE_NO_COALESC);
893 if (err)
894 goto err_hw_ci;
895
896 err = tx_request_irq(txq);
897 if (err) {
898 netdev_err(netdev, "Failed to request Tx irq\n");
899 goto err_req_tx_irq;
900 }
901
902 return 0;
903
904 err_req_tx_irq:
905 err_hw_ci:
906 devm_kfree(&netdev->dev, txq->irq_name);
907
908 err_alloc_irqname:
909 devm_kfree(&netdev->dev, txq->free_sges);
910
911 err_alloc_free_sges:
912 devm_kfree(&netdev->dev, txq->sges);
913 return err;
914 }
915
916 /**
917 * hinic_clean_txq - Clean the Tx Queue
918 * @txq: Logical Tx Queue
919 **/
hinic_clean_txq(struct hinic_txq * txq)920 void hinic_clean_txq(struct hinic_txq *txq)
921 {
922 struct net_device *netdev = txq->netdev;
923
924 tx_free_irq(txq);
925
926 free_all_tx_skbs(txq);
927
928 devm_kfree(&netdev->dev, txq->irq_name);
929 devm_kfree(&netdev->dev, txq->free_sges);
930 devm_kfree(&netdev->dev, txq->sges);
931 }
932