1 /*
2 * Copyright © 2008-2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "i915_drv.h"
25 #include "i915_scatterlist.h"
26 #include "i915_pvinfo.h"
27 #include "i915_vgpu.h"
28
29 /**
30 * DOC: fence register handling
31 *
32 * Important to avoid confusions: "fences" in the i915 driver are not execution
33 * fences used to track command completion but hardware detiler objects which
34 * wrap a given range of the global GTT. Each platform has only a fairly limited
35 * set of these objects.
36 *
37 * Fences are used to detile GTT memory mappings. They're also connected to the
38 * hardware frontbuffer render tracking and hence interact with frontbuffer
39 * compression. Furthermore on older platforms fences are required for tiled
40 * objects used by the display engine. They can also be used by the render
41 * engine - they're required for blitter commands and are optional for render
42 * commands. But on gen4+ both display (with the exception of fbc) and rendering
43 * have their own tiling state bits and don't need fences.
44 *
45 * Also note that fences only support X and Y tiling and hence can't be used for
46 * the fancier new tiling formats like W, Ys and Yf.
47 *
48 * Finally note that because fences are such a restricted resource they're
49 * dynamically associated with objects. Furthermore fence state is committed to
50 * the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must
51 * explicitly call i915_gem_object_get_fence() to synchronize fencing status
52 * for cpu access. Also note that some code wants an unfenced view, for those
53 * cases the fence can be removed forcefully with i915_gem_object_put_fence().
54 *
55 * Internally these functions will synchronize with userspace access by removing
56 * CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.
57 */
58
59 #define pipelined 0
60
fence_to_i915(struct i915_fence_reg * fence)61 static struct drm_i915_private *fence_to_i915(struct i915_fence_reg *fence)
62 {
63 return fence->ggtt->vm.i915;
64 }
65
fence_to_uncore(struct i915_fence_reg * fence)66 static struct intel_uncore *fence_to_uncore(struct i915_fence_reg *fence)
67 {
68 return fence->ggtt->vm.gt->uncore;
69 }
70
i965_write_fence_reg(struct i915_fence_reg * fence)71 static void i965_write_fence_reg(struct i915_fence_reg *fence)
72 {
73 i915_reg_t fence_reg_lo, fence_reg_hi;
74 int fence_pitch_shift;
75 u64 val;
76
77 if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
78 fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
79 fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
80 fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
81
82 } else {
83 fence_reg_lo = FENCE_REG_965_LO(fence->id);
84 fence_reg_hi = FENCE_REG_965_HI(fence->id);
85 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
86 }
87
88 val = 0;
89 if (fence->tiling) {
90 unsigned int stride = fence->stride;
91
92 GEM_BUG_ON(!IS_ALIGNED(stride, 128));
93
94 val = fence->start + fence->size - I965_FENCE_PAGE;
95 val <<= 32;
96 val |= fence->start;
97 val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
98 if (fence->tiling == I915_TILING_Y)
99 val |= BIT(I965_FENCE_TILING_Y_SHIFT);
100 val |= I965_FENCE_REG_VALID;
101 }
102
103 if (!pipelined) {
104 struct intel_uncore *uncore = fence_to_uncore(fence);
105
106 /*
107 * To w/a incoherency with non-atomic 64-bit register updates,
108 * we split the 64-bit update into two 32-bit writes. In order
109 * for a partial fence not to be evaluated between writes, we
110 * precede the update with write to turn off the fence register,
111 * and only enable the fence as the last step.
112 *
113 * For extra levels of paranoia, we make sure each step lands
114 * before applying the next step.
115 */
116 intel_uncore_write_fw(uncore, fence_reg_lo, 0);
117 intel_uncore_posting_read_fw(uncore, fence_reg_lo);
118
119 intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val));
120 intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val));
121 intel_uncore_posting_read_fw(uncore, fence_reg_lo);
122 }
123 }
124
i915_write_fence_reg(struct i915_fence_reg * fence)125 static void i915_write_fence_reg(struct i915_fence_reg *fence)
126 {
127 u32 val;
128
129 val = 0;
130 if (fence->tiling) {
131 unsigned int stride = fence->stride;
132 unsigned int tiling = fence->tiling;
133 bool is_y_tiled = tiling == I915_TILING_Y;
134
135 if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence_to_i915(fence)))
136 stride /= 128;
137 else
138 stride /= 512;
139 GEM_BUG_ON(!is_power_of_2(stride));
140
141 val = fence->start;
142 if (is_y_tiled)
143 val |= BIT(I830_FENCE_TILING_Y_SHIFT);
144 val |= I915_FENCE_SIZE_BITS(fence->size);
145 val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT;
146
147 val |= I830_FENCE_REG_VALID;
148 }
149
150 if (!pipelined) {
151 struct intel_uncore *uncore = fence_to_uncore(fence);
152 i915_reg_t reg = FENCE_REG(fence->id);
153
154 intel_uncore_write_fw(uncore, reg, val);
155 intel_uncore_posting_read_fw(uncore, reg);
156 }
157 }
158
i830_write_fence_reg(struct i915_fence_reg * fence)159 static void i830_write_fence_reg(struct i915_fence_reg *fence)
160 {
161 u32 val;
162
163 val = 0;
164 if (fence->tiling) {
165 unsigned int stride = fence->stride;
166
167 val = fence->start;
168 if (fence->tiling == I915_TILING_Y)
169 val |= BIT(I830_FENCE_TILING_Y_SHIFT);
170 val |= I830_FENCE_SIZE_BITS(fence->size);
171 val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
172 val |= I830_FENCE_REG_VALID;
173 }
174
175 if (!pipelined) {
176 struct intel_uncore *uncore = fence_to_uncore(fence);
177 i915_reg_t reg = FENCE_REG(fence->id);
178
179 intel_uncore_write_fw(uncore, reg, val);
180 intel_uncore_posting_read_fw(uncore, reg);
181 }
182 }
183
fence_write(struct i915_fence_reg * fence)184 static void fence_write(struct i915_fence_reg *fence)
185 {
186 struct drm_i915_private *i915 = fence_to_i915(fence);
187
188 /*
189 * Previous access through the fence register is marshalled by
190 * the mb() inside the fault handlers (i915_gem_release_mmaps)
191 * and explicitly managed for internal users.
192 */
193
194 if (IS_GEN(i915, 2))
195 i830_write_fence_reg(fence);
196 else if (IS_GEN(i915, 3))
197 i915_write_fence_reg(fence);
198 else
199 i965_write_fence_reg(fence);
200
201 /*
202 * Access through the fenced region afterwards is
203 * ordered by the posting reads whilst writing the registers.
204 */
205 }
206
gpu_uses_fence_registers(struct i915_fence_reg * fence)207 static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
208 {
209 return INTEL_GEN(fence_to_i915(fence)) < 4;
210 }
211
fence_update(struct i915_fence_reg * fence,struct i915_vma * vma)212 static int fence_update(struct i915_fence_reg *fence,
213 struct i915_vma *vma)
214 {
215 struct i915_ggtt *ggtt = fence->ggtt;
216 struct intel_uncore *uncore = fence_to_uncore(fence);
217 intel_wakeref_t wakeref;
218 struct i915_vma *old;
219 int ret;
220
221 fence->tiling = 0;
222 if (vma) {
223 GEM_BUG_ON(!i915_gem_object_get_stride(vma->obj) ||
224 !i915_gem_object_get_tiling(vma->obj));
225
226 if (!i915_vma_is_map_and_fenceable(vma))
227 return -EINVAL;
228
229 if (gpu_uses_fence_registers(fence)) {
230 /* implicit 'unfenced' GPU blits */
231 ret = i915_vma_sync(vma);
232 if (ret)
233 return ret;
234 }
235
236 fence->start = vma->node.start;
237 fence->size = vma->fence_size;
238 fence->stride = i915_gem_object_get_stride(vma->obj);
239 fence->tiling = i915_gem_object_get_tiling(vma->obj);
240 }
241 WRITE_ONCE(fence->dirty, false);
242
243 old = xchg(&fence->vma, NULL);
244 if (old) {
245 /* XXX Ideally we would move the waiting to outside the mutex */
246 ret = i915_active_wait(&fence->active);
247 if (ret) {
248 fence->vma = old;
249 return ret;
250 }
251
252 i915_vma_flush_writes(old);
253
254 /*
255 * Ensure that all userspace CPU access is completed before
256 * stealing the fence.
257 */
258 if (old != vma) {
259 GEM_BUG_ON(old->fence != fence);
260 i915_vma_revoke_mmap(old);
261 old->fence = NULL;
262 }
263
264 list_move(&fence->link, &ggtt->fence_list);
265 }
266
267 /*
268 * We only need to update the register itself if the device is awake.
269 * If the device is currently powered down, we will defer the write
270 * to the runtime resume, see intel_ggtt_restore_fences().
271 *
272 * This only works for removing the fence register, on acquisition
273 * the caller must hold the rpm wakeref. The fence register must
274 * be cleared before we can use any other fences to ensure that
275 * the new fences do not overlap the elided clears, confusing HW.
276 */
277 wakeref = intel_runtime_pm_get_if_in_use(uncore->rpm);
278 if (!wakeref) {
279 GEM_BUG_ON(vma);
280 return 0;
281 }
282
283 WRITE_ONCE(fence->vma, vma);
284 fence_write(fence);
285
286 if (vma) {
287 vma->fence = fence;
288 list_move_tail(&fence->link, &ggtt->fence_list);
289 }
290
291 intel_runtime_pm_put(uncore->rpm, wakeref);
292 return 0;
293 }
294
295 /**
296 * i915_vma_revoke_fence - force-remove fence for a VMA
297 * @vma: vma to map linearly (not through a fence reg)
298 *
299 * This function force-removes any fence from the given object, which is useful
300 * if the kernel wants to do untiled GTT access.
301 */
i915_vma_revoke_fence(struct i915_vma * vma)302 void i915_vma_revoke_fence(struct i915_vma *vma)
303 {
304 struct i915_fence_reg *fence = vma->fence;
305 intel_wakeref_t wakeref;
306
307 lockdep_assert_held(&vma->vm->mutex);
308 if (!fence)
309 return;
310
311 GEM_BUG_ON(fence->vma != vma);
312 GEM_BUG_ON(!i915_active_is_idle(&fence->active));
313 GEM_BUG_ON(atomic_read(&fence->pin_count));
314
315 fence->tiling = 0;
316 WRITE_ONCE(fence->vma, NULL);
317 vma->fence = NULL;
318
319 /*
320 * Skip the write to HW if and only if the device is currently
321 * suspended.
322 *
323 * If the driver does not currently hold a wakeref (if_in_use == 0),
324 * the device may currently be runtime suspended, or it may be woken
325 * up before the suspend takes place. If the device is not suspended
326 * (powered down) and we skip clearing the fence register, the HW is
327 * left in an undefined state where we may end up with multiple
328 * registers overlapping.
329 */
330 with_intel_runtime_pm_if_active(fence_to_uncore(fence)->rpm, wakeref)
331 fence_write(fence);
332 }
333
fence_find(struct i915_ggtt * ggtt)334 static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt)
335 {
336 struct i915_fence_reg *fence;
337
338 list_for_each_entry(fence, &ggtt->fence_list, link) {
339 GEM_BUG_ON(fence->vma && fence->vma->fence != fence);
340
341 if (atomic_read(&fence->pin_count))
342 continue;
343
344 return fence;
345 }
346
347 /* Wait for completion of pending flips which consume fences */
348 if (intel_has_pending_fb_unpin(ggtt->vm.i915))
349 return ERR_PTR(-EAGAIN);
350
351 return ERR_PTR(-ENOBUFS);
352 }
353
__i915_vma_pin_fence(struct i915_vma * vma)354 int __i915_vma_pin_fence(struct i915_vma *vma)
355 {
356 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm);
357 struct i915_fence_reg *fence;
358 struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
359 int err;
360
361 lockdep_assert_held(&vma->vm->mutex);
362
363 /* Just update our place in the LRU if our fence is getting reused. */
364 if (vma->fence) {
365 fence = vma->fence;
366 GEM_BUG_ON(fence->vma != vma);
367 atomic_inc(&fence->pin_count);
368 if (!fence->dirty) {
369 list_move_tail(&fence->link, &ggtt->fence_list);
370 return 0;
371 }
372 } else if (set) {
373 fence = fence_find(ggtt);
374 if (IS_ERR(fence))
375 return PTR_ERR(fence);
376
377 GEM_BUG_ON(atomic_read(&fence->pin_count));
378 atomic_inc(&fence->pin_count);
379 } else {
380 return 0;
381 }
382
383 err = fence_update(fence, set);
384 if (err)
385 goto out_unpin;
386
387 GEM_BUG_ON(fence->vma != set);
388 GEM_BUG_ON(vma->fence != (set ? fence : NULL));
389
390 if (set)
391 return 0;
392
393 out_unpin:
394 atomic_dec(&fence->pin_count);
395 return err;
396 }
397
398 /**
399 * i915_vma_pin_fence - set up fencing for a vma
400 * @vma: vma to map through a fence reg
401 *
402 * When mapping objects through the GTT, userspace wants to be able to write
403 * to them without having to worry about swizzling if the object is tiled.
404 * This function walks the fence regs looking for a free one for @obj,
405 * stealing one if it can't find any.
406 *
407 * It then sets up the reg based on the object's properties: address, pitch
408 * and tiling format.
409 *
410 * For an untiled surface, this removes any existing fence.
411 *
412 * Returns:
413 *
414 * 0 on success, negative error code on failure.
415 */
i915_vma_pin_fence(struct i915_vma * vma)416 int i915_vma_pin_fence(struct i915_vma *vma)
417 {
418 int err;
419
420 if (!vma->fence && !i915_gem_object_is_tiled(vma->obj))
421 return 0;
422
423 /*
424 * Note that we revoke fences on runtime suspend. Therefore the user
425 * must keep the device awake whilst using the fence.
426 */
427 assert_rpm_wakelock_held(vma->vm->gt->uncore->rpm);
428 GEM_BUG_ON(!i915_vma_is_pinned(vma));
429 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
430
431 err = mutex_lock_interruptible(&vma->vm->mutex);
432 if (err)
433 return err;
434
435 err = __i915_vma_pin_fence(vma);
436 mutex_unlock(&vma->vm->mutex);
437
438 return err;
439 }
440
441 /**
442 * i915_reserve_fence - Reserve a fence for vGPU
443 * @ggtt: Global GTT
444 *
445 * This function walks the fence regs looking for a free one and remove
446 * it from the fence_list. It is used to reserve fence for vGPU to use.
447 */
i915_reserve_fence(struct i915_ggtt * ggtt)448 struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt)
449 {
450 struct i915_fence_reg *fence;
451 int count;
452 int ret;
453
454 lockdep_assert_held(&ggtt->vm.mutex);
455
456 /* Keep at least one fence available for the display engine. */
457 count = 0;
458 list_for_each_entry(fence, &ggtt->fence_list, link)
459 count += !atomic_read(&fence->pin_count);
460 if (count <= 1)
461 return ERR_PTR(-ENOSPC);
462
463 fence = fence_find(ggtt);
464 if (IS_ERR(fence))
465 return fence;
466
467 if (fence->vma) {
468 /* Force-remove fence from VMA */
469 ret = fence_update(fence, NULL);
470 if (ret)
471 return ERR_PTR(ret);
472 }
473
474 list_del(&fence->link);
475
476 return fence;
477 }
478
479 /**
480 * i915_unreserve_fence - Reclaim a reserved fence
481 * @fence: the fence reg
482 *
483 * This function add a reserved fence register from vGPU to the fence_list.
484 */
i915_unreserve_fence(struct i915_fence_reg * fence)485 void i915_unreserve_fence(struct i915_fence_reg *fence)
486 {
487 struct i915_ggtt *ggtt = fence->ggtt;
488
489 lockdep_assert_held(&ggtt->vm.mutex);
490
491 list_add(&fence->link, &ggtt->fence_list);
492 }
493
494 /**
495 * intel_ggtt_restore_fences - restore fence state
496 * @ggtt: Global GTT
497 *
498 * Restore the hw fence state to match the software tracking again, to be called
499 * after a gpu reset and on resume. Note that on runtime suspend we only cancel
500 * the fences, to be reacquired by the user later.
501 */
intel_ggtt_restore_fences(struct i915_ggtt * ggtt)502 void intel_ggtt_restore_fences(struct i915_ggtt *ggtt)
503 {
504 int i;
505
506 for (i = 0; i < ggtt->num_fences; i++)
507 fence_write(&ggtt->fence_regs[i]);
508 }
509
510 /**
511 * DOC: tiling swizzling details
512 *
513 * The idea behind tiling is to increase cache hit rates by rearranging
514 * pixel data so that a group of pixel accesses are in the same cacheline.
515 * Performance improvement from doing this on the back/depth buffer are on
516 * the order of 30%.
517 *
518 * Intel architectures make this somewhat more complicated, though, by
519 * adjustments made to addressing of data when the memory is in interleaved
520 * mode (matched pairs of DIMMS) to improve memory bandwidth.
521 * For interleaved memory, the CPU sends every sequential 64 bytes
522 * to an alternate memory channel so it can get the bandwidth from both.
523 *
524 * The GPU also rearranges its accesses for increased bandwidth to interleaved
525 * memory, and it matches what the CPU does for non-tiled. However, when tiled
526 * it does it a little differently, since one walks addresses not just in the
527 * X direction but also Y. So, along with alternating channels when bit
528 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
529 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
530 * are common to both the 915 and 965-class hardware.
531 *
532 * The CPU also sometimes XORs in higher bits as well, to improve
533 * bandwidth doing strided access like we do so frequently in graphics. This
534 * is called "Channel XOR Randomization" in the MCH documentation. The result
535 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
536 * decode.
537 *
538 * All of this bit 6 XORing has an effect on our memory management,
539 * as we need to make sure that the 3d driver can correctly address object
540 * contents.
541 *
542 * If we don't have interleaved memory, all tiling is safe and no swizzling is
543 * required.
544 *
545 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
546 * 17 is not just a page offset, so as we page an object out and back in,
547 * individual pages in it will have different bit 17 addresses, resulting in
548 * each 64 bytes being swapped with its neighbor!
549 *
550 * Otherwise, if interleaved, we have to tell the 3d driver what the address
551 * swizzling it needs to do is, since it's writing with the CPU to the pages
552 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
553 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
554 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
555 * to match what the GPU expects.
556 */
557
558 /**
559 * detect_bit_6_swizzle - detect bit 6 swizzling pattern
560 * @ggtt: Global GGTT
561 *
562 * Detects bit 6 swizzling of address lookup between IGD access and CPU
563 * access through main memory.
564 */
detect_bit_6_swizzle(struct i915_ggtt * ggtt)565 static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
566 {
567 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
568 struct drm_i915_private *i915 = ggtt->vm.i915;
569 u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
570 u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
571
572 if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
573 /*
574 * On BDW+, swizzling is not used. We leave the CPU memory
575 * controller in charge of optimizing memory accesses without
576 * the extra address manipulation GPU side.
577 *
578 * VLV and CHV don't have GPU swizzling.
579 */
580 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
581 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
582 } else if (INTEL_GEN(i915) >= 6) {
583 if (i915->preserve_bios_swizzle) {
584 if (intel_uncore_read(uncore, DISP_ARB_CTL) &
585 DISP_TILE_SURFACE_SWIZZLING) {
586 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
587 swizzle_y = I915_BIT_6_SWIZZLE_9;
588 } else {
589 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
590 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
591 }
592 } else {
593 u32 dimm_c0, dimm_c1;
594 dimm_c0 = intel_uncore_read(uncore, MAD_DIMM_C0);
595 dimm_c1 = intel_uncore_read(uncore, MAD_DIMM_C1);
596 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
597 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
598 /*
599 * Enable swizzling when the channels are populated
600 * with identically sized dimms. We don't need to check
601 * the 3rd channel because no cpu with gpu attached
602 * ships in that configuration. Also, swizzling only
603 * makes sense for 2 channels anyway.
604 */
605 if (dimm_c0 == dimm_c1) {
606 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
607 swizzle_y = I915_BIT_6_SWIZZLE_9;
608 } else {
609 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
610 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
611 }
612 }
613 } else if (IS_GEN(i915, 5)) {
614 /*
615 * On Ironlake whatever DRAM config, GPU always do
616 * same swizzling setup.
617 */
618 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
619 swizzle_y = I915_BIT_6_SWIZZLE_9;
620 } else if (IS_GEN(i915, 2)) {
621 /*
622 * As far as we know, the 865 doesn't have these bit 6
623 * swizzling issues.
624 */
625 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
626 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
627 } else if (IS_G45(i915) || IS_I965G(i915) || IS_G33(i915)) {
628 /*
629 * The 965, G33, and newer, have a very flexible memory
630 * configuration. It will enable dual-channel mode
631 * (interleaving) on as much memory as it can, and the GPU
632 * will additionally sometimes enable different bit 6
633 * swizzling for tiled objects from the CPU.
634 *
635 * Here's what I found on the G965:
636 * slot fill memory size swizzling
637 * 0A 0B 1A 1B 1-ch 2-ch
638 * 512 0 0 0 512 0 O
639 * 512 0 512 0 16 1008 X
640 * 512 0 0 512 16 1008 X
641 * 0 512 0 512 16 1008 X
642 * 1024 1024 1024 0 2048 1024 O
643 *
644 * We could probably detect this based on either the DRB
645 * matching, which was the case for the swizzling required in
646 * the table above, or from the 1-ch value being less than
647 * the minimum size of a rank.
648 *
649 * Reports indicate that the swizzling actually
650 * varies depending upon page placement inside the
651 * channels, i.e. we see swizzled pages where the
652 * banks of memory are paired and unswizzled on the
653 * uneven portion, so leave that as unknown.
654 */
655 if (intel_uncore_read16(uncore, C0DRB3) ==
656 intel_uncore_read16(uncore, C1DRB3)) {
657 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
658 swizzle_y = I915_BIT_6_SWIZZLE_9;
659 }
660 } else {
661 u32 dcc = intel_uncore_read(uncore, DCC);
662
663 /*
664 * On 9xx chipsets, channel interleave by the CPU is
665 * determined by DCC. For single-channel, neither the CPU
666 * nor the GPU do swizzling. For dual channel interleaved,
667 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
668 * 9 for Y tiled. The CPU's interleave is independent, and
669 * can be based on either bit 11 (haven't seen this yet) or
670 * bit 17 (common).
671 */
672 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
673 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
674 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
675 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
676 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
677 break;
678 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
679 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
680 /*
681 * This is the base swizzling by the GPU for
682 * tiled buffers.
683 */
684 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
685 swizzle_y = I915_BIT_6_SWIZZLE_9;
686 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
687 /* Bit 11 swizzling by the CPU in addition. */
688 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
689 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
690 } else {
691 /* Bit 17 swizzling by the CPU in addition. */
692 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
693 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
694 }
695 break;
696 }
697
698 /* check for L-shaped memory aka modified enhanced addressing */
699 if (IS_GEN(i915, 4) &&
700 !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
701 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
702 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
703 }
704
705 if (dcc == 0xffffffff) {
706 drm_err(&i915->drm, "Couldn't read from MCHBAR. "
707 "Disabling tiling.\n");
708 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
709 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
710 }
711 }
712
713 if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||
714 swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) {
715 /*
716 * Userspace likes to explode if it sees unknown swizzling,
717 * so lie. We will finish the lie when reporting through
718 * the get-tiling-ioctl by reporting the physical swizzle
719 * mode as unknown instead.
720 *
721 * As we don't strictly know what the swizzling is, it may be
722 * bit17 dependent, and so we need to also prevent the pages
723 * from being moved.
724 */
725 i915->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
726 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
727 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
728 }
729
730 i915->ggtt.bit_6_swizzle_x = swizzle_x;
731 i915->ggtt.bit_6_swizzle_y = swizzle_y;
732 }
733
734 /*
735 * Swap every 64 bytes of this page around, to account for it having a new
736 * bit 17 of its physical address and therefore being interpreted differently
737 * by the GPU.
738 */
swizzle_page(struct page * page)739 static void swizzle_page(struct page *page)
740 {
741 char temp[64];
742 char *vaddr;
743 int i;
744
745 vaddr = kmap(page);
746
747 for (i = 0; i < PAGE_SIZE; i += 128) {
748 memcpy(temp, &vaddr[i], 64);
749 memcpy(&vaddr[i], &vaddr[i + 64], 64);
750 memcpy(&vaddr[i + 64], temp, 64);
751 }
752
753 kunmap(page);
754 }
755
756 /**
757 * i915_gem_object_do_bit_17_swizzle - fixup bit 17 swizzling
758 * @obj: i915 GEM buffer object
759 * @pages: the scattergather list of physical pages
760 *
761 * This function fixes up the swizzling in case any page frame number for this
762 * object has changed in bit 17 since that state has been saved with
763 * i915_gem_object_save_bit_17_swizzle().
764 *
765 * This is called when pinning backing storage again, since the kernel is free
766 * to move unpinned backing storage around (either by directly moving pages or
767 * by swapping them out and back in again).
768 */
769 void
i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object * obj,struct sg_table * pages)770 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
771 struct sg_table *pages)
772 {
773 struct sgt_iter sgt_iter;
774 struct page *page;
775 int i;
776
777 if (obj->bit_17 == NULL)
778 return;
779
780 i = 0;
781 for_each_sgt_page(page, sgt_iter, pages) {
782 char new_bit_17 = page_to_phys(page) >> 17;
783 if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) {
784 swizzle_page(page);
785 set_page_dirty(page);
786 }
787 i++;
788 }
789 }
790
791 /**
792 * i915_gem_object_save_bit_17_swizzle - save bit 17 swizzling
793 * @obj: i915 GEM buffer object
794 * @pages: the scattergather list of physical pages
795 *
796 * This function saves the bit 17 of each page frame number so that swizzling
797 * can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must
798 * be called before the backing storage can be unpinned.
799 */
800 void
i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object * obj,struct sg_table * pages)801 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
802 struct sg_table *pages)
803 {
804 const unsigned int page_count = obj->base.size >> PAGE_SHIFT;
805 struct sgt_iter sgt_iter;
806 struct page *page;
807 int i;
808
809 if (obj->bit_17 == NULL) {
810 obj->bit_17 = bitmap_zalloc(page_count, GFP_KERNEL);
811 if (obj->bit_17 == NULL) {
812 DRM_ERROR("Failed to allocate memory for bit 17 "
813 "record\n");
814 return;
815 }
816 }
817
818 i = 0;
819
820 for_each_sgt_page(page, sgt_iter, pages) {
821 if (page_to_phys(page) & (1 << 17))
822 __set_bit(i, obj->bit_17);
823 else
824 __clear_bit(i, obj->bit_17);
825 i++;
826 }
827 }
828
intel_ggtt_init_fences(struct i915_ggtt * ggtt)829 void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
830 {
831 struct drm_i915_private *i915 = ggtt->vm.i915;
832 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
833 int num_fences;
834 int i;
835
836 INIT_LIST_HEAD(&ggtt->fence_list);
837 INIT_LIST_HEAD(&ggtt->userfault_list);
838 intel_wakeref_auto_init(&ggtt->userfault_wakeref, uncore->rpm);
839
840 detect_bit_6_swizzle(ggtt);
841
842 if (!i915_ggtt_has_aperture(ggtt))
843 num_fences = 0;
844 else if (INTEL_GEN(i915) >= 7 &&
845 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
846 num_fences = 32;
847 else if (INTEL_GEN(i915) >= 4 ||
848 IS_I945G(i915) || IS_I945GM(i915) ||
849 IS_G33(i915) || IS_PINEVIEW(i915))
850 num_fences = 16;
851 else
852 num_fences = 8;
853
854 if (intel_vgpu_active(i915))
855 num_fences = intel_uncore_read(uncore,
856 vgtif_reg(avail_rs.fence_num));
857 ggtt->fence_regs = kcalloc(num_fences,
858 sizeof(*ggtt->fence_regs),
859 GFP_KERNEL);
860 if (!ggtt->fence_regs)
861 num_fences = 0;
862
863 /* Initialize fence registers to zero */
864 for (i = 0; i < num_fences; i++) {
865 struct i915_fence_reg *fence = &ggtt->fence_regs[i];
866
867 i915_active_init(&fence->active, NULL, NULL);
868 fence->ggtt = ggtt;
869 fence->id = i;
870 list_add_tail(&fence->link, &ggtt->fence_list);
871 }
872 ggtt->num_fences = num_fences;
873
874 intel_ggtt_restore_fences(ggtt);
875 }
876
intel_ggtt_fini_fences(struct i915_ggtt * ggtt)877 void intel_ggtt_fini_fences(struct i915_ggtt *ggtt)
878 {
879 int i;
880
881 for (i = 0; i < ggtt->num_fences; i++) {
882 struct i915_fence_reg *fence = &ggtt->fence_regs[i];
883
884 i915_active_fini(&fence->active);
885 }
886
887 kfree(ggtt->fence_regs);
888 }
889
intel_gt_init_swizzling(struct intel_gt * gt)890 void intel_gt_init_swizzling(struct intel_gt *gt)
891 {
892 struct drm_i915_private *i915 = gt->i915;
893 struct intel_uncore *uncore = gt->uncore;
894
895 if (INTEL_GEN(i915) < 5 ||
896 i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
897 return;
898
899 intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
900
901 if (IS_GEN(i915, 5))
902 return;
903
904 intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
905
906 if (IS_GEN(i915, 6))
907 intel_uncore_write(uncore,
908 ARB_MODE,
909 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
910 else if (IS_GEN(i915, 7))
911 intel_uncore_write(uncore,
912 ARB_MODE,
913 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
914 else if (IS_GEN(i915, 8))
915 intel_uncore_write(uncore,
916 GAMTARBMODE,
917 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
918 else
919 MISSING_CASE(INTEL_GEN(i915));
920 }
921