1 /*
2 * Copyright (c) 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "isl_gfx9.h"
25 #include "isl_gfx12.h"
26 #include "isl_priv.h"
27
28 /**
29 * @brief Filter out tiling flags that are incompatible with the surface.
30 *
31 * The resultant outgoing @a flags is a subset of the incoming @a flags. The
32 * outgoing flags may be empty (0x0) if the incoming flags were too
33 * restrictive.
34 *
35 * For example, if the surface will be used for a display
36 * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling
37 * flags except ISL_TILING_4_BIT, ISL_TILING_X_BIT, and ISL_TILING_LINEAR_BIT.
38 */
39 void
isl_gfx125_filter_tiling(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,isl_tiling_flags_t * flags)40 isl_gfx125_filter_tiling(const struct isl_device *dev,
41 const struct isl_surf_init_info *restrict info,
42 isl_tiling_flags_t *flags)
43 {
44 /* Clear flags unsupported on this hardware */
45 assert(ISL_GFX_VERX10(dev) >= 125);
46 *flags &= ISL_TILING_LINEAR_BIT |
47 ISL_TILING_X_BIT |
48 ISL_TILING_4_BIT |
49 ISL_TILING_64_BIT;
50
51 if (isl_surf_usage_is_depth_or_stencil(info->usage))
52 *flags &= ISL_TILING_4_BIT | ISL_TILING_64_BIT;
53
54 if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT)
55 *flags &= ~ISL_TILING_64_BIT;
56
57 /* From RENDER_SURFACE_STATE::AuxiliarySurfaceMode,
58 *
59 * MCS tiling format is always Tile4
60 */
61 if (info->usage & ISL_SURF_USAGE_MCS_BIT)
62 *flags &= ISL_TILING_4_BIT;
63
64 /* From RENDER_SURFACE_STATE::TileMode,
65 *
66 * TILEMODE_XMAJOR is only allowed if Surface Type is SURFTYPE_2D.
67 *
68 * X-tiling is only allowed for 2D surfaces.
69 */
70 if (info->dim != ISL_SURF_DIM_2D)
71 *flags &= ~ISL_TILING_X_BIT;
72
73 /* ISL only implements Tile64 support for 2D surfaces. */
74 if (info->dim != ISL_SURF_DIM_2D)
75 *flags &= ~ISL_TILING_64_BIT;
76
77 /* From RENDER_SURFACE_STATE::NumberofMultisamples,
78 *
79 * This field must not be programmed to anything other than
80 * [MULTISAMPLECOUNT_1] unless the Tile Mode field is programmed to
81 * Tile64.
82 *
83 * Tile64 is required for multisampling.
84 */
85 if (info->samples > 1)
86 *flags &= ISL_TILING_64_BIT;
87
88 /* Tile64 is not defined for format sizes that are 24, 48, and 96 bpb. */
89 if (isl_format_get_layout(info->format)->bpb % 3 == 0)
90 *flags &= ~ISL_TILING_64_BIT;
91
92 /* BSpec 46962: 3DSTATE_CPSIZE_CONTROL_BUFFER::Tiled Mode : TILE4 & TILE64
93 * are the only 2 valid values.
94 *
95 * TODO: For now we only TILE64 as we need to figure out potential
96 * additional requirements for TILE4.
97 */
98 if (info->usage & ISL_SURF_USAGE_CPB_BIT)
99 *flags &= ISL_TILING_64_BIT;
100 }
101
102 void
isl_gfx125_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_tiling tiling,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)103 isl_gfx125_choose_image_alignment_el(const struct isl_device *dev,
104 const struct isl_surf_init_info *restrict info,
105 enum isl_tiling tiling,
106 enum isl_dim_layout dim_layout,
107 enum isl_msaa_layout msaa_layout,
108 struct isl_extent3d *image_align_el)
109 {
110 /* Handled by isl_choose_image_alignment_el */
111 assert(info->format != ISL_FORMAT_GFX125_HIZ);
112
113 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
114
115 if (tiling == ISL_TILING_64) {
116 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
117 *
118 * This field is ignored for Tile64 surface formats because horizontal
119 * alignment is always to the start of the next tile in that case.
120 *
121 * From RENDER_SURFACE_STATE::SurfaceQPitch,
122 *
123 * Because MSAA is only supported for Tile64, QPitch must also be
124 * programmed to an aligned tile boundary for MSAA surfaces.
125 *
126 * Images in this surface must be tile-aligned. The table on the Bspec
127 * page, "2D/CUBE Alignment Requirement", shows that the vertical
128 * alignment is also a tile height for non-MSAA as well.
129 */
130 struct isl_tile_info tile_info;
131 isl_tiling_get_info(tiling, info->dim, msaa_layout, fmtl->bpb,
132 info->samples, &tile_info);
133
134 *image_align_el = isl_extent3d(tile_info.logical_extent_el.w,
135 tile_info.logical_extent_el.h,
136 1);
137 } else if (isl_surf_usage_is_depth(info->usage)) {
138 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
139 *
140 * - 16b Depth Surfaces Must Be HALIGN=16Bytes (8texels)
141 * - 32b Depth Surfaces Must Be HALIGN=32Bytes (8texels)
142 *
143 * From RENDER_SURFACE_STATE::SurfaceVerticalAlignment,
144 *
145 * This field is intended to be set to VALIGN_4 if the surface
146 * was rendered as a depth buffer [...]
147 *
148 * and
149 *
150 * This field should also be set to VALIGN_8 if the surface was
151 * rendered as a D16_UNORM depth buffer [...]
152 */
153 *image_align_el =
154 info->format != ISL_FORMAT_R16_UNORM ?
155 isl_extent3d(8, 4, 1) :
156 isl_extent3d(8, 8, 1);
157 } else if (isl_surf_usage_is_stencil(info->usage)) {
158 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
159 *
160 * - Stencil Surfaces (8b) Must be HALIGN=16Bytes (16texels)
161 *
162 * From RENDER_SURFACE_STATE::SurfaceVerticalAlignment,
163 *
164 * This field is intended to be set to VALIGN_8 only if
165 * the surface was rendered as a stencil buffer, since stencil buffer
166 * surfaces support only alignment of 8.
167 */
168 *image_align_el = isl_extent3d(16, 8, 1);
169 } else if (!isl_is_pow2(fmtl->bpb)) {
170 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
171 *
172 * - Linear Surfaces surfaces must use HALIGN=128, including 1D which
173 * is always Linear. For 24,48 and 96bpp this means 128texels.
174 * - Tiled 24bpp, 48bpp and 96bpp surfaces must use HALIGN=16
175 */
176 *image_align_el = tiling == ISL_TILING_LINEAR ?
177 isl_extent3d(128, 4, 1) :
178 isl_extent3d(16, 4, 1);
179 } else {
180 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
181 *
182 * - Losslessly Compressed Surfaces Must be HALIGN=128 for all
183 * supported Bpp
184 * - 64bpe and 128bpe Surfaces Must Be HALIGN=64Bytes or 128Bytes (4,
185 * 8 texels or 16 texels)
186 * - Linear Surfaces surfaces must use HALIGN=128, including 1D which
187 * is always Linear.
188 *
189 * Even though we could choose a horizontal alignment of 64B for certain
190 * 64 and 128-bit formats, we want to be able to enable CCS whenever
191 * possible and CCS requires 128B horizontal alignment.
192 */
193 *image_align_el = isl_extent3d(128 * 8 / fmtl->bpb, 4, 1);
194 }
195 }
196
197 void
isl_gfx12_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_tiling tiling,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)198 isl_gfx12_choose_image_alignment_el(const struct isl_device *dev,
199 const struct isl_surf_init_info *restrict info,
200 enum isl_tiling tiling,
201 enum isl_dim_layout dim_layout,
202 enum isl_msaa_layout msaa_layout,
203 struct isl_extent3d *image_align_el)
204 {
205 /* Handled by isl_choose_image_alignment_el */
206 assert(info->format != ISL_FORMAT_HIZ);
207
208 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
209 if (fmtl->txc == ISL_TXC_CCS) {
210 /* This CCS compresses a 2D-view of the entire surface. */
211 assert(info->levels == 1 && info->array_len == 1 && info->depth == 1);
212 *image_align_el = isl_extent3d(1, 1, 1);
213 return;
214 }
215
216 if (isl_surf_usage_is_depth(info->usage)) {
217 /* The alignment parameters for depth buffers are summarized in the
218 * following table:
219 *
220 * Surface Format | MSAA | Align Width | Align Height
221 * -----------------+-------------+-------------+--------------
222 * D16_UNORM | 1x, 4x, 16x | 8 | 8
223 * ----------------+-------------+-------------+--------------
224 * D16_UNORM | 2x, 8x | 16 | 4
225 * ----------------+-------------+-------------+--------------
226 * other | any | 8 | 4
227 * -----------------+-------------+-------------+--------------
228 */
229 assert(isl_is_pow2(info->samples));
230 *image_align_el =
231 info->format != ISL_FORMAT_R16_UNORM ?
232 isl_extent3d(8, 4, 1) :
233 (info->samples == 2 || info->samples == 8 ?
234 isl_extent3d(16, 4, 1) : isl_extent3d(8, 8, 1));
235 } else if (isl_surf_usage_is_stencil(info->usage)) {
236 *image_align_el = isl_extent3d(16, 8, 1);
237 } else {
238 isl_gfx9_choose_image_alignment_el(dev, info, tiling, dim_layout,
239 msaa_layout, image_align_el);
240 }
241 }
242