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1 // Copyright 2017, VIXL authors
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 //   * Redistributions of source code must retain the above copyright notice,
8 //     this list of conditions and the following disclaimer.
9 //   * Redistributions in binary form must reproduce the above copyright notice,
10 //     this list of conditions and the following disclaimer in the documentation
11 //     and/or other materials provided with the distribution.
12 //   * Neither the name of ARM Limited nor the names of its contributors may be
13 //     used to endorse or promote products derived from this software without
14 //     specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 
27 #ifndef VIXL_AARCH32_ASSEMBLER_AARCH32_H_
28 #define VIXL_AARCH32_ASSEMBLER_AARCH32_H_
29 
30 #include "assembler-base-vixl.h"
31 
32 #include "aarch32/instructions-aarch32.h"
33 #include "aarch32/location-aarch32.h"
34 
35 namespace vixl {
36 namespace aarch32 {
37 
38 class Assembler : public internal::AssemblerBase {
39   InstructionSet isa_;
40   Condition first_condition_;
41   uint16_t it_mask_;
42   bool has_32_dregs_;
43   bool allow_unpredictable_;
44   bool allow_strongly_discouraged_;
45 
46  protected:
47   void EmitT32_16(uint16_t instr);
48   void EmitT32_32(uint32_t instr);
49   void EmitA32(uint32_t instr);
50   // Check that the condition of the current instruction is consistent with the
51   // IT state.
CheckIT(Condition condition)52   void CheckIT(Condition condition) {
53 #ifdef VIXL_DEBUG
54     PerformCheckIT(condition);
55 #else
56     USE(condition);
57 #endif
58   }
59 #ifdef VIXL_DEBUG
60   void PerformCheckIT(Condition condition);
61 #endif
AdvanceIT()62   void AdvanceIT() {
63     first_condition_ =
64         Condition((first_condition_.GetCondition() & 0xe) | (it_mask_ >> 3));
65     it_mask_ = (it_mask_ << 1) & 0xf;
66   }
67   // Virtual, in order to be overridden by the MacroAssembler, which needs to
68   // notify the pool manager.
69   virtual void BindHelper(Label* label);
70 
71   uint32_t Link(uint32_t instr,
72                 Location* location,
73                 const Location::EmitOperator& op,
74                 const ReferenceInfo* info);
75 
76  public:
77   class AllowUnpredictableScope {
78     Assembler* assembler_;
79     bool old_;
80 
81    public:
AllowUnpredictableScope(Assembler * assembler)82     explicit AllowUnpredictableScope(Assembler* assembler)
83         : assembler_(assembler), old_(assembler->allow_unpredictable_) {
84       assembler_->allow_unpredictable_ = true;
85     }
~AllowUnpredictableScope()86     ~AllowUnpredictableScope() { assembler_->allow_unpredictable_ = old_; }
87   };
88   class AllowStronglyDiscouragedScope {
89     Assembler* assembler_;
90     bool old_;
91 
92    public:
AllowStronglyDiscouragedScope(Assembler * assembler)93     explicit AllowStronglyDiscouragedScope(Assembler* assembler)
94         : assembler_(assembler), old_(assembler->allow_strongly_discouraged_) {
95       assembler_->allow_strongly_discouraged_ = true;
96     }
~AllowStronglyDiscouragedScope()97     ~AllowStronglyDiscouragedScope() {
98       assembler_->allow_strongly_discouraged_ = old_;
99     }
100   };
101 
102     explicit Assembler(InstructionSet isa = kDefaultISA)
isa_(isa)103       : isa_(isa),
104         first_condition_(al),
105         it_mask_(0),
106         has_32_dregs_(true),
107         allow_unpredictable_(false),
108         allow_strongly_discouraged_(false) {
109 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
110     // Avoid compiler warning.
111     USE(isa_);
112     VIXL_ASSERT(isa == A32);
113 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
114     USE(isa_);
115     VIXL_ASSERT(isa == T32);
116 #endif
117   }
118 
119 #ifdef PANDA_BUILD
120   explicit Assembler(size_t capacity, InstructionSet isa = kDefaultISA) = delete;
121 #else
122   explicit Assembler(size_t capacity, InstructionSet isa = kDefaultISA)
AssemblerBase(capacity)123       : AssemblerBase(capacity),
124         isa_(isa),
125         first_condition_(al),
126         it_mask_(0),
127         has_32_dregs_(true),
128         allow_unpredictable_(false),
129         allow_strongly_discouraged_(false) {
130 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
131     VIXL_ASSERT(isa == A32);
132 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
133     VIXL_ASSERT(isa == T32);
134 #endif
135   }
136 #endif
137 
138 
139   Assembler(byte* buffer, size_t capacity, InstructionSet isa = kDefaultISA)
AssemblerBase(buffer,capacity)140       : AssemblerBase(buffer, capacity),
141         isa_(isa),
142         first_condition_(al),
143         it_mask_(0),
144         has_32_dregs_(true),
145         allow_unpredictable_(false),
146         allow_strongly_discouraged_(false) {
147 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
148     VIXL_ASSERT(isa == A32);
149 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
150     VIXL_ASSERT(isa == T32);
151 #endif
152     USE(isa_);
153   }
~Assembler()154   virtual ~Assembler() {}
155 
UseInstructionSet(InstructionSet isa)156   void UseInstructionSet(InstructionSet isa) {
157 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
158     USE(isa);
159     VIXL_ASSERT(isa == A32);
160 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
161     USE(isa);
162     VIXL_ASSERT(isa == T32);
163 #else
164     VIXL_ASSERT((isa_ == isa) || (GetCursorOffset() == 0));
165     isa_ = isa;
166 #endif
167   }
168 
169 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
GetInstructionSetInUse()170   InstructionSet GetInstructionSetInUse() const { return A32; }
171 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
GetInstructionSetInUse()172   InstructionSet GetInstructionSetInUse() const { return T32; }
173 #else
GetInstructionSetInUse()174   InstructionSet GetInstructionSetInUse() const { return isa_; }
175 #endif
176 
UseT32()177   void UseT32() { UseInstructionSet(T32); }
UseA32()178   void UseA32() { UseInstructionSet(A32); }
IsUsingT32()179   bool IsUsingT32() const { return GetInstructionSetInUse() == T32; }
IsUsingA32()180   bool IsUsingA32() const { return GetInstructionSetInUse() == A32; }
181 
SetIT(Condition first_condition,uint16_t it_mask)182   void SetIT(Condition first_condition, uint16_t it_mask) {
183     VIXL_ASSERT(it_mask_ == 0);
184     first_condition_ = first_condition;
185     it_mask_ = it_mask;
186   }
InITBlock()187   bool InITBlock() { return it_mask_ != 0; }
OutsideITBlock()188   bool OutsideITBlock() { return it_mask_ == 0; }
OutsideITBlockOrLast()189   bool OutsideITBlockOrLast() { return (it_mask_ == 0) || (it_mask_ == 0x8); }
OutsideITBlockAndAlOrLast(Condition cond)190   bool OutsideITBlockAndAlOrLast(Condition cond) {
191     return ((it_mask_ == 0) && cond.Is(al)) || (it_mask_ == 0x8);
192   }
CheckNotIT()193   void CheckNotIT() { VIXL_ASSERT(it_mask_ == 0); }
Has32DRegs()194   bool Has32DRegs() const { return has_32_dregs_; }
SetHas32DRegs(bool has_32_dregs)195   void SetHas32DRegs(bool has_32_dregs) { has_32_dregs_ = has_32_dregs; }
196 
GetCursorOffset()197   int32_t GetCursorOffset() const {
198     ptrdiff_t offset = buffer_.GetCursorOffset();
199     VIXL_ASSERT(IsInt32(offset));
200     return static_cast<int32_t>(offset);
201   }
202 
GetArchitectureStatePCOffset()203   uint32_t GetArchitectureStatePCOffset() const { return IsUsingT32() ? 4 : 8; }
204 
205   // Bind a raw Location that will never be tracked by the pool manager.
bind(Location * location)206   void bind(Location* location) {
207     VIXL_ASSERT(AllowAssembler());
208     VIXL_ASSERT(!location->IsBound());
209     location->SetLocation(this, GetCursorOffset());
210     location->MarkBound();
211   }
212 
213   // Bind a Label, which may be tracked by the pool manager in the presence of a
214   // MacroAssembler.
bind(Label * label)215   void bind(Label* label) {
216     VIXL_ASSERT(AllowAssembler());
217     BindHelper(label);
218   }
219 
place(RawLiteral * literal)220   void place(RawLiteral* literal) {
221     VIXL_ASSERT(AllowAssembler());
222     VIXL_ASSERT(literal->IsManuallyPlaced());
223     literal->SetLocation(this, GetCursorOffset());
224     literal->MarkBound();
225     GetBuffer()->EnsureSpaceFor(literal->GetSize());
226     GetBuffer()->EmitData(literal->GetDataAddress(), literal->GetSize());
227   }
228 
GetSizeOfCodeGeneratedSince(Label * label)229   size_t GetSizeOfCodeGeneratedSince(Label* label) const {
230     VIXL_ASSERT(label->IsBound());
231     return buffer_.GetOffsetFrom(label->GetLocation());
232   }
233 
234   // Helpers for it instruction.
it(Condition cond)235   void it(Condition cond) { it(cond, 0x8); }
itt(Condition cond)236   void itt(Condition cond) { it(cond, 0x4); }
ite(Condition cond)237   void ite(Condition cond) { it(cond, 0xc); }
ittt(Condition cond)238   void ittt(Condition cond) { it(cond, 0x2); }
itet(Condition cond)239   void itet(Condition cond) { it(cond, 0xa); }
itte(Condition cond)240   void itte(Condition cond) { it(cond, 0x6); }
itee(Condition cond)241   void itee(Condition cond) { it(cond, 0xe); }
itttt(Condition cond)242   void itttt(Condition cond) { it(cond, 0x1); }
itett(Condition cond)243   void itett(Condition cond) { it(cond, 0x9); }
ittet(Condition cond)244   void ittet(Condition cond) { it(cond, 0x5); }
iteet(Condition cond)245   void iteet(Condition cond) { it(cond, 0xd); }
ittte(Condition cond)246   void ittte(Condition cond) { it(cond, 0x3); }
itete(Condition cond)247   void itete(Condition cond) { it(cond, 0xb); }
ittee(Condition cond)248   void ittee(Condition cond) { it(cond, 0x7); }
iteee(Condition cond)249   void iteee(Condition cond) { it(cond, 0xf); }
250 
251   // Start of generated code.
252   typedef void (Assembler::*InstructionCondSizeRROp)(Condition cond,
253                                                      EncodingSize size,
254                                                      Register rd,
255                                                      Register rn,
256                                                      const Operand& operand);
257   typedef void (Assembler::*InstructionCondROp)(Condition cond,
258                                                 Register rd,
259                                                 const Operand& operand);
260   typedef void (Assembler::*InstructionROp)(Register rd,
261                                             const Operand& operand);
262   typedef void (Assembler::*InstructionCondRROp)(Condition cond,
263                                                  Register rd,
264                                                  Register rn,
265                                                  const Operand& operand);
266   typedef void (Assembler::*InstructionCondSizeRL)(Condition cond,
267                                                    EncodingSize size,
268                                                    Register rd,
269                                                    Location* location);
270   typedef void (Assembler::*InstructionDtQQ)(DataType dt,
271                                              QRegister rd,
272                                              QRegister rm);
273   typedef void (Assembler::*InstructionCondSizeL)(Condition cond,
274                                                   EncodingSize size,
275                                                   Location* location);
276   typedef void (Assembler::*InstructionCondRII)(Condition cond,
277                                                 Register rd,
278                                                 uint32_t lsb,
279                                                 uint32_t width);
280   typedef void (Assembler::*InstructionCondRRII)(
281       Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
282   typedef void (Assembler::*InstructionCondI)(Condition cond, uint32_t imm);
283   typedef void (Assembler::*InstructionCondL)(Condition cond,
284                                               Location* location);
285   typedef void (Assembler::*InstructionCondR)(Condition cond, Register rm);
286   typedef void (Assembler::*InstructionRL)(Register rn, Location* location);
287   typedef void (Assembler::*InstructionCond)(Condition cond);
288   typedef void (Assembler::*InstructionCondRR)(Condition cond,
289                                                Register rd,
290                                                Register rm);
291   typedef void (Assembler::*InstructionCondSizeROp)(Condition cond,
292                                                     EncodingSize size,
293                                                     Register rn,
294                                                     const Operand& operand);
295   typedef void (Assembler::*InstructionCondRRR)(Condition cond,
296                                                 Register rd,
297                                                 Register rn,
298                                                 Register rm);
299   typedef void (Assembler::*InstructionCondBa)(Condition cond,
300                                                MemoryBarrier option);
301   typedef void (Assembler::*InstructionCondRwbDrl)(Condition cond,
302                                                    Register rn,
303                                                    WriteBack write_back,
304                                                    DRegisterList dreglist);
305   typedef void (Assembler::*InstructionCondRMop)(Condition cond,
306                                                  Register rt,
307                                                  const MemOperand& operand);
308   typedef void (Assembler::*InstructionCondRRMop)(Condition cond,
309                                                   Register rt,
310                                                   Register rt2,
311                                                   const MemOperand& operand);
312   typedef void (Assembler::*InstructionCondSizeRwbRl)(Condition cond,
313                                                       EncodingSize size,
314                                                       Register rn,
315                                                       WriteBack write_back,
316                                                       RegisterList registers);
317   typedef void (Assembler::*InstructionCondRwbRl)(Condition cond,
318                                                   Register rn,
319                                                   WriteBack write_back,
320                                                   RegisterList registers);
321   typedef void (Assembler::*InstructionCondSizeRMop)(Condition cond,
322                                                      EncodingSize size,
323                                                      Register rt,
324                                                      const MemOperand& operand);
325   typedef void (Assembler::*InstructionCondRL)(Condition cond,
326                                                Register rt,
327                                                Location* location);
328   typedef void (Assembler::*InstructionCondRRL)(Condition cond,
329                                                 Register rt,
330                                                 Register rt2,
331                                                 Location* location);
332   typedef void (Assembler::*InstructionCondRRRR)(
333       Condition cond, Register rd, Register rn, Register rm, Register ra);
334   typedef void (Assembler::*InstructionCondRSr)(Condition cond,
335                                                 Register rd,
336                                                 SpecialRegister spec_reg);
337   typedef void (Assembler::*InstructionCondMsrOp)(
338       Condition cond, MaskedSpecialRegister spec_reg, const Operand& operand);
339   typedef void (Assembler::*InstructionCondSizeRRR)(
340       Condition cond, EncodingSize size, Register rd, Register rn, Register rm);
341   typedef void (Assembler::*InstructionCondSize)(Condition cond,
342                                                  EncodingSize size);
343   typedef void (Assembler::*InstructionCondMop)(Condition cond,
344                                                 const MemOperand& operand);
345   typedef void (Assembler::*InstructionCondSizeRl)(Condition cond,
346                                                    EncodingSize size,
347                                                    RegisterList registers);
348   typedef void (Assembler::*InstructionCondSizeOrl)(Condition cond,
349                                                     EncodingSize size,
350                                                     Register rt);
351   typedef void (Assembler::*InstructionCondSizeRR)(Condition cond,
352                                                    EncodingSize size,
353                                                    Register rd,
354                                                    Register rm);
355   typedef void (Assembler::*InstructionDtQQQ)(DataType dt,
356                                               QRegister rd,
357                                               QRegister rn,
358                                               QRegister rm);
359   typedef void (Assembler::*InstructionCondRIOp)(Condition cond,
360                                                  Register rd,
361                                                  uint32_t imm,
362                                                  const Operand& operand);
363   typedef void (Assembler::*InstructionCondRIR)(Condition cond,
364                                                 Register rd,
365                                                 uint32_t imm,
366                                                 Register rn);
367   typedef void (Assembler::*InstructionCondRRRMop)(Condition cond,
368                                                    Register rd,
369                                                    Register rt,
370                                                    Register rt2,
371                                                    const MemOperand& operand);
372   typedef void (Assembler::*InstructionCondSizeI)(Condition cond,
373                                                   EncodingSize size,
374                                                   uint32_t imm);
375   typedef void (Assembler::*InstructionCondDtDDD)(
376       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
377   typedef void (Assembler::*InstructionCondDtQQQ)(
378       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
379   typedef void (Assembler::*InstructionCondDtQDD)(
380       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
381   typedef void (Assembler::*InstructionCondDtDD)(Condition cond,
382                                                  DataType dt,
383                                                  DRegister rd,
384                                                  DRegister rm);
385   typedef void (Assembler::*InstructionCondDtQQ)(Condition cond,
386                                                  DataType dt,
387                                                  QRegister rd,
388                                                  QRegister rm);
389   typedef void (Assembler::*InstructionCondDtSS)(Condition cond,
390                                                  DataType dt,
391                                                  SRegister rd,
392                                                  SRegister rm);
393   typedef void (Assembler::*InstructionCondDtSSS)(
394       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
395   typedef void (Assembler::*InstructionCondDtDQQ)(
396       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
397   typedef void (Assembler::*InstructionCondDtQQD)(
398       Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm);
399   typedef void (Assembler::*InstructionCondDtDDDop)(Condition cond,
400                                                     DataType dt,
401                                                     DRegister rd,
402                                                     DRegister rn,
403                                                     const DOperand& operand);
404   typedef void (Assembler::*InstructionCondDtQQQop)(Condition cond,
405                                                     DataType dt,
406                                                     QRegister rd,
407                                                     QRegister rn,
408                                                     const QOperand& operand);
409   typedef void (Assembler::*InstructionCondDtSSop)(Condition cond,
410                                                    DataType dt,
411                                                    SRegister rd,
412                                                    const SOperand& operand);
413   typedef void (Assembler::*InstructionCondDtDDop)(Condition cond,
414                                                    DataType dt,
415                                                    DRegister rd,
416                                                    const DOperand& operand);
417   typedef void (Assembler::*InstructionCondDtDtDS)(
418       Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
419   typedef void (Assembler::*InstructionCondDtDtSD)(
420       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
421   typedef void (Assembler::*InstructionCondDtDtDDSi)(Condition cond,
422                                                      DataType dt1,
423                                                      DataType dt2,
424                                                      DRegister rd,
425                                                      DRegister rm,
426                                                      int32_t fbits);
427   typedef void (Assembler::*InstructionCondDtDtQQSi)(Condition cond,
428                                                      DataType dt1,
429                                                      DataType dt2,
430                                                      QRegister rd,
431                                                      QRegister rm,
432                                                      int32_t fbits);
433   typedef void (Assembler::*InstructionCondDtDtSSSi)(Condition cond,
434                                                      DataType dt1,
435                                                      DataType dt2,
436                                                      SRegister rd,
437                                                      SRegister rm,
438                                                      int32_t fbits);
439   typedef void (Assembler::*InstructionCondDtDtDD)(
440       Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm);
441   typedef void (Assembler::*InstructionCondDtDtQQ)(
442       Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm);
443   typedef void (Assembler::*InstructionCondDtDtDQ)(
444       Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm);
445   typedef void (Assembler::*InstructionCondDtDtQD)(
446       Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm);
447   typedef void (Assembler::*InstructionCondDtDtSS)(
448       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
449   typedef void (Assembler::*InstructionDtDtDD)(DataType dt1,
450                                                DataType dt2,
451                                                DRegister rd,
452                                                DRegister rm);
453   typedef void (Assembler::*InstructionDtDtQQ)(DataType dt1,
454                                                DataType dt2,
455                                                QRegister rd,
456                                                QRegister rm);
457   typedef void (Assembler::*InstructionDtDtSS)(DataType dt1,
458                                                DataType dt2,
459                                                SRegister rd,
460                                                SRegister rm);
461   typedef void (Assembler::*InstructionDtDtSD)(DataType dt1,
462                                                DataType dt2,
463                                                SRegister rd,
464                                                DRegister rm);
465   typedef void (Assembler::*InstructionCondDtQR)(Condition cond,
466                                                  DataType dt,
467                                                  QRegister rd,
468                                                  Register rt);
469   typedef void (Assembler::*InstructionCondDtDR)(Condition cond,
470                                                  DataType dt,
471                                                  DRegister rd,
472                                                  Register rt);
473   typedef void (Assembler::*InstructionCondDtDDx)(Condition cond,
474                                                   DataType dt,
475                                                   DRegister rd,
476                                                   DRegisterLane rm);
477   typedef void (Assembler::*InstructionCondDtQDx)(Condition cond,
478                                                   DataType dt,
479                                                   QRegister rd,
480                                                   DRegisterLane rm);
481   typedef void (Assembler::*InstructionCondDtDDDDop)(Condition cond,
482                                                      DataType dt,
483                                                      DRegister rd,
484                                                      DRegister rn,
485                                                      DRegister rm,
486                                                      const DOperand& operand);
487   typedef void (Assembler::*InstructionCondDtQQQQop)(Condition cond,
488                                                      DataType dt,
489                                                      QRegister rd,
490                                                      QRegister rn,
491                                                      QRegister rm,
492                                                      const QOperand& operand);
493   typedef void (Assembler::*InstructionCondDtNrlAmop)(
494       Condition cond,
495       DataType dt,
496       const NeonRegisterList& nreglist,
497       const AlignedMemOperand& operand);
498   typedef void (Assembler::*InstructionCondDtNrlMop)(
499       Condition cond,
500       DataType dt,
501       const NeonRegisterList& nreglist,
502       const MemOperand& operand);
503   typedef void (Assembler::*InstructionCondDtRwbDrl)(Condition cond,
504                                                      DataType dt,
505                                                      Register rn,
506                                                      WriteBack write_back,
507                                                      DRegisterList dreglist);
508   typedef void (Assembler::*InstructionCondDtRwbSrl)(Condition cond,
509                                                      DataType dt,
510                                                      Register rn,
511                                                      WriteBack write_back,
512                                                      SRegisterList sreglist);
513   typedef void (Assembler::*InstructionCondDtDL)(Condition cond,
514                                                  DataType dt,
515                                                  DRegister rd,
516                                                  Location* location);
517   typedef void (Assembler::*InstructionCondDtDMop)(Condition cond,
518                                                    DataType dt,
519                                                    DRegister rd,
520                                                    const MemOperand& operand);
521   typedef void (Assembler::*InstructionCondDtSL)(Condition cond,
522                                                  DataType dt,
523                                                  SRegister rd,
524                                                  Location* location);
525   typedef void (Assembler::*InstructionCondDtSMop)(Condition cond,
526                                                    DataType dt,
527                                                    SRegister rd,
528                                                    const MemOperand& operand);
529   typedef void (Assembler::*InstructionDtDDD)(DataType dt,
530                                               DRegister rd,
531                                               DRegister rn,
532                                               DRegister rm);
533   typedef void (Assembler::*InstructionDtSSS)(DataType dt,
534                                               SRegister rd,
535                                               SRegister rn,
536                                               SRegister rm);
537   typedef void (Assembler::*InstructionCondDtDDDx)(Condition cond,
538                                                    DataType dt,
539                                                    DRegister rd,
540                                                    DRegister rn,
541                                                    DRegisterLane rm);
542   typedef void (Assembler::*InstructionCondDtQQDx)(Condition cond,
543                                                    DataType dt,
544                                                    QRegister rd,
545                                                    QRegister rn,
546                                                    DRegisterLane rm);
547   typedef void (Assembler::*InstructionCondDtQDDx)(Condition cond,
548                                                    DataType dt,
549                                                    QRegister rd,
550                                                    DRegister rn,
551                                                    DRegisterLane rm);
552   typedef void (Assembler::*InstructionCondRS)(Condition cond,
553                                                Register rt,
554                                                SRegister rn);
555   typedef void (Assembler::*InstructionCondSR)(Condition cond,
556                                                SRegister rn,
557                                                Register rt);
558   typedef void (Assembler::*InstructionCondRRD)(Condition cond,
559                                                 Register rt,
560                                                 Register rt2,
561                                                 DRegister rm);
562   typedef void (Assembler::*InstructionCondDRR)(Condition cond,
563                                                 DRegister rm,
564                                                 Register rt,
565                                                 Register rt2);
566   typedef void (Assembler::*InstructionCondRRSS)(
567       Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1);
568   typedef void (Assembler::*InstructionCondSSRR)(
569       Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2);
570   typedef void (Assembler::*InstructionCondDtDxR)(Condition cond,
571                                                   DataType dt,
572                                                   DRegisterLane rd,
573                                                   Register rt);
574   typedef void (Assembler::*InstructionCondDtQQop)(Condition cond,
575                                                    DataType dt,
576                                                    QRegister rd,
577                                                    const QOperand& operand);
578   typedef void (Assembler::*InstructionCondDtRDx)(Condition cond,
579                                                   DataType dt,
580                                                   Register rt,
581                                                   DRegisterLane rn);
582   typedef void (Assembler::*InstructionCondDtQD)(Condition cond,
583                                                  DataType dt,
584                                                  QRegister rd,
585                                                  DRegister rm);
586   typedef void (Assembler::*InstructionCondDtDQ)(Condition cond,
587                                                  DataType dt,
588                                                  DRegister rd,
589                                                  QRegister rm);
590   typedef void (Assembler::*InstructionCondRoaSfp)(Condition cond,
591                                                    RegisterOrAPSR_nzcv rt,
592                                                    SpecialFPRegister spec_reg);
593   typedef void (Assembler::*InstructionCondSfpR)(Condition cond,
594                                                  SpecialFPRegister spec_reg,
595                                                  Register rt);
596   typedef void (Assembler::*InstructionCondDtDDIr)(Condition cond,
597                                                    DataType dt,
598                                                    DRegister rd,
599                                                    DRegister rn,
600                                                    DRegister dm,
601                                                    unsigned index);
602   typedef void (Assembler::*InstructionCondDtQQIr)(Condition cond,
603                                                    DataType dt,
604                                                    QRegister rd,
605                                                    QRegister rn,
606                                                    DRegister dm,
607                                                    unsigned index);
608   typedef void (Assembler::*InstructionCondDtQDIr)(Condition cond,
609                                                    DataType dt,
610                                                    QRegister rd,
611                                                    DRegister rn,
612                                                    DRegister dm,
613                                                    unsigned index);
614   typedef void (Assembler::*InstructionCondDtDrl)(Condition cond,
615                                                   DataType dt,
616                                                   DRegisterList dreglist);
617   typedef void (Assembler::*InstructionCondDtSrl)(Condition cond,
618                                                   DataType dt,
619                                                   SRegisterList sreglist);
620   typedef void (Assembler::*InstructionCondDtDQQop)(Condition cond,
621                                                     DataType dt,
622                                                     DRegister rd,
623                                                     QRegister rm,
624                                                     const QOperand& operand);
625   typedef void (Assembler::*InstructionDtDD)(DataType dt,
626                                              DRegister rd,
627                                              DRegister rm);
628   typedef void (Assembler::*InstructionDtSS)(DataType dt,
629                                              SRegister rd,
630                                              SRegister rm);
631   typedef void (Assembler::*InstructionCondDtQDDop)(Condition cond,
632                                                     DataType dt,
633                                                     QRegister rd,
634                                                     DRegister rm,
635                                                     const DOperand& operand);
636   typedef void (Assembler::*InstructionCondDtDNrlD)(
637       Condition cond,
638       DataType dt,
639       DRegister rd,
640       const NeonRegisterList& nreglist,
641       DRegister rm);
Delegate(InstructionType type,InstructionCondSizeRROp,Condition,EncodingSize,Register,Register,const Operand &)642   virtual void Delegate(InstructionType type,
643                         InstructionCondSizeRROp /*instruction*/,
644                         Condition /*cond*/,
645                         EncodingSize /*size*/,
646                         Register /*rd*/,
647                         Register /*rn*/,
648                         const Operand& /*operand*/) {
649     USE(type);
650     VIXL_ASSERT((type == kAdc) || (type == kAdcs) || (type == kAdd) ||
651                 (type == kAdds) || (type == kAnd) || (type == kAnds) ||
652                 (type == kAsr) || (type == kAsrs) || (type == kBic) ||
653                 (type == kBics) || (type == kEor) || (type == kEors) ||
654                 (type == kLsl) || (type == kLsls) || (type == kLsr) ||
655                 (type == kLsrs) || (type == kOrr) || (type == kOrrs) ||
656                 (type == kRor) || (type == kRors) || (type == kRsb) ||
657                 (type == kRsbs) || (type == kSbc) || (type == kSbcs) ||
658                 (type == kSub) || (type == kSubs));
659     UnimplementedDelegate(type);
660   }
Delegate(InstructionType type,InstructionCondROp,Condition,Register,const Operand &)661   virtual void Delegate(InstructionType type,
662                         InstructionCondROp /*instruction*/,
663                         Condition /*cond*/,
664                         Register /*rd*/,
665                         const Operand& /*operand*/) {
666     USE(type);
667     VIXL_ASSERT((type == kAdd) || (type == kMovt) || (type == kMovw) ||
668                 (type == kSub) || (type == kSxtb16) || (type == kTeq) ||
669                 (type == kUxtb16));
670     UnimplementedDelegate(type);
671   }
Delegate(InstructionType type,InstructionROp,Register,const Operand &)672   virtual void Delegate(InstructionType type,
673                         InstructionROp /*instruction*/,
674                         Register /*rd*/,
675                         const Operand& /*operand*/) {
676     USE(type);
677     VIXL_ASSERT((type == kAdds) || (type == kSubs));
678     UnimplementedDelegate(type);
679   }
Delegate(InstructionType type,InstructionCondRROp,Condition,Register,Register,const Operand &)680   virtual void Delegate(InstructionType type,
681                         InstructionCondRROp /*instruction*/,
682                         Condition /*cond*/,
683                         Register /*rd*/,
684                         Register /*rn*/,
685                         const Operand& /*operand*/) {
686     USE(type);
687     VIXL_ASSERT((type == kAddw) || (type == kOrn) || (type == kOrns) ||
688                 (type == kPkhbt) || (type == kPkhtb) || (type == kRsc) ||
689                 (type == kRscs) || (type == kSubw) || (type == kSxtab) ||
690                 (type == kSxtab16) || (type == kSxtah) || (type == kUxtab) ||
691                 (type == kUxtab16) || (type == kUxtah));
692     UnimplementedDelegate(type);
693   }
Delegate(InstructionType type,InstructionCondSizeRL,Condition,EncodingSize,Register,Location *)694   virtual void Delegate(InstructionType type,
695                         InstructionCondSizeRL /*instruction*/,
696                         Condition /*cond*/,
697                         EncodingSize /*size*/,
698                         Register /*rd*/,
699                         Location* /*location*/) {
700     USE(type);
701     VIXL_ASSERT((type == kAdr) || (type == kLdr));
702     UnimplementedDelegate(type);
703   }
Delegate(InstructionType type,InstructionDtQQ,DataType,QRegister,QRegister)704   virtual void Delegate(InstructionType type,
705                         InstructionDtQQ /*instruction*/,
706                         DataType /*dt*/,
707                         QRegister /*rd*/,
708                         QRegister /*rm*/) {
709     USE(type);
710     VIXL_ASSERT((type == kVrinta) || (type == kVrintm) || (type == kVrintn) ||
711                 (type == kVrintp) || (type == kVrintx) || (type == kVrintz));
712     UnimplementedDelegate(type);
713   }
Delegate(InstructionType type,InstructionCondSizeL,Condition,EncodingSize,Location *)714   virtual void Delegate(InstructionType type,
715                         InstructionCondSizeL /*instruction*/,
716                         Condition /*cond*/,
717                         EncodingSize /*size*/,
718                         Location* /*location*/) {
719     USE(type);
720     VIXL_ASSERT((type == kB));
721     UnimplementedDelegate(type);
722   }
Delegate(InstructionType type,InstructionCondRII,Condition,Register,uint32_t,uint32_t)723   virtual void Delegate(InstructionType type,
724                         InstructionCondRII /*instruction*/,
725                         Condition /*cond*/,
726                         Register /*rd*/,
727                         uint32_t /*lsb*/,
728                         uint32_t /*width*/) {
729     USE(type);
730     VIXL_ASSERT((type == kBfc));
731     UnimplementedDelegate(type);
732   }
Delegate(InstructionType type,InstructionCondRRII,Condition,Register,Register,uint32_t,uint32_t)733   virtual void Delegate(InstructionType type,
734                         InstructionCondRRII /*instruction*/,
735                         Condition /*cond*/,
736                         Register /*rd*/,
737                         Register /*rn*/,
738                         uint32_t /*lsb*/,
739                         uint32_t /*width*/) {
740     USE(type);
741     VIXL_ASSERT((type == kBfi) || (type == kSbfx) || (type == kUbfx));
742     UnimplementedDelegate(type);
743   }
Delegate(InstructionType type,InstructionCondI,Condition,uint32_t)744   virtual void Delegate(InstructionType type,
745                         InstructionCondI /*instruction*/,
746                         Condition /*cond*/,
747                         uint32_t /*imm*/) {
748     USE(type);
749     VIXL_ASSERT((type == kBkpt) || (type == kHlt) || (type == kHvc) ||
750                 (type == kSvc));
751     UnimplementedDelegate(type);
752   }
Delegate(InstructionType type,InstructionCondL,Condition,Location *)753   virtual void Delegate(InstructionType type,
754                         InstructionCondL /*instruction*/,
755                         Condition /*cond*/,
756                         Location* /*location*/) {
757     USE(type);
758     VIXL_ASSERT((type == kBl) || (type == kBlx) || (type == kPld) ||
759                 (type == kPli));
760     UnimplementedDelegate(type);
761   }
Delegate(InstructionType type,InstructionCondR,Condition,Register)762   virtual void Delegate(InstructionType type,
763                         InstructionCondR /*instruction*/,
764                         Condition /*cond*/,
765                         Register /*rm*/) {
766     USE(type);
767     VIXL_ASSERT((type == kBlx) || (type == kBx) || (type == kBxj));
768     UnimplementedDelegate(type);
769   }
Delegate(InstructionType type,InstructionRL,Register,Location *)770   virtual void Delegate(InstructionType type,
771                         InstructionRL /*instruction*/,
772                         Register /*rn*/,
773                         Location* /*location*/) {
774     USE(type);
775     VIXL_ASSERT((type == kCbnz) || (type == kCbz));
776     UnimplementedDelegate(type);
777   }
Delegate(InstructionType type,InstructionCond,Condition)778   virtual void Delegate(InstructionType type,
779                         InstructionCond /*instruction*/,
780                         Condition /*cond*/) {
781     USE(type);
782     VIXL_ASSERT((type == kClrex));
783     UnimplementedDelegate(type);
784   }
Delegate(InstructionType type,InstructionCondRR,Condition,Register,Register)785   virtual void Delegate(InstructionType type,
786                         InstructionCondRR /*instruction*/,
787                         Condition /*cond*/,
788                         Register /*rd*/,
789                         Register /*rm*/) {
790     USE(type);
791     VIXL_ASSERT((type == kClz) || (type == kRbit) || (type == kRrx) ||
792                 (type == kRrxs));
793     UnimplementedDelegate(type);
794   }
Delegate(InstructionType type,InstructionCondSizeROp,Condition,EncodingSize,Register,const Operand &)795   virtual void Delegate(InstructionType type,
796                         InstructionCondSizeROp /*instruction*/,
797                         Condition /*cond*/,
798                         EncodingSize /*size*/,
799                         Register /*rn*/,
800                         const Operand& /*operand*/) {
801     USE(type);
802     VIXL_ASSERT((type == kCmn) || (type == kCmp) || (type == kMov) ||
803                 (type == kMovs) || (type == kMvn) || (type == kMvns) ||
804                 (type == kSxtb) || (type == kSxth) || (type == kTst) ||
805                 (type == kUxtb) || (type == kUxth));
806     UnimplementedDelegate(type);
807   }
Delegate(InstructionType type,InstructionCondRRR,Condition,Register,Register,Register)808   virtual void Delegate(InstructionType type,
809                         InstructionCondRRR /*instruction*/,
810                         Condition /*cond*/,
811                         Register /*rd*/,
812                         Register /*rn*/,
813                         Register /*rm*/) {
814     USE(type);
815     VIXL_ASSERT((type == kCrc32b) || (type == kCrc32cb) || (type == kCrc32ch) ||
816                 (type == kCrc32cw) || (type == kCrc32h) || (type == kCrc32w) ||
817                 (type == kMuls) || (type == kQadd) || (type == kQadd16) ||
818                 (type == kQadd8) || (type == kQasx) || (type == kQdadd) ||
819                 (type == kQdsub) || (type == kQsax) || (type == kQsub) ||
820                 (type == kQsub16) || (type == kQsub8) || (type == kSadd16) ||
821                 (type == kSadd8) || (type == kSasx) || (type == kSdiv) ||
822                 (type == kSel) || (type == kShadd16) || (type == kShadd8) ||
823                 (type == kShasx) || (type == kShsax) || (type == kShsub16) ||
824                 (type == kShsub8) || (type == kSmmul) || (type == kSmmulr) ||
825                 (type == kSmuad) || (type == kSmuadx) || (type == kSmulbb) ||
826                 (type == kSmulbt) || (type == kSmultb) || (type == kSmultt) ||
827                 (type == kSmulwb) || (type == kSmulwt) || (type == kSmusd) ||
828                 (type == kSmusdx) || (type == kSsax) || (type == kSsub16) ||
829                 (type == kSsub8) || (type == kUadd16) || (type == kUadd8) ||
830                 (type == kUasx) || (type == kUdiv) || (type == kUhadd16) ||
831                 (type == kUhadd8) || (type == kUhasx) || (type == kUhsax) ||
832                 (type == kUhsub16) || (type == kUhsub8) || (type == kUqadd16) ||
833                 (type == kUqadd8) || (type == kUqasx) || (type == kUqsax) ||
834                 (type == kUqsub16) || (type == kUqsub8) || (type == kUsad8) ||
835                 (type == kUsax) || (type == kUsub16) || (type == kUsub8));
836     UnimplementedDelegate(type);
837   }
Delegate(InstructionType type,InstructionCondBa,Condition,MemoryBarrier)838   virtual void Delegate(InstructionType type,
839                         InstructionCondBa /*instruction*/,
840                         Condition /*cond*/,
841                         MemoryBarrier /*option*/) {
842     USE(type);
843     VIXL_ASSERT((type == kDmb) || (type == kDsb) || (type == kIsb));
844     UnimplementedDelegate(type);
845   }
Delegate(InstructionType type,InstructionCondRwbDrl,Condition,Register,WriteBack,DRegisterList)846   virtual void Delegate(InstructionType type,
847                         InstructionCondRwbDrl /*instruction*/,
848                         Condition /*cond*/,
849                         Register /*rn*/,
850                         WriteBack /*write_back*/,
851                         DRegisterList /*dreglist*/) {
852     USE(type);
853     VIXL_ASSERT((type == kFldmdbx) || (type == kFldmiax) ||
854                 (type == kFstmdbx) || (type == kFstmiax));
855     UnimplementedDelegate(type);
856   }
DelegateIt(Condition,uint16_t)857   virtual void DelegateIt(Condition /*cond*/, uint16_t /*mask*/) {
858     UnimplementedDelegate(kIt);
859   }
Delegate(InstructionType type,InstructionCondRMop,Condition,Register,const MemOperand &)860   virtual void Delegate(InstructionType type,
861                         InstructionCondRMop /*instruction*/,
862                         Condition /*cond*/,
863                         Register /*rt*/,
864                         const MemOperand& /*operand*/) {
865     USE(type);
866     VIXL_ASSERT((type == kLda) || (type == kLdab) || (type == kLdaex) ||
867                 (type == kLdaexb) || (type == kLdaexh) || (type == kLdah) ||
868                 (type == kLdrex) || (type == kLdrexb) || (type == kLdrexh) ||
869                 (type == kStl) || (type == kStlb) || (type == kStlh));
870     UnimplementedDelegate(type);
871   }
Delegate(InstructionType type,InstructionCondRRMop,Condition,Register,Register,const MemOperand &)872   virtual void Delegate(InstructionType type,
873                         InstructionCondRRMop /*instruction*/,
874                         Condition /*cond*/,
875                         Register /*rt*/,
876                         Register /*rt2*/,
877                         const MemOperand& /*operand*/) {
878     USE(type);
879     VIXL_ASSERT((type == kLdaexd) || (type == kLdrd) || (type == kLdrexd) ||
880                 (type == kStlex) || (type == kStlexb) || (type == kStlexh) ||
881                 (type == kStrd) || (type == kStrex) || (type == kStrexb) ||
882                 (type == kStrexh));
883     UnimplementedDelegate(type);
884   }
Delegate(InstructionType type,InstructionCondSizeRwbRl,Condition,EncodingSize,Register,WriteBack,RegisterList)885   virtual void Delegate(InstructionType type,
886                         InstructionCondSizeRwbRl /*instruction*/,
887                         Condition /*cond*/,
888                         EncodingSize /*size*/,
889                         Register /*rn*/,
890                         WriteBack /*write_back*/,
891                         RegisterList /*registers*/) {
892     USE(type);
893     VIXL_ASSERT((type == kLdm) || (type == kLdmfd) || (type == kStm) ||
894                 (type == kStmdb) || (type == kStmea));
895     UnimplementedDelegate(type);
896   }
Delegate(InstructionType type,InstructionCondRwbRl,Condition,Register,WriteBack,RegisterList)897   virtual void Delegate(InstructionType type,
898                         InstructionCondRwbRl /*instruction*/,
899                         Condition /*cond*/,
900                         Register /*rn*/,
901                         WriteBack /*write_back*/,
902                         RegisterList /*registers*/) {
903     USE(type);
904     VIXL_ASSERT((type == kLdmda) || (type == kLdmdb) || (type == kLdmea) ||
905                 (type == kLdmed) || (type == kLdmfa) || (type == kLdmib) ||
906                 (type == kStmda) || (type == kStmed) || (type == kStmfa) ||
907                 (type == kStmfd) || (type == kStmib));
908     UnimplementedDelegate(type);
909   }
Delegate(InstructionType type,InstructionCondSizeRMop,Condition,EncodingSize,Register,const MemOperand &)910   virtual void Delegate(InstructionType type,
911                         InstructionCondSizeRMop /*instruction*/,
912                         Condition /*cond*/,
913                         EncodingSize /*size*/,
914                         Register /*rt*/,
915                         const MemOperand& /*operand*/) {
916     USE(type);
917     VIXL_ASSERT((type == kLdr) || (type == kLdrb) || (type == kLdrh) ||
918                 (type == kLdrsb) || (type == kLdrsh) || (type == kStr) ||
919                 (type == kStrb) || (type == kStrh));
920     UnimplementedDelegate(type);
921   }
Delegate(InstructionType type,InstructionCondRL,Condition,Register,Location *)922   virtual void Delegate(InstructionType type,
923                         InstructionCondRL /*instruction*/,
924                         Condition /*cond*/,
925                         Register /*rt*/,
926                         Location* /*location*/) {
927     USE(type);
928     VIXL_ASSERT((type == kLdrb) || (type == kLdrh) || (type == kLdrsb) ||
929                 (type == kLdrsh));
930     UnimplementedDelegate(type);
931   }
Delegate(InstructionType type,InstructionCondRRL,Condition,Register,Register,Location *)932   virtual void Delegate(InstructionType type,
933                         InstructionCondRRL /*instruction*/,
934                         Condition /*cond*/,
935                         Register /*rt*/,
936                         Register /*rt2*/,
937                         Location* /*location*/) {
938     USE(type);
939     VIXL_ASSERT((type == kLdrd));
940     UnimplementedDelegate(type);
941   }
Delegate(InstructionType type,InstructionCondRRRR,Condition,Register,Register,Register,Register)942   virtual void Delegate(InstructionType type,
943                         InstructionCondRRRR /*instruction*/,
944                         Condition /*cond*/,
945                         Register /*rd*/,
946                         Register /*rn*/,
947                         Register /*rm*/,
948                         Register /*ra*/) {
949     USE(type);
950     VIXL_ASSERT((type == kMla) || (type == kMlas) || (type == kMls) ||
951                 (type == kSmlabb) || (type == kSmlabt) || (type == kSmlad) ||
952                 (type == kSmladx) || (type == kSmlal) || (type == kSmlalbb) ||
953                 (type == kSmlalbt) || (type == kSmlald) || (type == kSmlaldx) ||
954                 (type == kSmlals) || (type == kSmlaltb) || (type == kSmlaltt) ||
955                 (type == kSmlatb) || (type == kSmlatt) || (type == kSmlawb) ||
956                 (type == kSmlawt) || (type == kSmlsd) || (type == kSmlsdx) ||
957                 (type == kSmlsld) || (type == kSmlsldx) || (type == kSmmla) ||
958                 (type == kSmmlar) || (type == kSmmls) || (type == kSmmlsr) ||
959                 (type == kSmull) || (type == kSmulls) || (type == kUmaal) ||
960                 (type == kUmlal) || (type == kUmlals) || (type == kUmull) ||
961                 (type == kUmulls) || (type == kUsada8));
962     UnimplementedDelegate(type);
963   }
Delegate(InstructionType type,InstructionCondRSr,Condition,Register,SpecialRegister)964   virtual void Delegate(InstructionType type,
965                         InstructionCondRSr /*instruction*/,
966                         Condition /*cond*/,
967                         Register /*rd*/,
968                         SpecialRegister /*spec_reg*/) {
969     USE(type);
970     VIXL_ASSERT((type == kMrs));
971     UnimplementedDelegate(type);
972   }
Delegate(InstructionType type,InstructionCondMsrOp,Condition,MaskedSpecialRegister,const Operand &)973   virtual void Delegate(InstructionType type,
974                         InstructionCondMsrOp /*instruction*/,
975                         Condition /*cond*/,
976                         MaskedSpecialRegister /*spec_reg*/,
977                         const Operand& /*operand*/) {
978     USE(type);
979     VIXL_ASSERT((type == kMsr));
980     UnimplementedDelegate(type);
981   }
Delegate(InstructionType type,InstructionCondSizeRRR,Condition,EncodingSize,Register,Register,Register)982   virtual void Delegate(InstructionType type,
983                         InstructionCondSizeRRR /*instruction*/,
984                         Condition /*cond*/,
985                         EncodingSize /*size*/,
986                         Register /*rd*/,
987                         Register /*rn*/,
988                         Register /*rm*/) {
989     USE(type);
990     VIXL_ASSERT((type == kMul));
991     UnimplementedDelegate(type);
992   }
Delegate(InstructionType type,InstructionCondSize,Condition,EncodingSize)993   virtual void Delegate(InstructionType type,
994                         InstructionCondSize /*instruction*/,
995                         Condition /*cond*/,
996                         EncodingSize /*size*/) {
997     USE(type);
998     VIXL_ASSERT((type == kNop) || (type == kYield));
999     UnimplementedDelegate(type);
1000   }
Delegate(InstructionType type,InstructionCondMop,Condition,const MemOperand &)1001   virtual void Delegate(InstructionType type,
1002                         InstructionCondMop /*instruction*/,
1003                         Condition /*cond*/,
1004                         const MemOperand& /*operand*/) {
1005     USE(type);
1006     VIXL_ASSERT((type == kPld) || (type == kPldw) || (type == kPli));
1007     UnimplementedDelegate(type);
1008   }
Delegate(InstructionType type,InstructionCondSizeRl,Condition,EncodingSize,RegisterList)1009   virtual void Delegate(InstructionType type,
1010                         InstructionCondSizeRl /*instruction*/,
1011                         Condition /*cond*/,
1012                         EncodingSize /*size*/,
1013                         RegisterList /*registers*/) {
1014     USE(type);
1015     VIXL_ASSERT((type == kPop) || (type == kPush));
1016     UnimplementedDelegate(type);
1017   }
Delegate(InstructionType type,InstructionCondSizeOrl,Condition,EncodingSize,Register)1018   virtual void Delegate(InstructionType type,
1019                         InstructionCondSizeOrl /*instruction*/,
1020                         Condition /*cond*/,
1021                         EncodingSize /*size*/,
1022                         Register /*rt*/) {
1023     USE(type);
1024     VIXL_ASSERT((type == kPop) || (type == kPush));
1025     UnimplementedDelegate(type);
1026   }
Delegate(InstructionType type,InstructionCondSizeRR,Condition,EncodingSize,Register,Register)1027   virtual void Delegate(InstructionType type,
1028                         InstructionCondSizeRR /*instruction*/,
1029                         Condition /*cond*/,
1030                         EncodingSize /*size*/,
1031                         Register /*rd*/,
1032                         Register /*rm*/) {
1033     USE(type);
1034     VIXL_ASSERT((type == kRev) || (type == kRev16) || (type == kRevsh));
1035     UnimplementedDelegate(type);
1036   }
Delegate(InstructionType type,InstructionDtQQQ,DataType,QRegister,QRegister,QRegister)1037   virtual void Delegate(InstructionType type,
1038                         InstructionDtQQQ /*instruction*/,
1039                         DataType /*dt*/,
1040                         QRegister /*rd*/,
1041                         QRegister /*rn*/,
1042                         QRegister /*rm*/) {
1043     USE(type);
1044     VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm));
1045     UnimplementedDelegate(type);
1046   }
Delegate(InstructionType type,InstructionCondRIOp,Condition,Register,uint32_t,const Operand &)1047   virtual void Delegate(InstructionType type,
1048                         InstructionCondRIOp /*instruction*/,
1049                         Condition /*cond*/,
1050                         Register /*rd*/,
1051                         uint32_t /*imm*/,
1052                         const Operand& /*operand*/) {
1053     USE(type);
1054     VIXL_ASSERT((type == kSsat) || (type == kUsat));
1055     UnimplementedDelegate(type);
1056   }
Delegate(InstructionType type,InstructionCondRIR,Condition,Register,uint32_t,Register)1057   virtual void Delegate(InstructionType type,
1058                         InstructionCondRIR /*instruction*/,
1059                         Condition /*cond*/,
1060                         Register /*rd*/,
1061                         uint32_t /*imm*/,
1062                         Register /*rn*/) {
1063     USE(type);
1064     VIXL_ASSERT((type == kSsat16) || (type == kUsat16));
1065     UnimplementedDelegate(type);
1066   }
Delegate(InstructionType type,InstructionCondRRRMop,Condition,Register,Register,Register,const MemOperand &)1067   virtual void Delegate(InstructionType type,
1068                         InstructionCondRRRMop /*instruction*/,
1069                         Condition /*cond*/,
1070                         Register /*rd*/,
1071                         Register /*rt*/,
1072                         Register /*rt2*/,
1073                         const MemOperand& /*operand*/) {
1074     USE(type);
1075     VIXL_ASSERT((type == kStlexd) || (type == kStrexd));
1076     UnimplementedDelegate(type);
1077   }
Delegate(InstructionType type,InstructionCondSizeI,Condition,EncodingSize,uint32_t)1078   virtual void Delegate(InstructionType type,
1079                         InstructionCondSizeI /*instruction*/,
1080                         Condition /*cond*/,
1081                         EncodingSize /*size*/,
1082                         uint32_t /*imm*/) {
1083     USE(type);
1084     VIXL_ASSERT((type == kUdf));
1085     UnimplementedDelegate(type);
1086   }
Delegate(InstructionType type,InstructionCondDtDDD,Condition,DataType,DRegister,DRegister,DRegister)1087   virtual void Delegate(InstructionType type,
1088                         InstructionCondDtDDD /*instruction*/,
1089                         Condition /*cond*/,
1090                         DataType /*dt*/,
1091                         DRegister /*rd*/,
1092                         DRegister /*rn*/,
1093                         DRegister /*rm*/) {
1094     USE(type);
1095     VIXL_ASSERT((type == kVaba) || (type == kVabd) || (type == kVacge) ||
1096                 (type == kVacgt) || (type == kVacle) || (type == kVaclt) ||
1097                 (type == kVadd) || (type == kVbif) || (type == kVbit) ||
1098                 (type == kVbsl) || (type == kVceq) || (type == kVcge) ||
1099                 (type == kVcgt) || (type == kVcle) || (type == kVclt) ||
1100                 (type == kVdiv) || (type == kVeor) || (type == kVfma) ||
1101                 (type == kVfms) || (type == kVfnma) || (type == kVfnms) ||
1102                 (type == kVhadd) || (type == kVhsub) || (type == kVmax) ||
1103                 (type == kVmin) || (type == kVmla) || (type == kVmls) ||
1104                 (type == kVmul) || (type == kVnmla) || (type == kVnmls) ||
1105                 (type == kVnmul) || (type == kVpadd) || (type == kVpmax) ||
1106                 (type == kVpmin) || (type == kVqadd) || (type == kVqdmulh) ||
1107                 (type == kVqrdmulh) || (type == kVqrshl) || (type == kVqsub) ||
1108                 (type == kVrecps) || (type == kVrhadd) || (type == kVrshl) ||
1109                 (type == kVrsqrts) || (type == kVsub) || (type == kVtst));
1110     UnimplementedDelegate(type);
1111   }
Delegate(InstructionType type,InstructionCondDtQQQ,Condition,DataType,QRegister,QRegister,QRegister)1112   virtual void Delegate(InstructionType type,
1113                         InstructionCondDtQQQ /*instruction*/,
1114                         Condition /*cond*/,
1115                         DataType /*dt*/,
1116                         QRegister /*rd*/,
1117                         QRegister /*rn*/,
1118                         QRegister /*rm*/) {
1119     USE(type);
1120     VIXL_ASSERT((type == kVaba) || (type == kVabd) || (type == kVacge) ||
1121                 (type == kVacgt) || (type == kVacle) || (type == kVaclt) ||
1122                 (type == kVadd) || (type == kVbif) || (type == kVbit) ||
1123                 (type == kVbsl) || (type == kVceq) || (type == kVcge) ||
1124                 (type == kVcgt) || (type == kVcle) || (type == kVclt) ||
1125                 (type == kVeor) || (type == kVfma) || (type == kVfms) ||
1126                 (type == kVhadd) || (type == kVhsub) || (type == kVmax) ||
1127                 (type == kVmin) || (type == kVmla) || (type == kVmls) ||
1128                 (type == kVmul) || (type == kVqadd) || (type == kVqdmulh) ||
1129                 (type == kVqrdmulh) || (type == kVqrshl) || (type == kVqsub) ||
1130                 (type == kVrecps) || (type == kVrhadd) || (type == kVrshl) ||
1131                 (type == kVrsqrts) || (type == kVsub) || (type == kVtst));
1132     UnimplementedDelegate(type);
1133   }
Delegate(InstructionType type,InstructionCondDtQDD,Condition,DataType,QRegister,DRegister,DRegister)1134   virtual void Delegate(InstructionType type,
1135                         InstructionCondDtQDD /*instruction*/,
1136                         Condition /*cond*/,
1137                         DataType /*dt*/,
1138                         QRegister /*rd*/,
1139                         DRegister /*rn*/,
1140                         DRegister /*rm*/) {
1141     USE(type);
1142     VIXL_ASSERT((type == kVabal) || (type == kVabdl) || (type == kVaddl) ||
1143                 (type == kVmlal) || (type == kVmlsl) || (type == kVmull) ||
1144                 (type == kVqdmlal) || (type == kVqdmlsl) ||
1145                 (type == kVqdmull) || (type == kVsubl));
1146     UnimplementedDelegate(type);
1147   }
Delegate(InstructionType type,InstructionCondDtDD,Condition,DataType,DRegister,DRegister)1148   virtual void Delegate(InstructionType type,
1149                         InstructionCondDtDD /*instruction*/,
1150                         Condition /*cond*/,
1151                         DataType /*dt*/,
1152                         DRegister /*rd*/,
1153                         DRegister /*rm*/) {
1154     USE(type);
1155     VIXL_ASSERT((type == kVabs) || (type == kVcls) || (type == kVclz) ||
1156                 (type == kVcnt) || (type == kVneg) || (type == kVpadal) ||
1157                 (type == kVpaddl) || (type == kVqabs) || (type == kVqneg) ||
1158                 (type == kVrecpe) || (type == kVrev16) || (type == kVrev32) ||
1159                 (type == kVrev64) || (type == kVrintr) || (type == kVrintx) ||
1160                 (type == kVrintz) || (type == kVrsqrte) || (type == kVsqrt) ||
1161                 (type == kVswp) || (type == kVtrn) || (type == kVuzp) ||
1162                 (type == kVzip));
1163     UnimplementedDelegate(type);
1164   }
Delegate(InstructionType type,InstructionCondDtQQ,Condition,DataType,QRegister,QRegister)1165   virtual void Delegate(InstructionType type,
1166                         InstructionCondDtQQ /*instruction*/,
1167                         Condition /*cond*/,
1168                         DataType /*dt*/,
1169                         QRegister /*rd*/,
1170                         QRegister /*rm*/) {
1171     USE(type);
1172     VIXL_ASSERT((type == kVabs) || (type == kVcls) || (type == kVclz) ||
1173                 (type == kVcnt) || (type == kVneg) || (type == kVpadal) ||
1174                 (type == kVpaddl) || (type == kVqabs) || (type == kVqneg) ||
1175                 (type == kVrecpe) || (type == kVrev16) || (type == kVrev32) ||
1176                 (type == kVrev64) || (type == kVrsqrte) || (type == kVswp) ||
1177                 (type == kVtrn) || (type == kVuzp) || (type == kVzip));
1178     UnimplementedDelegate(type);
1179   }
Delegate(InstructionType type,InstructionCondDtSS,Condition,DataType,SRegister,SRegister)1180   virtual void Delegate(InstructionType type,
1181                         InstructionCondDtSS /*instruction*/,
1182                         Condition /*cond*/,
1183                         DataType /*dt*/,
1184                         SRegister /*rd*/,
1185                         SRegister /*rm*/) {
1186     USE(type);
1187     VIXL_ASSERT((type == kVabs) || (type == kVneg) || (type == kVrintr) ||
1188                 (type == kVrintx) || (type == kVrintz) || (type == kVsqrt));
1189     UnimplementedDelegate(type);
1190   }
Delegate(InstructionType type,InstructionCondDtSSS,Condition,DataType,SRegister,SRegister,SRegister)1191   virtual void Delegate(InstructionType type,
1192                         InstructionCondDtSSS /*instruction*/,
1193                         Condition /*cond*/,
1194                         DataType /*dt*/,
1195                         SRegister /*rd*/,
1196                         SRegister /*rn*/,
1197                         SRegister /*rm*/) {
1198     USE(type);
1199     VIXL_ASSERT((type == kVadd) || (type == kVdiv) || (type == kVfma) ||
1200                 (type == kVfms) || (type == kVfnma) || (type == kVfnms) ||
1201                 (type == kVmla) || (type == kVmls) || (type == kVmul) ||
1202                 (type == kVnmla) || (type == kVnmls) || (type == kVnmul) ||
1203                 (type == kVsub));
1204     UnimplementedDelegate(type);
1205   }
Delegate(InstructionType type,InstructionCondDtDQQ,Condition,DataType,DRegister,QRegister,QRegister)1206   virtual void Delegate(InstructionType type,
1207                         InstructionCondDtDQQ /*instruction*/,
1208                         Condition /*cond*/,
1209                         DataType /*dt*/,
1210                         DRegister /*rd*/,
1211                         QRegister /*rn*/,
1212                         QRegister /*rm*/) {
1213     USE(type);
1214     VIXL_ASSERT((type == kVaddhn) || (type == kVraddhn) || (type == kVrsubhn) ||
1215                 (type == kVsubhn));
1216     UnimplementedDelegate(type);
1217   }
Delegate(InstructionType type,InstructionCondDtQQD,Condition,DataType,QRegister,QRegister,DRegister)1218   virtual void Delegate(InstructionType type,
1219                         InstructionCondDtQQD /*instruction*/,
1220                         Condition /*cond*/,
1221                         DataType /*dt*/,
1222                         QRegister /*rd*/,
1223                         QRegister /*rn*/,
1224                         DRegister /*rm*/) {
1225     USE(type);
1226     VIXL_ASSERT((type == kVaddw) || (type == kVsubw));
1227     UnimplementedDelegate(type);
1228   }
Delegate(InstructionType type,InstructionCondDtDDDop,Condition,DataType,DRegister,DRegister,const DOperand &)1229   virtual void Delegate(InstructionType type,
1230                         InstructionCondDtDDDop /*instruction*/,
1231                         Condition /*cond*/,
1232                         DataType /*dt*/,
1233                         DRegister /*rd*/,
1234                         DRegister /*rn*/,
1235                         const DOperand& /*operand*/) {
1236     USE(type);
1237     VIXL_ASSERT((type == kVand) || (type == kVbic) || (type == kVceq) ||
1238                 (type == kVcge) || (type == kVcgt) || (type == kVcle) ||
1239                 (type == kVclt) || (type == kVorn) || (type == kVorr) ||
1240                 (type == kVqshl) || (type == kVqshlu) || (type == kVrshr) ||
1241                 (type == kVrsra) || (type == kVshl) || (type == kVshr) ||
1242                 (type == kVsli) || (type == kVsra) || (type == kVsri));
1243     UnimplementedDelegate(type);
1244   }
Delegate(InstructionType type,InstructionCondDtQQQop,Condition,DataType,QRegister,QRegister,const QOperand &)1245   virtual void Delegate(InstructionType type,
1246                         InstructionCondDtQQQop /*instruction*/,
1247                         Condition /*cond*/,
1248                         DataType /*dt*/,
1249                         QRegister /*rd*/,
1250                         QRegister /*rn*/,
1251                         const QOperand& /*operand*/) {
1252     USE(type);
1253     VIXL_ASSERT((type == kVand) || (type == kVbic) || (type == kVceq) ||
1254                 (type == kVcge) || (type == kVcgt) || (type == kVcle) ||
1255                 (type == kVclt) || (type == kVorn) || (type == kVorr) ||
1256                 (type == kVqshl) || (type == kVqshlu) || (type == kVrshr) ||
1257                 (type == kVrsra) || (type == kVshl) || (type == kVshr) ||
1258                 (type == kVsli) || (type == kVsra) || (type == kVsri));
1259     UnimplementedDelegate(type);
1260   }
Delegate(InstructionType type,InstructionCondDtSSop,Condition,DataType,SRegister,const SOperand &)1261   virtual void Delegate(InstructionType type,
1262                         InstructionCondDtSSop /*instruction*/,
1263                         Condition /*cond*/,
1264                         DataType /*dt*/,
1265                         SRegister /*rd*/,
1266                         const SOperand& /*operand*/) {
1267     USE(type);
1268     VIXL_ASSERT((type == kVcmp) || (type == kVcmpe) || (type == kVmov));
1269     UnimplementedDelegate(type);
1270   }
Delegate(InstructionType type,InstructionCondDtDDop,Condition,DataType,DRegister,const DOperand &)1271   virtual void Delegate(InstructionType type,
1272                         InstructionCondDtDDop /*instruction*/,
1273                         Condition /*cond*/,
1274                         DataType /*dt*/,
1275                         DRegister /*rd*/,
1276                         const DOperand& /*operand*/) {
1277     USE(type);
1278     VIXL_ASSERT((type == kVcmp) || (type == kVcmpe) || (type == kVmov) ||
1279                 (type == kVmvn));
1280     UnimplementedDelegate(type);
1281   }
Delegate(InstructionType type,InstructionCondDtDtDS,Condition,DataType,DataType,DRegister,SRegister)1282   virtual void Delegate(InstructionType type,
1283                         InstructionCondDtDtDS /*instruction*/,
1284                         Condition /*cond*/,
1285                         DataType /*dt1*/,
1286                         DataType /*dt2*/,
1287                         DRegister /*rd*/,
1288                         SRegister /*rm*/) {
1289     USE(type);
1290     VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtt));
1291     UnimplementedDelegate(type);
1292   }
Delegate(InstructionType type,InstructionCondDtDtSD,Condition,DataType,DataType,SRegister,DRegister)1293   virtual void Delegate(InstructionType type,
1294                         InstructionCondDtDtSD /*instruction*/,
1295                         Condition /*cond*/,
1296                         DataType /*dt1*/,
1297                         DataType /*dt2*/,
1298                         SRegister /*rd*/,
1299                         DRegister /*rm*/) {
1300     USE(type);
1301     VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtr) ||
1302                 (type == kVcvtt));
1303     UnimplementedDelegate(type);
1304   }
Delegate(InstructionType type,InstructionCondDtDtDDSi,Condition,DataType,DataType,DRegister,DRegister,int32_t)1305   virtual void Delegate(InstructionType type,
1306                         InstructionCondDtDtDDSi /*instruction*/,
1307                         Condition /*cond*/,
1308                         DataType /*dt1*/,
1309                         DataType /*dt2*/,
1310                         DRegister /*rd*/,
1311                         DRegister /*rm*/,
1312                         int32_t /*fbits*/) {
1313     USE(type);
1314     VIXL_ASSERT((type == kVcvt));
1315     UnimplementedDelegate(type);
1316   }
Delegate(InstructionType type,InstructionCondDtDtQQSi,Condition,DataType,DataType,QRegister,QRegister,int32_t)1317   virtual void Delegate(InstructionType type,
1318                         InstructionCondDtDtQQSi /*instruction*/,
1319                         Condition /*cond*/,
1320                         DataType /*dt1*/,
1321                         DataType /*dt2*/,
1322                         QRegister /*rd*/,
1323                         QRegister /*rm*/,
1324                         int32_t /*fbits*/) {
1325     USE(type);
1326     VIXL_ASSERT((type == kVcvt));
1327     UnimplementedDelegate(type);
1328   }
Delegate(InstructionType type,InstructionCondDtDtSSSi,Condition,DataType,DataType,SRegister,SRegister,int32_t)1329   virtual void Delegate(InstructionType type,
1330                         InstructionCondDtDtSSSi /*instruction*/,
1331                         Condition /*cond*/,
1332                         DataType /*dt1*/,
1333                         DataType /*dt2*/,
1334                         SRegister /*rd*/,
1335                         SRegister /*rm*/,
1336                         int32_t /*fbits*/) {
1337     USE(type);
1338     VIXL_ASSERT((type == kVcvt));
1339     UnimplementedDelegate(type);
1340   }
Delegate(InstructionType type,InstructionCondDtDtDD,Condition,DataType,DataType,DRegister,DRegister)1341   virtual void Delegate(InstructionType type,
1342                         InstructionCondDtDtDD /*instruction*/,
1343                         Condition /*cond*/,
1344                         DataType /*dt1*/,
1345                         DataType /*dt2*/,
1346                         DRegister /*rd*/,
1347                         DRegister /*rm*/) {
1348     USE(type);
1349     VIXL_ASSERT((type == kVcvt));
1350     UnimplementedDelegate(type);
1351   }
Delegate(InstructionType type,InstructionCondDtDtQQ,Condition,DataType,DataType,QRegister,QRegister)1352   virtual void Delegate(InstructionType type,
1353                         InstructionCondDtDtQQ /*instruction*/,
1354                         Condition /*cond*/,
1355                         DataType /*dt1*/,
1356                         DataType /*dt2*/,
1357                         QRegister /*rd*/,
1358                         QRegister /*rm*/) {
1359     USE(type);
1360     VIXL_ASSERT((type == kVcvt));
1361     UnimplementedDelegate(type);
1362   }
Delegate(InstructionType type,InstructionCondDtDtDQ,Condition,DataType,DataType,DRegister,QRegister)1363   virtual void Delegate(InstructionType type,
1364                         InstructionCondDtDtDQ /*instruction*/,
1365                         Condition /*cond*/,
1366                         DataType /*dt1*/,
1367                         DataType /*dt2*/,
1368                         DRegister /*rd*/,
1369                         QRegister /*rm*/) {
1370     USE(type);
1371     VIXL_ASSERT((type == kVcvt));
1372     UnimplementedDelegate(type);
1373   }
Delegate(InstructionType type,InstructionCondDtDtQD,Condition,DataType,DataType,QRegister,DRegister)1374   virtual void Delegate(InstructionType type,
1375                         InstructionCondDtDtQD /*instruction*/,
1376                         Condition /*cond*/,
1377                         DataType /*dt1*/,
1378                         DataType /*dt2*/,
1379                         QRegister /*rd*/,
1380                         DRegister /*rm*/) {
1381     USE(type);
1382     VIXL_ASSERT((type == kVcvt));
1383     UnimplementedDelegate(type);
1384   }
Delegate(InstructionType type,InstructionCondDtDtSS,Condition,DataType,DataType,SRegister,SRegister)1385   virtual void Delegate(InstructionType type,
1386                         InstructionCondDtDtSS /*instruction*/,
1387                         Condition /*cond*/,
1388                         DataType /*dt1*/,
1389                         DataType /*dt2*/,
1390                         SRegister /*rd*/,
1391                         SRegister /*rm*/) {
1392     USE(type);
1393     VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtr) ||
1394                 (type == kVcvtt));
1395     UnimplementedDelegate(type);
1396   }
Delegate(InstructionType type,InstructionDtDtDD,DataType,DataType,DRegister,DRegister)1397   virtual void Delegate(InstructionType type,
1398                         InstructionDtDtDD /*instruction*/,
1399                         DataType /*dt1*/,
1400                         DataType /*dt2*/,
1401                         DRegister /*rd*/,
1402                         DRegister /*rm*/) {
1403     USE(type);
1404     VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) ||
1405                 (type == kVcvtp));
1406     UnimplementedDelegate(type);
1407   }
Delegate(InstructionType type,InstructionDtDtQQ,DataType,DataType,QRegister,QRegister)1408   virtual void Delegate(InstructionType type,
1409                         InstructionDtDtQQ /*instruction*/,
1410                         DataType /*dt1*/,
1411                         DataType /*dt2*/,
1412                         QRegister /*rd*/,
1413                         QRegister /*rm*/) {
1414     USE(type);
1415     VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) ||
1416                 (type == kVcvtp));
1417     UnimplementedDelegate(type);
1418   }
Delegate(InstructionType type,InstructionDtDtSS,DataType,DataType,SRegister,SRegister)1419   virtual void Delegate(InstructionType type,
1420                         InstructionDtDtSS /*instruction*/,
1421                         DataType /*dt1*/,
1422                         DataType /*dt2*/,
1423                         SRegister /*rd*/,
1424                         SRegister /*rm*/) {
1425     USE(type);
1426     VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) ||
1427                 (type == kVcvtp));
1428     UnimplementedDelegate(type);
1429   }
Delegate(InstructionType type,InstructionDtDtSD,DataType,DataType,SRegister,DRegister)1430   virtual void Delegate(InstructionType type,
1431                         InstructionDtDtSD /*instruction*/,
1432                         DataType /*dt1*/,
1433                         DataType /*dt2*/,
1434                         SRegister /*rd*/,
1435                         DRegister /*rm*/) {
1436     USE(type);
1437     VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) ||
1438                 (type == kVcvtp));
1439     UnimplementedDelegate(type);
1440   }
Delegate(InstructionType type,InstructionCondDtQR,Condition,DataType,QRegister,Register)1441   virtual void Delegate(InstructionType type,
1442                         InstructionCondDtQR /*instruction*/,
1443                         Condition /*cond*/,
1444                         DataType /*dt*/,
1445                         QRegister /*rd*/,
1446                         Register /*rt*/) {
1447     USE(type);
1448     VIXL_ASSERT((type == kVdup));
1449     UnimplementedDelegate(type);
1450   }
Delegate(InstructionType type,InstructionCondDtDR,Condition,DataType,DRegister,Register)1451   virtual void Delegate(InstructionType type,
1452                         InstructionCondDtDR /*instruction*/,
1453                         Condition /*cond*/,
1454                         DataType /*dt*/,
1455                         DRegister /*rd*/,
1456                         Register /*rt*/) {
1457     USE(type);
1458     VIXL_ASSERT((type == kVdup));
1459     UnimplementedDelegate(type);
1460   }
Delegate(InstructionType type,InstructionCondDtDDx,Condition,DataType,DRegister,DRegisterLane)1461   virtual void Delegate(InstructionType type,
1462                         InstructionCondDtDDx /*instruction*/,
1463                         Condition /*cond*/,
1464                         DataType /*dt*/,
1465                         DRegister /*rd*/,
1466                         DRegisterLane /*rm*/) {
1467     USE(type);
1468     VIXL_ASSERT((type == kVdup));
1469     UnimplementedDelegate(type);
1470   }
Delegate(InstructionType type,InstructionCondDtQDx,Condition,DataType,QRegister,DRegisterLane)1471   virtual void Delegate(InstructionType type,
1472                         InstructionCondDtQDx /*instruction*/,
1473                         Condition /*cond*/,
1474                         DataType /*dt*/,
1475                         QRegister /*rd*/,
1476                         DRegisterLane /*rm*/) {
1477     USE(type);
1478     VIXL_ASSERT((type == kVdup));
1479     UnimplementedDelegate(type);
1480   }
Delegate(InstructionType type,InstructionCondDtDDDDop,Condition,DataType,DRegister,DRegister,DRegister,const DOperand &)1481   virtual void Delegate(InstructionType type,
1482                         InstructionCondDtDDDDop /*instruction*/,
1483                         Condition /*cond*/,
1484                         DataType /*dt*/,
1485                         DRegister /*rd*/,
1486                         DRegister /*rn*/,
1487                         DRegister /*rm*/,
1488                         const DOperand& /*operand*/) {
1489     USE(type);
1490     VIXL_ASSERT((type == kVext));
1491     UnimplementedDelegate(type);
1492   }
Delegate(InstructionType type,InstructionCondDtQQQQop,Condition,DataType,QRegister,QRegister,QRegister,const QOperand &)1493   virtual void Delegate(InstructionType type,
1494                         InstructionCondDtQQQQop /*instruction*/,
1495                         Condition /*cond*/,
1496                         DataType /*dt*/,
1497                         QRegister /*rd*/,
1498                         QRegister /*rn*/,
1499                         QRegister /*rm*/,
1500                         const QOperand& /*operand*/) {
1501     USE(type);
1502     VIXL_ASSERT((type == kVext));
1503     UnimplementedDelegate(type);
1504   }
Delegate(InstructionType type,InstructionCondDtNrlAmop,Condition,DataType,const NeonRegisterList &,const AlignedMemOperand &)1505   virtual void Delegate(InstructionType type,
1506                         InstructionCondDtNrlAmop /*instruction*/,
1507                         Condition /*cond*/,
1508                         DataType /*dt*/,
1509                         const NeonRegisterList& /*nreglist*/,
1510                         const AlignedMemOperand& /*operand*/) {
1511     USE(type);
1512     VIXL_ASSERT((type == kVld1) || (type == kVld2) || (type == kVld3) ||
1513                 (type == kVld4) || (type == kVst1) || (type == kVst2) ||
1514                 (type == kVst3) || (type == kVst4));
1515     UnimplementedDelegate(type);
1516   }
Delegate(InstructionType type,InstructionCondDtNrlMop,Condition,DataType,const NeonRegisterList &,const MemOperand &)1517   virtual void Delegate(InstructionType type,
1518                         InstructionCondDtNrlMop /*instruction*/,
1519                         Condition /*cond*/,
1520                         DataType /*dt*/,
1521                         const NeonRegisterList& /*nreglist*/,
1522                         const MemOperand& /*operand*/) {
1523     USE(type);
1524     VIXL_ASSERT((type == kVld3) || (type == kVst3));
1525     UnimplementedDelegate(type);
1526   }
Delegate(InstructionType type,InstructionCondDtRwbDrl,Condition,DataType,Register,WriteBack,DRegisterList)1527   virtual void Delegate(InstructionType type,
1528                         InstructionCondDtRwbDrl /*instruction*/,
1529                         Condition /*cond*/,
1530                         DataType /*dt*/,
1531                         Register /*rn*/,
1532                         WriteBack /*write_back*/,
1533                         DRegisterList /*dreglist*/) {
1534     USE(type);
1535     VIXL_ASSERT((type == kVldm) || (type == kVldmdb) || (type == kVldmia) ||
1536                 (type == kVstm) || (type == kVstmdb) || (type == kVstmia));
1537     UnimplementedDelegate(type);
1538   }
Delegate(InstructionType type,InstructionCondDtRwbSrl,Condition,DataType,Register,WriteBack,SRegisterList)1539   virtual void Delegate(InstructionType type,
1540                         InstructionCondDtRwbSrl /*instruction*/,
1541                         Condition /*cond*/,
1542                         DataType /*dt*/,
1543                         Register /*rn*/,
1544                         WriteBack /*write_back*/,
1545                         SRegisterList /*sreglist*/) {
1546     USE(type);
1547     VIXL_ASSERT((type == kVldm) || (type == kVldmdb) || (type == kVldmia) ||
1548                 (type == kVstm) || (type == kVstmdb) || (type == kVstmia));
1549     UnimplementedDelegate(type);
1550   }
Delegate(InstructionType type,InstructionCondDtDL,Condition,DataType,DRegister,Location *)1551   virtual void Delegate(InstructionType type,
1552                         InstructionCondDtDL /*instruction*/,
1553                         Condition /*cond*/,
1554                         DataType /*dt*/,
1555                         DRegister /*rd*/,
1556                         Location* /*location*/) {
1557     USE(type);
1558     VIXL_ASSERT((type == kVldr));
1559     UnimplementedDelegate(type);
1560   }
Delegate(InstructionType type,InstructionCondDtDMop,Condition,DataType,DRegister,const MemOperand &)1561   virtual void Delegate(InstructionType type,
1562                         InstructionCondDtDMop /*instruction*/,
1563                         Condition /*cond*/,
1564                         DataType /*dt*/,
1565                         DRegister /*rd*/,
1566                         const MemOperand& /*operand*/) {
1567     USE(type);
1568     VIXL_ASSERT((type == kVldr) || (type == kVstr));
1569     UnimplementedDelegate(type);
1570   }
Delegate(InstructionType type,InstructionCondDtSL,Condition,DataType,SRegister,Location *)1571   virtual void Delegate(InstructionType type,
1572                         InstructionCondDtSL /*instruction*/,
1573                         Condition /*cond*/,
1574                         DataType /*dt*/,
1575                         SRegister /*rd*/,
1576                         Location* /*location*/) {
1577     USE(type);
1578     VIXL_ASSERT((type == kVldr));
1579     UnimplementedDelegate(type);
1580   }
Delegate(InstructionType type,InstructionCondDtSMop,Condition,DataType,SRegister,const MemOperand &)1581   virtual void Delegate(InstructionType type,
1582                         InstructionCondDtSMop /*instruction*/,
1583                         Condition /*cond*/,
1584                         DataType /*dt*/,
1585                         SRegister /*rd*/,
1586                         const MemOperand& /*operand*/) {
1587     USE(type);
1588     VIXL_ASSERT((type == kVldr) || (type == kVstr));
1589     UnimplementedDelegate(type);
1590   }
Delegate(InstructionType type,InstructionDtDDD,DataType,DRegister,DRegister,DRegister)1591   virtual void Delegate(InstructionType type,
1592                         InstructionDtDDD /*instruction*/,
1593                         DataType /*dt*/,
1594                         DRegister /*rd*/,
1595                         DRegister /*rn*/,
1596                         DRegister /*rm*/) {
1597     USE(type);
1598     VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm) || (type == kVseleq) ||
1599                 (type == kVselge) || (type == kVselgt) || (type == kVselvs));
1600     UnimplementedDelegate(type);
1601   }
Delegate(InstructionType type,InstructionDtSSS,DataType,SRegister,SRegister,SRegister)1602   virtual void Delegate(InstructionType type,
1603                         InstructionDtSSS /*instruction*/,
1604                         DataType /*dt*/,
1605                         SRegister /*rd*/,
1606                         SRegister /*rn*/,
1607                         SRegister /*rm*/) {
1608     USE(type);
1609     VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm) || (type == kVseleq) ||
1610                 (type == kVselge) || (type == kVselgt) || (type == kVselvs));
1611     UnimplementedDelegate(type);
1612   }
Delegate(InstructionType type,InstructionCondDtDDDx,Condition,DataType,DRegister,DRegister,DRegisterLane)1613   virtual void Delegate(InstructionType type,
1614                         InstructionCondDtDDDx /*instruction*/,
1615                         Condition /*cond*/,
1616                         DataType /*dt*/,
1617                         DRegister /*rd*/,
1618                         DRegister /*rn*/,
1619                         DRegisterLane /*rm*/) {
1620     USE(type);
1621     VIXL_ASSERT((type == kVmla) || (type == kVmls) || (type == kVqdmulh) ||
1622                 (type == kVqrdmulh));
1623     UnimplementedDelegate(type);
1624   }
Delegate(InstructionType type,InstructionCondDtQQDx,Condition,DataType,QRegister,QRegister,DRegisterLane)1625   virtual void Delegate(InstructionType type,
1626                         InstructionCondDtQQDx /*instruction*/,
1627                         Condition /*cond*/,
1628                         DataType /*dt*/,
1629                         QRegister /*rd*/,
1630                         QRegister /*rn*/,
1631                         DRegisterLane /*rm*/) {
1632     USE(type);
1633     VIXL_ASSERT((type == kVmla) || (type == kVmls) || (type == kVqdmulh) ||
1634                 (type == kVqrdmulh));
1635     UnimplementedDelegate(type);
1636   }
Delegate(InstructionType type,InstructionCondDtQDDx,Condition,DataType,QRegister,DRegister,DRegisterLane)1637   virtual void Delegate(InstructionType type,
1638                         InstructionCondDtQDDx /*instruction*/,
1639                         Condition /*cond*/,
1640                         DataType /*dt*/,
1641                         QRegister /*rd*/,
1642                         DRegister /*rn*/,
1643                         DRegisterLane /*rm*/) {
1644     USE(type);
1645     VIXL_ASSERT((type == kVmlal) || (type == kVmlsl) || (type == kVqdmull));
1646     UnimplementedDelegate(type);
1647   }
Delegate(InstructionType type,InstructionCondRS,Condition,Register,SRegister)1648   virtual void Delegate(InstructionType type,
1649                         InstructionCondRS /*instruction*/,
1650                         Condition /*cond*/,
1651                         Register /*rt*/,
1652                         SRegister /*rn*/) {
1653     USE(type);
1654     VIXL_ASSERT((type == kVmov));
1655     UnimplementedDelegate(type);
1656   }
Delegate(InstructionType type,InstructionCondSR,Condition,SRegister,Register)1657   virtual void Delegate(InstructionType type,
1658                         InstructionCondSR /*instruction*/,
1659                         Condition /*cond*/,
1660                         SRegister /*rn*/,
1661                         Register /*rt*/) {
1662     USE(type);
1663     VIXL_ASSERT((type == kVmov));
1664     UnimplementedDelegate(type);
1665   }
Delegate(InstructionType type,InstructionCondRRD,Condition,Register,Register,DRegister)1666   virtual void Delegate(InstructionType type,
1667                         InstructionCondRRD /*instruction*/,
1668                         Condition /*cond*/,
1669                         Register /*rt*/,
1670                         Register /*rt2*/,
1671                         DRegister /*rm*/) {
1672     USE(type);
1673     VIXL_ASSERT((type == kVmov));
1674     UnimplementedDelegate(type);
1675   }
Delegate(InstructionType type,InstructionCondDRR,Condition,DRegister,Register,Register)1676   virtual void Delegate(InstructionType type,
1677                         InstructionCondDRR /*instruction*/,
1678                         Condition /*cond*/,
1679                         DRegister /*rm*/,
1680                         Register /*rt*/,
1681                         Register /*rt2*/) {
1682     USE(type);
1683     VIXL_ASSERT((type == kVmov));
1684     UnimplementedDelegate(type);
1685   }
Delegate(InstructionType type,InstructionCondRRSS,Condition,Register,Register,SRegister,SRegister)1686   virtual void Delegate(InstructionType type,
1687                         InstructionCondRRSS /*instruction*/,
1688                         Condition /*cond*/,
1689                         Register /*rt*/,
1690                         Register /*rt2*/,
1691                         SRegister /*rm*/,
1692                         SRegister /*rm1*/) {
1693     USE(type);
1694     VIXL_ASSERT((type == kVmov));
1695     UnimplementedDelegate(type);
1696   }
Delegate(InstructionType type,InstructionCondSSRR,Condition,SRegister,SRegister,Register,Register)1697   virtual void Delegate(InstructionType type,
1698                         InstructionCondSSRR /*instruction*/,
1699                         Condition /*cond*/,
1700                         SRegister /*rm*/,
1701                         SRegister /*rm1*/,
1702                         Register /*rt*/,
1703                         Register /*rt2*/) {
1704     USE(type);
1705     VIXL_ASSERT((type == kVmov));
1706     UnimplementedDelegate(type);
1707   }
Delegate(InstructionType type,InstructionCondDtDxR,Condition,DataType,DRegisterLane,Register)1708   virtual void Delegate(InstructionType type,
1709                         InstructionCondDtDxR /*instruction*/,
1710                         Condition /*cond*/,
1711                         DataType /*dt*/,
1712                         DRegisterLane /*rd*/,
1713                         Register /*rt*/) {
1714     USE(type);
1715     VIXL_ASSERT((type == kVmov));
1716     UnimplementedDelegate(type);
1717   }
Delegate(InstructionType type,InstructionCondDtQQop,Condition,DataType,QRegister,const QOperand &)1718   virtual void Delegate(InstructionType type,
1719                         InstructionCondDtQQop /*instruction*/,
1720                         Condition /*cond*/,
1721                         DataType /*dt*/,
1722                         QRegister /*rd*/,
1723                         const QOperand& /*operand*/) {
1724     USE(type);
1725     VIXL_ASSERT((type == kVmov) || (type == kVmvn));
1726     UnimplementedDelegate(type);
1727   }
Delegate(InstructionType type,InstructionCondDtRDx,Condition,DataType,Register,DRegisterLane)1728   virtual void Delegate(InstructionType type,
1729                         InstructionCondDtRDx /*instruction*/,
1730                         Condition /*cond*/,
1731                         DataType /*dt*/,
1732                         Register /*rt*/,
1733                         DRegisterLane /*rn*/) {
1734     USE(type);
1735     VIXL_ASSERT((type == kVmov));
1736     UnimplementedDelegate(type);
1737   }
Delegate(InstructionType type,InstructionCondDtQD,Condition,DataType,QRegister,DRegister)1738   virtual void Delegate(InstructionType type,
1739                         InstructionCondDtQD /*instruction*/,
1740                         Condition /*cond*/,
1741                         DataType /*dt*/,
1742                         QRegister /*rd*/,
1743                         DRegister /*rm*/) {
1744     USE(type);
1745     VIXL_ASSERT((type == kVmovl));
1746     UnimplementedDelegate(type);
1747   }
Delegate(InstructionType type,InstructionCondDtDQ,Condition,DataType,DRegister,QRegister)1748   virtual void Delegate(InstructionType type,
1749                         InstructionCondDtDQ /*instruction*/,
1750                         Condition /*cond*/,
1751                         DataType /*dt*/,
1752                         DRegister /*rd*/,
1753                         QRegister /*rm*/) {
1754     USE(type);
1755     VIXL_ASSERT((type == kVmovn) || (type == kVqmovn) || (type == kVqmovun));
1756     UnimplementedDelegate(type);
1757   }
Delegate(InstructionType type,InstructionCondRoaSfp,Condition,RegisterOrAPSR_nzcv,SpecialFPRegister)1758   virtual void Delegate(InstructionType type,
1759                         InstructionCondRoaSfp /*instruction*/,
1760                         Condition /*cond*/,
1761                         RegisterOrAPSR_nzcv /*rt*/,
1762                         SpecialFPRegister /*spec_reg*/) {
1763     USE(type);
1764     VIXL_ASSERT((type == kVmrs));
1765     UnimplementedDelegate(type);
1766   }
Delegate(InstructionType type,InstructionCondSfpR,Condition,SpecialFPRegister,Register)1767   virtual void Delegate(InstructionType type,
1768                         InstructionCondSfpR /*instruction*/,
1769                         Condition /*cond*/,
1770                         SpecialFPRegister /*spec_reg*/,
1771                         Register /*rt*/) {
1772     USE(type);
1773     VIXL_ASSERT((type == kVmsr));
1774     UnimplementedDelegate(type);
1775   }
Delegate(InstructionType type,InstructionCondDtDDIr,Condition,DataType,DRegister,DRegister,DRegister,unsigned)1776   virtual void Delegate(InstructionType type,
1777                         InstructionCondDtDDIr /*instruction*/,
1778                         Condition /*cond*/,
1779                         DataType /*dt*/,
1780                         DRegister /*rd*/,
1781                         DRegister /*rn*/,
1782                         DRegister /*dm*/,
1783                         unsigned /*index*/) {
1784     USE(type);
1785     VIXL_ASSERT((type == kVmul));
1786     UnimplementedDelegate(type);
1787   }
Delegate(InstructionType type,InstructionCondDtQQIr,Condition,DataType,QRegister,QRegister,DRegister,unsigned)1788   virtual void Delegate(InstructionType type,
1789                         InstructionCondDtQQIr /*instruction*/,
1790                         Condition /*cond*/,
1791                         DataType /*dt*/,
1792                         QRegister /*rd*/,
1793                         QRegister /*rn*/,
1794                         DRegister /*dm*/,
1795                         unsigned /*index*/) {
1796     USE(type);
1797     VIXL_ASSERT((type == kVmul));
1798     UnimplementedDelegate(type);
1799   }
Delegate(InstructionType type,InstructionCondDtQDIr,Condition,DataType,QRegister,DRegister,DRegister,unsigned)1800   virtual void Delegate(InstructionType type,
1801                         InstructionCondDtQDIr /*instruction*/,
1802                         Condition /*cond*/,
1803                         DataType /*dt*/,
1804                         QRegister /*rd*/,
1805                         DRegister /*rn*/,
1806                         DRegister /*dm*/,
1807                         unsigned /*index*/) {
1808     USE(type);
1809     VIXL_ASSERT((type == kVmull) || (type == kVqdmlal) || (type == kVqdmlsl));
1810     UnimplementedDelegate(type);
1811   }
Delegate(InstructionType type,InstructionCondDtDrl,Condition,DataType,DRegisterList)1812   virtual void Delegate(InstructionType type,
1813                         InstructionCondDtDrl /*instruction*/,
1814                         Condition /*cond*/,
1815                         DataType /*dt*/,
1816                         DRegisterList /*dreglist*/) {
1817     USE(type);
1818     VIXL_ASSERT((type == kVpop) || (type == kVpush));
1819     UnimplementedDelegate(type);
1820   }
Delegate(InstructionType type,InstructionCondDtSrl,Condition,DataType,SRegisterList)1821   virtual void Delegate(InstructionType type,
1822                         InstructionCondDtSrl /*instruction*/,
1823                         Condition /*cond*/,
1824                         DataType /*dt*/,
1825                         SRegisterList /*sreglist*/) {
1826     USE(type);
1827     VIXL_ASSERT((type == kVpop) || (type == kVpush));
1828     UnimplementedDelegate(type);
1829   }
Delegate(InstructionType type,InstructionCondDtDQQop,Condition,DataType,DRegister,QRegister,const QOperand &)1830   virtual void Delegate(InstructionType type,
1831                         InstructionCondDtDQQop /*instruction*/,
1832                         Condition /*cond*/,
1833                         DataType /*dt*/,
1834                         DRegister /*rd*/,
1835                         QRegister /*rm*/,
1836                         const QOperand& /*operand*/) {
1837     USE(type);
1838     VIXL_ASSERT((type == kVqrshrn) || (type == kVqrshrun) ||
1839                 (type == kVqshrn) || (type == kVqshrun) || (type == kVrshrn) ||
1840                 (type == kVshrn));
1841     UnimplementedDelegate(type);
1842   }
Delegate(InstructionType type,InstructionDtDD,DataType,DRegister,DRegister)1843   virtual void Delegate(InstructionType type,
1844                         InstructionDtDD /*instruction*/,
1845                         DataType /*dt*/,
1846                         DRegister /*rd*/,
1847                         DRegister /*rm*/) {
1848     USE(type);
1849     VIXL_ASSERT((type == kVrinta) || (type == kVrintm) || (type == kVrintn) ||
1850                 (type == kVrintp));
1851     UnimplementedDelegate(type);
1852   }
Delegate(InstructionType type,InstructionDtSS,DataType,SRegister,SRegister)1853   virtual void Delegate(InstructionType type,
1854                         InstructionDtSS /*instruction*/,
1855                         DataType /*dt*/,
1856                         SRegister /*rd*/,
1857                         SRegister /*rm*/) {
1858     USE(type);
1859     VIXL_ASSERT((type == kVrinta) || (type == kVrintm) || (type == kVrintn) ||
1860                 (type == kVrintp));
1861     UnimplementedDelegate(type);
1862   }
Delegate(InstructionType type,InstructionCondDtQDDop,Condition,DataType,QRegister,DRegister,const DOperand &)1863   virtual void Delegate(InstructionType type,
1864                         InstructionCondDtQDDop /*instruction*/,
1865                         Condition /*cond*/,
1866                         DataType /*dt*/,
1867                         QRegister /*rd*/,
1868                         DRegister /*rm*/,
1869                         const DOperand& /*operand*/) {
1870     USE(type);
1871     VIXL_ASSERT((type == kVshll));
1872     UnimplementedDelegate(type);
1873   }
Delegate(InstructionType type,InstructionCondDtDNrlD,Condition,DataType,DRegister,const NeonRegisterList &,DRegister)1874   virtual void Delegate(InstructionType type,
1875                         InstructionCondDtDNrlD /*instruction*/,
1876                         Condition /*cond*/,
1877                         DataType /*dt*/,
1878                         DRegister /*rd*/,
1879                         const NeonRegisterList& /*nreglist*/,
1880                         DRegister /*rm*/) {
1881     USE(type);
1882     VIXL_ASSERT((type == kVtbl) || (type == kVtbx));
1883     UnimplementedDelegate(type);
1884   }
1885 
1886   void adc(Condition cond,
1887            EncodingSize size,
1888            Register rd,
1889            Register rn,
1890            const Operand& operand);
adc(Register rd,Register rn,const Operand & operand)1891   void adc(Register rd, Register rn, const Operand& operand) {
1892     adc(al, Best, rd, rn, operand);
1893   }
adc(Condition cond,Register rd,Register rn,const Operand & operand)1894   void adc(Condition cond, Register rd, Register rn, const Operand& operand) {
1895     adc(cond, Best, rd, rn, operand);
1896   }
adc(EncodingSize size,Register rd,Register rn,const Operand & operand)1897   void adc(EncodingSize size,
1898            Register rd,
1899            Register rn,
1900            const Operand& operand) {
1901     adc(al, size, rd, rn, operand);
1902   }
1903 
1904   void adcs(Condition cond,
1905             EncodingSize size,
1906             Register rd,
1907             Register rn,
1908             const Operand& operand);
adcs(Register rd,Register rn,const Operand & operand)1909   void adcs(Register rd, Register rn, const Operand& operand) {
1910     adcs(al, Best, rd, rn, operand);
1911   }
adcs(Condition cond,Register rd,Register rn,const Operand & operand)1912   void adcs(Condition cond, Register rd, Register rn, const Operand& operand) {
1913     adcs(cond, Best, rd, rn, operand);
1914   }
adcs(EncodingSize size,Register rd,Register rn,const Operand & operand)1915   void adcs(EncodingSize size,
1916             Register rd,
1917             Register rn,
1918             const Operand& operand) {
1919     adcs(al, size, rd, rn, operand);
1920   }
1921 
1922   void add(Condition cond,
1923            EncodingSize size,
1924            Register rd,
1925            Register rn,
1926            const Operand& operand);
add(Register rd,Register rn,const Operand & operand)1927   void add(Register rd, Register rn, const Operand& operand) {
1928     add(al, Best, rd, rn, operand);
1929   }
add(Condition cond,Register rd,Register rn,const Operand & operand)1930   void add(Condition cond, Register rd, Register rn, const Operand& operand) {
1931     add(cond, Best, rd, rn, operand);
1932   }
add(EncodingSize size,Register rd,Register rn,const Operand & operand)1933   void add(EncodingSize size,
1934            Register rd,
1935            Register rn,
1936            const Operand& operand) {
1937     add(al, size, rd, rn, operand);
1938   }
1939 
1940   void add(Condition cond, Register rd, const Operand& operand);
add(Register rd,const Operand & operand)1941   void add(Register rd, const Operand& operand) { add(al, rd, operand); }
1942 
1943   void adds(Condition cond,
1944             EncodingSize size,
1945             Register rd,
1946             Register rn,
1947             const Operand& operand);
adds(Register rd,Register rn,const Operand & operand)1948   void adds(Register rd, Register rn, const Operand& operand) {
1949     adds(al, Best, rd, rn, operand);
1950   }
adds(Condition cond,Register rd,Register rn,const Operand & operand)1951   void adds(Condition cond, Register rd, Register rn, const Operand& operand) {
1952     adds(cond, Best, rd, rn, operand);
1953   }
adds(EncodingSize size,Register rd,Register rn,const Operand & operand)1954   void adds(EncodingSize size,
1955             Register rd,
1956             Register rn,
1957             const Operand& operand) {
1958     adds(al, size, rd, rn, operand);
1959   }
1960 
1961   void adds(Register rd, const Operand& operand);
1962 
1963   void addw(Condition cond, Register rd, Register rn, const Operand& operand);
addw(Register rd,Register rn,const Operand & operand)1964   void addw(Register rd, Register rn, const Operand& operand) {
1965     addw(al, rd, rn, operand);
1966   }
1967 
1968   void adr(Condition cond, EncodingSize size, Register rd, Location* location);
1969   bool adr_info(Condition cond,
1970                 EncodingSize size,
1971                 Register rd,
1972                 Location* location,
1973                 const struct ReferenceInfo** info);
adr(Register rd,Location * location)1974   void adr(Register rd, Location* location) { adr(al, Best, rd, location); }
adr(Condition cond,Register rd,Location * location)1975   void adr(Condition cond, Register rd, Location* location) {
1976     adr(cond, Best, rd, location);
1977   }
adr(EncodingSize size,Register rd,Location * location)1978   void adr(EncodingSize size, Register rd, Location* location) {
1979     adr(al, size, rd, location);
1980   }
1981 
1982   void and_(Condition cond,
1983             EncodingSize size,
1984             Register rd,
1985             Register rn,
1986             const Operand& operand);
and_(Register rd,Register rn,const Operand & operand)1987   void and_(Register rd, Register rn, const Operand& operand) {
1988     and_(al, Best, rd, rn, operand);
1989   }
and_(Condition cond,Register rd,Register rn,const Operand & operand)1990   void and_(Condition cond, Register rd, Register rn, const Operand& operand) {
1991     and_(cond, Best, rd, rn, operand);
1992   }
and_(EncodingSize size,Register rd,Register rn,const Operand & operand)1993   void and_(EncodingSize size,
1994             Register rd,
1995             Register rn,
1996             const Operand& operand) {
1997     and_(al, size, rd, rn, operand);
1998   }
1999 
2000   void ands(Condition cond,
2001             EncodingSize size,
2002             Register rd,
2003             Register rn,
2004             const Operand& operand);
ands(Register rd,Register rn,const Operand & operand)2005   void ands(Register rd, Register rn, const Operand& operand) {
2006     ands(al, Best, rd, rn, operand);
2007   }
ands(Condition cond,Register rd,Register rn,const Operand & operand)2008   void ands(Condition cond, Register rd, Register rn, const Operand& operand) {
2009     ands(cond, Best, rd, rn, operand);
2010   }
ands(EncodingSize size,Register rd,Register rn,const Operand & operand)2011   void ands(EncodingSize size,
2012             Register rd,
2013             Register rn,
2014             const Operand& operand) {
2015     ands(al, size, rd, rn, operand);
2016   }
2017 
2018   void asr(Condition cond,
2019            EncodingSize size,
2020            Register rd,
2021            Register rm,
2022            const Operand& operand);
asr(Register rd,Register rm,const Operand & operand)2023   void asr(Register rd, Register rm, const Operand& operand) {
2024     asr(al, Best, rd, rm, operand);
2025   }
asr(Condition cond,Register rd,Register rm,const Operand & operand)2026   void asr(Condition cond, Register rd, Register rm, const Operand& operand) {
2027     asr(cond, Best, rd, rm, operand);
2028   }
asr(EncodingSize size,Register rd,Register rm,const Operand & operand)2029   void asr(EncodingSize size,
2030            Register rd,
2031            Register rm,
2032            const Operand& operand) {
2033     asr(al, size, rd, rm, operand);
2034   }
2035 
2036   void asrs(Condition cond,
2037             EncodingSize size,
2038             Register rd,
2039             Register rm,
2040             const Operand& operand);
asrs(Register rd,Register rm,const Operand & operand)2041   void asrs(Register rd, Register rm, const Operand& operand) {
2042     asrs(al, Best, rd, rm, operand);
2043   }
asrs(Condition cond,Register rd,Register rm,const Operand & operand)2044   void asrs(Condition cond, Register rd, Register rm, const Operand& operand) {
2045     asrs(cond, Best, rd, rm, operand);
2046   }
asrs(EncodingSize size,Register rd,Register rm,const Operand & operand)2047   void asrs(EncodingSize size,
2048             Register rd,
2049             Register rm,
2050             const Operand& operand) {
2051     asrs(al, size, rd, rm, operand);
2052   }
2053 
2054   void b(Condition cond, EncodingSize size, Location* location);
2055   bool b_info(Condition cond,
2056               EncodingSize size,
2057               Location* location,
2058               const struct ReferenceInfo** info);
b(Location * location)2059   void b(Location* location) { b(al, Best, location); }
b(Condition cond,Location * location)2060   void b(Condition cond, Location* location) { b(cond, Best, location); }
b(EncodingSize size,Location * location)2061   void b(EncodingSize size, Location* location) { b(al, size, location); }
2062 
2063   void bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width);
bfc(Register rd,uint32_t lsb,uint32_t width)2064   void bfc(Register rd, uint32_t lsb, uint32_t width) {
2065     bfc(al, rd, lsb, width);
2066   }
2067 
2068   void bfi(
2069       Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
bfi(Register rd,Register rn,uint32_t lsb,uint32_t width)2070   void bfi(Register rd, Register rn, uint32_t lsb, uint32_t width) {
2071     bfi(al, rd, rn, lsb, width);
2072   }
2073 
2074   void bic(Condition cond,
2075            EncodingSize size,
2076            Register rd,
2077            Register rn,
2078            const Operand& operand);
bic(Register rd,Register rn,const Operand & operand)2079   void bic(Register rd, Register rn, const Operand& operand) {
2080     bic(al, Best, rd, rn, operand);
2081   }
bic(Condition cond,Register rd,Register rn,const Operand & operand)2082   void bic(Condition cond, Register rd, Register rn, const Operand& operand) {
2083     bic(cond, Best, rd, rn, operand);
2084   }
bic(EncodingSize size,Register rd,Register rn,const Operand & operand)2085   void bic(EncodingSize size,
2086            Register rd,
2087            Register rn,
2088            const Operand& operand) {
2089     bic(al, size, rd, rn, operand);
2090   }
2091 
2092   void bics(Condition cond,
2093             EncodingSize size,
2094             Register rd,
2095             Register rn,
2096             const Operand& operand);
bics(Register rd,Register rn,const Operand & operand)2097   void bics(Register rd, Register rn, const Operand& operand) {
2098     bics(al, Best, rd, rn, operand);
2099   }
bics(Condition cond,Register rd,Register rn,const Operand & operand)2100   void bics(Condition cond, Register rd, Register rn, const Operand& operand) {
2101     bics(cond, Best, rd, rn, operand);
2102   }
bics(EncodingSize size,Register rd,Register rn,const Operand & operand)2103   void bics(EncodingSize size,
2104             Register rd,
2105             Register rn,
2106             const Operand& operand) {
2107     bics(al, size, rd, rn, operand);
2108   }
2109 
2110   void bkpt(Condition cond, uint32_t imm);
bkpt(uint32_t imm)2111   void bkpt(uint32_t imm) { bkpt(al, imm); }
2112 
2113   void bl(Condition cond, Location* location);
2114   bool bl_info(Condition cond,
2115                Location* location,
2116                const struct ReferenceInfo** info);
bl(Location * location)2117   void bl(Location* location) { bl(al, location); }
2118 
2119   void blx(Condition cond, Location* location);
2120   bool blx_info(Condition cond,
2121                 Location* location,
2122                 const struct ReferenceInfo** info);
blx(Location * location)2123   void blx(Location* location) { blx(al, location); }
2124 
2125   void blx(Condition cond, Register rm);
blx(Register rm)2126   void blx(Register rm) { blx(al, rm); }
2127 
2128   void bx(Condition cond, Register rm);
bx(Register rm)2129   void bx(Register rm) { bx(al, rm); }
2130 
2131   void bxj(Condition cond, Register rm);
bxj(Register rm)2132   void bxj(Register rm) { bxj(al, rm); }
2133 
2134   void cbnz(Register rn, Location* location);
2135   bool cbnz_info(Register rn,
2136                  Location* location,
2137                  const struct ReferenceInfo** info);
2138 
2139   void cbz(Register rn, Location* location);
2140   bool cbz_info(Register rn,
2141                 Location* location,
2142                 const struct ReferenceInfo** info);
2143 
2144   void clrex(Condition cond);
clrex()2145   void clrex() { clrex(al); }
2146 
2147   void clz(Condition cond, Register rd, Register rm);
clz(Register rd,Register rm)2148   void clz(Register rd, Register rm) { clz(al, rd, rm); }
2149 
2150   void cmn(Condition cond,
2151            EncodingSize size,
2152            Register rn,
2153            const Operand& operand);
cmn(Register rn,const Operand & operand)2154   void cmn(Register rn, const Operand& operand) { cmn(al, Best, rn, operand); }
cmn(Condition cond,Register rn,const Operand & operand)2155   void cmn(Condition cond, Register rn, const Operand& operand) {
2156     cmn(cond, Best, rn, operand);
2157   }
cmn(EncodingSize size,Register rn,const Operand & operand)2158   void cmn(EncodingSize size, Register rn, const Operand& operand) {
2159     cmn(al, size, rn, operand);
2160   }
2161 
2162   void cmp(Condition cond,
2163            EncodingSize size,
2164            Register rn,
2165            const Operand& operand);
cmp(Register rn,const Operand & operand)2166   void cmp(Register rn, const Operand& operand) { cmp(al, Best, rn, operand); }
cmp(Condition cond,Register rn,const Operand & operand)2167   void cmp(Condition cond, Register rn, const Operand& operand) {
2168     cmp(cond, Best, rn, operand);
2169   }
cmp(EncodingSize size,Register rn,const Operand & operand)2170   void cmp(EncodingSize size, Register rn, const Operand& operand) {
2171     cmp(al, size, rn, operand);
2172   }
2173 
2174   void crc32b(Condition cond, Register rd, Register rn, Register rm);
crc32b(Register rd,Register rn,Register rm)2175   void crc32b(Register rd, Register rn, Register rm) { crc32b(al, rd, rn, rm); }
2176 
2177   void crc32cb(Condition cond, Register rd, Register rn, Register rm);
crc32cb(Register rd,Register rn,Register rm)2178   void crc32cb(Register rd, Register rn, Register rm) {
2179     crc32cb(al, rd, rn, rm);
2180   }
2181 
2182   void crc32ch(Condition cond, Register rd, Register rn, Register rm);
crc32ch(Register rd,Register rn,Register rm)2183   void crc32ch(Register rd, Register rn, Register rm) {
2184     crc32ch(al, rd, rn, rm);
2185   }
2186 
2187   void crc32cw(Condition cond, Register rd, Register rn, Register rm);
crc32cw(Register rd,Register rn,Register rm)2188   void crc32cw(Register rd, Register rn, Register rm) {
2189     crc32cw(al, rd, rn, rm);
2190   }
2191 
2192   void crc32h(Condition cond, Register rd, Register rn, Register rm);
crc32h(Register rd,Register rn,Register rm)2193   void crc32h(Register rd, Register rn, Register rm) { crc32h(al, rd, rn, rm); }
2194 
2195   void crc32w(Condition cond, Register rd, Register rn, Register rm);
crc32w(Register rd,Register rn,Register rm)2196   void crc32w(Register rd, Register rn, Register rm) { crc32w(al, rd, rn, rm); }
2197 
2198   void dmb(Condition cond, MemoryBarrier option);
dmb(MemoryBarrier option)2199   void dmb(MemoryBarrier option) { dmb(al, option); }
2200 
2201   void dsb(Condition cond, MemoryBarrier option);
dsb(MemoryBarrier option)2202   void dsb(MemoryBarrier option) { dsb(al, option); }
2203 
2204   void eor(Condition cond,
2205            EncodingSize size,
2206            Register rd,
2207            Register rn,
2208            const Operand& operand);
eor(Register rd,Register rn,const Operand & operand)2209   void eor(Register rd, Register rn, const Operand& operand) {
2210     eor(al, Best, rd, rn, operand);
2211   }
eor(Condition cond,Register rd,Register rn,const Operand & operand)2212   void eor(Condition cond, Register rd, Register rn, const Operand& operand) {
2213     eor(cond, Best, rd, rn, operand);
2214   }
eor(EncodingSize size,Register rd,Register rn,const Operand & operand)2215   void eor(EncodingSize size,
2216            Register rd,
2217            Register rn,
2218            const Operand& operand) {
2219     eor(al, size, rd, rn, operand);
2220   }
2221 
2222   void eors(Condition cond,
2223             EncodingSize size,
2224             Register rd,
2225             Register rn,
2226             const Operand& operand);
eors(Register rd,Register rn,const Operand & operand)2227   void eors(Register rd, Register rn, const Operand& operand) {
2228     eors(al, Best, rd, rn, operand);
2229   }
eors(Condition cond,Register rd,Register rn,const Operand & operand)2230   void eors(Condition cond, Register rd, Register rn, const Operand& operand) {
2231     eors(cond, Best, rd, rn, operand);
2232   }
eors(EncodingSize size,Register rd,Register rn,const Operand & operand)2233   void eors(EncodingSize size,
2234             Register rd,
2235             Register rn,
2236             const Operand& operand) {
2237     eors(al, size, rd, rn, operand);
2238   }
2239 
2240   void fldmdbx(Condition cond,
2241                Register rn,
2242                WriteBack write_back,
2243                DRegisterList dreglist);
fldmdbx(Register rn,WriteBack write_back,DRegisterList dreglist)2244   void fldmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) {
2245     fldmdbx(al, rn, write_back, dreglist);
2246   }
2247 
2248   void fldmiax(Condition cond,
2249                Register rn,
2250                WriteBack write_back,
2251                DRegisterList dreglist);
fldmiax(Register rn,WriteBack write_back,DRegisterList dreglist)2252   void fldmiax(Register rn, WriteBack write_back, DRegisterList dreglist) {
2253     fldmiax(al, rn, write_back, dreglist);
2254   }
2255 
2256   void fstmdbx(Condition cond,
2257                Register rn,
2258                WriteBack write_back,
2259                DRegisterList dreglist);
fstmdbx(Register rn,WriteBack write_back,DRegisterList dreglist)2260   void fstmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) {
2261     fstmdbx(al, rn, write_back, dreglist);
2262   }
2263 
2264   void fstmiax(Condition cond,
2265                Register rn,
2266                WriteBack write_back,
2267                DRegisterList dreglist);
fstmiax(Register rn,WriteBack write_back,DRegisterList dreglist)2268   void fstmiax(Register rn, WriteBack write_back, DRegisterList dreglist) {
2269     fstmiax(al, rn, write_back, dreglist);
2270   }
2271 
2272   void hlt(Condition cond, uint32_t imm);
hlt(uint32_t imm)2273   void hlt(uint32_t imm) { hlt(al, imm); }
2274 
2275   void hvc(Condition cond, uint32_t imm);
hvc(uint32_t imm)2276   void hvc(uint32_t imm) { hvc(al, imm); }
2277 
2278   void isb(Condition cond, MemoryBarrier option);
isb(MemoryBarrier option)2279   void isb(MemoryBarrier option) { isb(al, option); }
2280 
2281   void it(Condition cond, uint16_t mask);
2282 
2283   void lda(Condition cond, Register rt, const MemOperand& operand);
lda(Register rt,const MemOperand & operand)2284   void lda(Register rt, const MemOperand& operand) { lda(al, rt, operand); }
2285 
2286   void ldab(Condition cond, Register rt, const MemOperand& operand);
ldab(Register rt,const MemOperand & operand)2287   void ldab(Register rt, const MemOperand& operand) { ldab(al, rt, operand); }
2288 
2289   void ldaex(Condition cond, Register rt, const MemOperand& operand);
ldaex(Register rt,const MemOperand & operand)2290   void ldaex(Register rt, const MemOperand& operand) { ldaex(al, rt, operand); }
2291 
2292   void ldaexb(Condition cond, Register rt, const MemOperand& operand);
ldaexb(Register rt,const MemOperand & operand)2293   void ldaexb(Register rt, const MemOperand& operand) {
2294     ldaexb(al, rt, operand);
2295   }
2296 
2297   void ldaexd(Condition cond,
2298               Register rt,
2299               Register rt2,
2300               const MemOperand& operand);
ldaexd(Register rt,Register rt2,const MemOperand & operand)2301   void ldaexd(Register rt, Register rt2, const MemOperand& operand) {
2302     ldaexd(al, rt, rt2, operand);
2303   }
2304 
2305   void ldaexh(Condition cond, Register rt, const MemOperand& operand);
ldaexh(Register rt,const MemOperand & operand)2306   void ldaexh(Register rt, const MemOperand& operand) {
2307     ldaexh(al, rt, operand);
2308   }
2309 
2310   void ldah(Condition cond, Register rt, const MemOperand& operand);
ldah(Register rt,const MemOperand & operand)2311   void ldah(Register rt, const MemOperand& operand) { ldah(al, rt, operand); }
2312 
2313   void ldm(Condition cond,
2314            EncodingSize size,
2315            Register rn,
2316            WriteBack write_back,
2317            RegisterList registers);
ldm(Register rn,WriteBack write_back,RegisterList registers)2318   void ldm(Register rn, WriteBack write_back, RegisterList registers) {
2319     ldm(al, Best, rn, write_back, registers);
2320   }
ldm(Condition cond,Register rn,WriteBack write_back,RegisterList registers)2321   void ldm(Condition cond,
2322            Register rn,
2323            WriteBack write_back,
2324            RegisterList registers) {
2325     ldm(cond, Best, rn, write_back, registers);
2326   }
ldm(EncodingSize size,Register rn,WriteBack write_back,RegisterList registers)2327   void ldm(EncodingSize size,
2328            Register rn,
2329            WriteBack write_back,
2330            RegisterList registers) {
2331     ldm(al, size, rn, write_back, registers);
2332   }
2333 
2334   void ldmda(Condition cond,
2335              Register rn,
2336              WriteBack write_back,
2337              RegisterList registers);
ldmda(Register rn,WriteBack write_back,RegisterList registers)2338   void ldmda(Register rn, WriteBack write_back, RegisterList registers) {
2339     ldmda(al, rn, write_back, registers);
2340   }
2341 
2342   void ldmdb(Condition cond,
2343              Register rn,
2344              WriteBack write_back,
2345              RegisterList registers);
ldmdb(Register rn,WriteBack write_back,RegisterList registers)2346   void ldmdb(Register rn, WriteBack write_back, RegisterList registers) {
2347     ldmdb(al, rn, write_back, registers);
2348   }
2349 
2350   void ldmea(Condition cond,
2351              Register rn,
2352              WriteBack write_back,
2353              RegisterList registers);
ldmea(Register rn,WriteBack write_back,RegisterList registers)2354   void ldmea(Register rn, WriteBack write_back, RegisterList registers) {
2355     ldmea(al, rn, write_back, registers);
2356   }
2357 
2358   void ldmed(Condition cond,
2359              Register rn,
2360              WriteBack write_back,
2361              RegisterList registers);
ldmed(Register rn,WriteBack write_back,RegisterList registers)2362   void ldmed(Register rn, WriteBack write_back, RegisterList registers) {
2363     ldmed(al, rn, write_back, registers);
2364   }
2365 
2366   void ldmfa(Condition cond,
2367              Register rn,
2368              WriteBack write_back,
2369              RegisterList registers);
ldmfa(Register rn,WriteBack write_back,RegisterList registers)2370   void ldmfa(Register rn, WriteBack write_back, RegisterList registers) {
2371     ldmfa(al, rn, write_back, registers);
2372   }
2373 
2374   void ldmfd(Condition cond,
2375              EncodingSize size,
2376              Register rn,
2377              WriteBack write_back,
2378              RegisterList registers);
ldmfd(Register rn,WriteBack write_back,RegisterList registers)2379   void ldmfd(Register rn, WriteBack write_back, RegisterList registers) {
2380     ldmfd(al, Best, rn, write_back, registers);
2381   }
ldmfd(Condition cond,Register rn,WriteBack write_back,RegisterList registers)2382   void ldmfd(Condition cond,
2383              Register rn,
2384              WriteBack write_back,
2385              RegisterList registers) {
2386     ldmfd(cond, Best, rn, write_back, registers);
2387   }
ldmfd(EncodingSize size,Register rn,WriteBack write_back,RegisterList registers)2388   void ldmfd(EncodingSize size,
2389              Register rn,
2390              WriteBack write_back,
2391              RegisterList registers) {
2392     ldmfd(al, size, rn, write_back, registers);
2393   }
2394 
2395   void ldmib(Condition cond,
2396              Register rn,
2397              WriteBack write_back,
2398              RegisterList registers);
ldmib(Register rn,WriteBack write_back,RegisterList registers)2399   void ldmib(Register rn, WriteBack write_back, RegisterList registers) {
2400     ldmib(al, rn, write_back, registers);
2401   }
2402 
2403   void ldr(Condition cond,
2404            EncodingSize size,
2405            Register rt,
2406            const MemOperand& operand);
ldr(Register rt,const MemOperand & operand)2407   void ldr(Register rt, const MemOperand& operand) {
2408     ldr(al, Best, rt, operand);
2409   }
ldr(Condition cond,Register rt,const MemOperand & operand)2410   void ldr(Condition cond, Register rt, const MemOperand& operand) {
2411     ldr(cond, Best, rt, operand);
2412   }
ldr(EncodingSize size,Register rt,const MemOperand & operand)2413   void ldr(EncodingSize size, Register rt, const MemOperand& operand) {
2414     ldr(al, size, rt, operand);
2415   }
2416 
2417   void ldr(Condition cond, EncodingSize size, Register rt, Location* location);
2418   bool ldr_info(Condition cond,
2419                 EncodingSize size,
2420                 Register rt,
2421                 Location* location,
2422                 const struct ReferenceInfo** info);
ldr(Register rt,Location * location)2423   void ldr(Register rt, Location* location) { ldr(al, Best, rt, location); }
ldr(Condition cond,Register rt,Location * location)2424   void ldr(Condition cond, Register rt, Location* location) {
2425     ldr(cond, Best, rt, location);
2426   }
ldr(EncodingSize size,Register rt,Location * location)2427   void ldr(EncodingSize size, Register rt, Location* location) {
2428     ldr(al, size, rt, location);
2429   }
2430 
2431   void ldrb(Condition cond,
2432             EncodingSize size,
2433             Register rt,
2434             const MemOperand& operand);
ldrb(Register rt,const MemOperand & operand)2435   void ldrb(Register rt, const MemOperand& operand) {
2436     ldrb(al, Best, rt, operand);
2437   }
ldrb(Condition cond,Register rt,const MemOperand & operand)2438   void ldrb(Condition cond, Register rt, const MemOperand& operand) {
2439     ldrb(cond, Best, rt, operand);
2440   }
ldrb(EncodingSize size,Register rt,const MemOperand & operand)2441   void ldrb(EncodingSize size, Register rt, const MemOperand& operand) {
2442     ldrb(al, size, rt, operand);
2443   }
2444 
2445   void ldrb(Condition cond, Register rt, Location* location);
2446   bool ldrb_info(Condition cond,
2447                  Register rt,
2448                  Location* location,
2449                  const struct ReferenceInfo** info);
ldrb(Register rt,Location * location)2450   void ldrb(Register rt, Location* location) { ldrb(al, rt, location); }
2451 
2452   void ldrd(Condition cond,
2453             Register rt,
2454             Register rt2,
2455             const MemOperand& operand);
ldrd(Register rt,Register rt2,const MemOperand & operand)2456   void ldrd(Register rt, Register rt2, const MemOperand& operand) {
2457     ldrd(al, rt, rt2, operand);
2458   }
2459 
2460   void ldrd(Condition cond, Register rt, Register rt2, Location* location);
2461   bool ldrd_info(Condition cond,
2462                  Register rt,
2463                  Register rt2,
2464                  Location* location,
2465                  const struct ReferenceInfo** info);
ldrd(Register rt,Register rt2,Location * location)2466   void ldrd(Register rt, Register rt2, Location* location) {
2467     ldrd(al, rt, rt2, location);
2468   }
2469 
2470   void ldrex(Condition cond, Register rt, const MemOperand& operand);
ldrex(Register rt,const MemOperand & operand)2471   void ldrex(Register rt, const MemOperand& operand) { ldrex(al, rt, operand); }
2472 
2473   void ldrexb(Condition cond, Register rt, const MemOperand& operand);
ldrexb(Register rt,const MemOperand & operand)2474   void ldrexb(Register rt, const MemOperand& operand) {
2475     ldrexb(al, rt, operand);
2476   }
2477 
2478   void ldrexd(Condition cond,
2479               Register rt,
2480               Register rt2,
2481               const MemOperand& operand);
ldrexd(Register rt,Register rt2,const MemOperand & operand)2482   void ldrexd(Register rt, Register rt2, const MemOperand& operand) {
2483     ldrexd(al, rt, rt2, operand);
2484   }
2485 
2486   void ldrexh(Condition cond, Register rt, const MemOperand& operand);
ldrexh(Register rt,const MemOperand & operand)2487   void ldrexh(Register rt, const MemOperand& operand) {
2488     ldrexh(al, rt, operand);
2489   }
2490 
2491   void ldrh(Condition cond,
2492             EncodingSize size,
2493             Register rt,
2494             const MemOperand& operand);
ldrh(Register rt,const MemOperand & operand)2495   void ldrh(Register rt, const MemOperand& operand) {
2496     ldrh(al, Best, rt, operand);
2497   }
ldrh(Condition cond,Register rt,const MemOperand & operand)2498   void ldrh(Condition cond, Register rt, const MemOperand& operand) {
2499     ldrh(cond, Best, rt, operand);
2500   }
ldrh(EncodingSize size,Register rt,const MemOperand & operand)2501   void ldrh(EncodingSize size, Register rt, const MemOperand& operand) {
2502     ldrh(al, size, rt, operand);
2503   }
2504 
2505   void ldrh(Condition cond, Register rt, Location* location);
2506   bool ldrh_info(Condition cond,
2507                  Register rt,
2508                  Location* location,
2509                  const struct ReferenceInfo** info);
ldrh(Register rt,Location * location)2510   void ldrh(Register rt, Location* location) { ldrh(al, rt, location); }
2511 
2512   void ldrsb(Condition cond,
2513              EncodingSize size,
2514              Register rt,
2515              const MemOperand& operand);
ldrsb(Register rt,const MemOperand & operand)2516   void ldrsb(Register rt, const MemOperand& operand) {
2517     ldrsb(al, Best, rt, operand);
2518   }
ldrsb(Condition cond,Register rt,const MemOperand & operand)2519   void ldrsb(Condition cond, Register rt, const MemOperand& operand) {
2520     ldrsb(cond, Best, rt, operand);
2521   }
ldrsb(EncodingSize size,Register rt,const MemOperand & operand)2522   void ldrsb(EncodingSize size, Register rt, const MemOperand& operand) {
2523     ldrsb(al, size, rt, operand);
2524   }
2525 
2526   void ldrsb(Condition cond, Register rt, Location* location);
2527   bool ldrsb_info(Condition cond,
2528                   Register rt,
2529                   Location* location,
2530                   const struct ReferenceInfo** info);
ldrsb(Register rt,Location * location)2531   void ldrsb(Register rt, Location* location) { ldrsb(al, rt, location); }
2532 
2533   void ldrsh(Condition cond,
2534              EncodingSize size,
2535              Register rt,
2536              const MemOperand& operand);
ldrsh(Register rt,const MemOperand & operand)2537   void ldrsh(Register rt, const MemOperand& operand) {
2538     ldrsh(al, Best, rt, operand);
2539   }
ldrsh(Condition cond,Register rt,const MemOperand & operand)2540   void ldrsh(Condition cond, Register rt, const MemOperand& operand) {
2541     ldrsh(cond, Best, rt, operand);
2542   }
ldrsh(EncodingSize size,Register rt,const MemOperand & operand)2543   void ldrsh(EncodingSize size, Register rt, const MemOperand& operand) {
2544     ldrsh(al, size, rt, operand);
2545   }
2546 
2547   void ldrsh(Condition cond, Register rt, Location* location);
2548   bool ldrsh_info(Condition cond,
2549                   Register rt,
2550                   Location* location,
2551                   const struct ReferenceInfo** info);
ldrsh(Register rt,Location * location)2552   void ldrsh(Register rt, Location* location) { ldrsh(al, rt, location); }
2553 
2554   void lsl(Condition cond,
2555            EncodingSize size,
2556            Register rd,
2557            Register rm,
2558            const Operand& operand);
lsl(Register rd,Register rm,const Operand & operand)2559   void lsl(Register rd, Register rm, const Operand& operand) {
2560     lsl(al, Best, rd, rm, operand);
2561   }
lsl(Condition cond,Register rd,Register rm,const Operand & operand)2562   void lsl(Condition cond, Register rd, Register rm, const Operand& operand) {
2563     lsl(cond, Best, rd, rm, operand);
2564   }
lsl(EncodingSize size,Register rd,Register rm,const Operand & operand)2565   void lsl(EncodingSize size,
2566            Register rd,
2567            Register rm,
2568            const Operand& operand) {
2569     lsl(al, size, rd, rm, operand);
2570   }
2571 
2572   void lsls(Condition cond,
2573             EncodingSize size,
2574             Register rd,
2575             Register rm,
2576             const Operand& operand);
lsls(Register rd,Register rm,const Operand & operand)2577   void lsls(Register rd, Register rm, const Operand& operand) {
2578     lsls(al, Best, rd, rm, operand);
2579   }
lsls(Condition cond,Register rd,Register rm,const Operand & operand)2580   void lsls(Condition cond, Register rd, Register rm, const Operand& operand) {
2581     lsls(cond, Best, rd, rm, operand);
2582   }
lsls(EncodingSize size,Register rd,Register rm,const Operand & operand)2583   void lsls(EncodingSize size,
2584             Register rd,
2585             Register rm,
2586             const Operand& operand) {
2587     lsls(al, size, rd, rm, operand);
2588   }
2589 
2590   void lsr(Condition cond,
2591            EncodingSize size,
2592            Register rd,
2593            Register rm,
2594            const Operand& operand);
lsr(Register rd,Register rm,const Operand & operand)2595   void lsr(Register rd, Register rm, const Operand& operand) {
2596     lsr(al, Best, rd, rm, operand);
2597   }
lsr(Condition cond,Register rd,Register rm,const Operand & operand)2598   void lsr(Condition cond, Register rd, Register rm, const Operand& operand) {
2599     lsr(cond, Best, rd, rm, operand);
2600   }
lsr(EncodingSize size,Register rd,Register rm,const Operand & operand)2601   void lsr(EncodingSize size,
2602            Register rd,
2603            Register rm,
2604            const Operand& operand) {
2605     lsr(al, size, rd, rm, operand);
2606   }
2607 
2608   void lsrs(Condition cond,
2609             EncodingSize size,
2610             Register rd,
2611             Register rm,
2612             const Operand& operand);
lsrs(Register rd,Register rm,const Operand & operand)2613   void lsrs(Register rd, Register rm, const Operand& operand) {
2614     lsrs(al, Best, rd, rm, operand);
2615   }
lsrs(Condition cond,Register rd,Register rm,const Operand & operand)2616   void lsrs(Condition cond, Register rd, Register rm, const Operand& operand) {
2617     lsrs(cond, Best, rd, rm, operand);
2618   }
lsrs(EncodingSize size,Register rd,Register rm,const Operand & operand)2619   void lsrs(EncodingSize size,
2620             Register rd,
2621             Register rm,
2622             const Operand& operand) {
2623     lsrs(al, size, rd, rm, operand);
2624   }
2625 
2626   void mla(Condition cond, Register rd, Register rn, Register rm, Register ra);
mla(Register rd,Register rn,Register rm,Register ra)2627   void mla(Register rd, Register rn, Register rm, Register ra) {
2628     mla(al, rd, rn, rm, ra);
2629   }
2630 
2631   void mlas(Condition cond, Register rd, Register rn, Register rm, Register ra);
mlas(Register rd,Register rn,Register rm,Register ra)2632   void mlas(Register rd, Register rn, Register rm, Register ra) {
2633     mlas(al, rd, rn, rm, ra);
2634   }
2635 
2636   void mls(Condition cond, Register rd, Register rn, Register rm, Register ra);
mls(Register rd,Register rn,Register rm,Register ra)2637   void mls(Register rd, Register rn, Register rm, Register ra) {
2638     mls(al, rd, rn, rm, ra);
2639   }
2640 
2641   void mov(Condition cond,
2642            EncodingSize size,
2643            Register rd,
2644            const Operand& operand);
mov(Register rd,const Operand & operand)2645   void mov(Register rd, const Operand& operand) { mov(al, Best, rd, operand); }
mov(Condition cond,Register rd,const Operand & operand)2646   void mov(Condition cond, Register rd, const Operand& operand) {
2647     mov(cond, Best, rd, operand);
2648   }
mov(EncodingSize size,Register rd,const Operand & operand)2649   void mov(EncodingSize size, Register rd, const Operand& operand) {
2650     mov(al, size, rd, operand);
2651   }
2652 
2653   void movs(Condition cond,
2654             EncodingSize size,
2655             Register rd,
2656             const Operand& operand);
movs(Register rd,const Operand & operand)2657   void movs(Register rd, const Operand& operand) {
2658     movs(al, Best, rd, operand);
2659   }
movs(Condition cond,Register rd,const Operand & operand)2660   void movs(Condition cond, Register rd, const Operand& operand) {
2661     movs(cond, Best, rd, operand);
2662   }
movs(EncodingSize size,Register rd,const Operand & operand)2663   void movs(EncodingSize size, Register rd, const Operand& operand) {
2664     movs(al, size, rd, operand);
2665   }
2666 
2667   void movt(Condition cond, Register rd, const Operand& operand);
movt(Register rd,const Operand & operand)2668   void movt(Register rd, const Operand& operand) { movt(al, rd, operand); }
2669 
2670   void movw(Condition cond, Register rd, const Operand& operand);
movw(Register rd,const Operand & operand)2671   void movw(Register rd, const Operand& operand) { movw(al, rd, operand); }
2672 
2673   void mrs(Condition cond, Register rd, SpecialRegister spec_reg);
mrs(Register rd,SpecialRegister spec_reg)2674   void mrs(Register rd, SpecialRegister spec_reg) { mrs(al, rd, spec_reg); }
2675 
2676   void msr(Condition cond,
2677            MaskedSpecialRegister spec_reg,
2678            const Operand& operand);
msr(MaskedSpecialRegister spec_reg,const Operand & operand)2679   void msr(MaskedSpecialRegister spec_reg, const Operand& operand) {
2680     msr(al, spec_reg, operand);
2681   }
2682 
2683   void mul(
2684       Condition cond, EncodingSize size, Register rd, Register rn, Register rm);
mul(Register rd,Register rn,Register rm)2685   void mul(Register rd, Register rn, Register rm) { mul(al, Best, rd, rn, rm); }
mul(Condition cond,Register rd,Register rn,Register rm)2686   void mul(Condition cond, Register rd, Register rn, Register rm) {
2687     mul(cond, Best, rd, rn, rm);
2688   }
mul(EncodingSize size,Register rd,Register rn,Register rm)2689   void mul(EncodingSize size, Register rd, Register rn, Register rm) {
2690     mul(al, size, rd, rn, rm);
2691   }
2692 
2693   void muls(Condition cond, Register rd, Register rn, Register rm);
muls(Register rd,Register rn,Register rm)2694   void muls(Register rd, Register rn, Register rm) { muls(al, rd, rn, rm); }
2695 
2696   void mvn(Condition cond,
2697            EncodingSize size,
2698            Register rd,
2699            const Operand& operand);
mvn(Register rd,const Operand & operand)2700   void mvn(Register rd, const Operand& operand) { mvn(al, Best, rd, operand); }
mvn(Condition cond,Register rd,const Operand & operand)2701   void mvn(Condition cond, Register rd, const Operand& operand) {
2702     mvn(cond, Best, rd, operand);
2703   }
mvn(EncodingSize size,Register rd,const Operand & operand)2704   void mvn(EncodingSize size, Register rd, const Operand& operand) {
2705     mvn(al, size, rd, operand);
2706   }
2707 
2708   void mvns(Condition cond,
2709             EncodingSize size,
2710             Register rd,
2711             const Operand& operand);
mvns(Register rd,const Operand & operand)2712   void mvns(Register rd, const Operand& operand) {
2713     mvns(al, Best, rd, operand);
2714   }
mvns(Condition cond,Register rd,const Operand & operand)2715   void mvns(Condition cond, Register rd, const Operand& operand) {
2716     mvns(cond, Best, rd, operand);
2717   }
mvns(EncodingSize size,Register rd,const Operand & operand)2718   void mvns(EncodingSize size, Register rd, const Operand& operand) {
2719     mvns(al, size, rd, operand);
2720   }
2721 
2722   void nop(Condition cond, EncodingSize size);
nop()2723   void nop() { nop(al, Best); }
nop(Condition cond)2724   void nop(Condition cond) { nop(cond, Best); }
nop(EncodingSize size)2725   void nop(EncodingSize size) { nop(al, size); }
2726 
2727   void orn(Condition cond, Register rd, Register rn, const Operand& operand);
orn(Register rd,Register rn,const Operand & operand)2728   void orn(Register rd, Register rn, const Operand& operand) {
2729     orn(al, rd, rn, operand);
2730   }
2731 
2732   void orns(Condition cond, Register rd, Register rn, const Operand& operand);
orns(Register rd,Register rn,const Operand & operand)2733   void orns(Register rd, Register rn, const Operand& operand) {
2734     orns(al, rd, rn, operand);
2735   }
2736 
2737   void orr(Condition cond,
2738            EncodingSize size,
2739            Register rd,
2740            Register rn,
2741            const Operand& operand);
orr(Register rd,Register rn,const Operand & operand)2742   void orr(Register rd, Register rn, const Operand& operand) {
2743     orr(al, Best, rd, rn, operand);
2744   }
orr(Condition cond,Register rd,Register rn,const Operand & operand)2745   void orr(Condition cond, Register rd, Register rn, const Operand& operand) {
2746     orr(cond, Best, rd, rn, operand);
2747   }
orr(EncodingSize size,Register rd,Register rn,const Operand & operand)2748   void orr(EncodingSize size,
2749            Register rd,
2750            Register rn,
2751            const Operand& operand) {
2752     orr(al, size, rd, rn, operand);
2753   }
2754 
2755   void orrs(Condition cond,
2756             EncodingSize size,
2757             Register rd,
2758             Register rn,
2759             const Operand& operand);
orrs(Register rd,Register rn,const Operand & operand)2760   void orrs(Register rd, Register rn, const Operand& operand) {
2761     orrs(al, Best, rd, rn, operand);
2762   }
orrs(Condition cond,Register rd,Register rn,const Operand & operand)2763   void orrs(Condition cond, Register rd, Register rn, const Operand& operand) {
2764     orrs(cond, Best, rd, rn, operand);
2765   }
orrs(EncodingSize size,Register rd,Register rn,const Operand & operand)2766   void orrs(EncodingSize size,
2767             Register rd,
2768             Register rn,
2769             const Operand& operand) {
2770     orrs(al, size, rd, rn, operand);
2771   }
2772 
2773   void pkhbt(Condition cond, Register rd, Register rn, const Operand& operand);
pkhbt(Register rd,Register rn,const Operand & operand)2774   void pkhbt(Register rd, Register rn, const Operand& operand) {
2775     pkhbt(al, rd, rn, operand);
2776   }
2777 
2778   void pkhtb(Condition cond, Register rd, Register rn, const Operand& operand);
pkhtb(Register rd,Register rn,const Operand & operand)2779   void pkhtb(Register rd, Register rn, const Operand& operand) {
2780     pkhtb(al, rd, rn, operand);
2781   }
2782 
2783   void pld(Condition cond, Location* location);
2784   bool pld_info(Condition cond,
2785                 Location* location,
2786                 const struct ReferenceInfo** info);
pld(Location * location)2787   void pld(Location* location) { pld(al, location); }
2788 
2789   void pld(Condition cond, const MemOperand& operand);
pld(const MemOperand & operand)2790   void pld(const MemOperand& operand) { pld(al, operand); }
2791 
2792   void pldw(Condition cond, const MemOperand& operand);
pldw(const MemOperand & operand)2793   void pldw(const MemOperand& operand) { pldw(al, operand); }
2794 
2795   void pli(Condition cond, const MemOperand& operand);
pli(const MemOperand & operand)2796   void pli(const MemOperand& operand) { pli(al, operand); }
2797 
2798   void pli(Condition cond, Location* location);
2799   bool pli_info(Condition cond,
2800                 Location* location,
2801                 const struct ReferenceInfo** info);
pli(Location * location)2802   void pli(Location* location) { pli(al, location); }
2803 
2804   void pop(Condition cond, EncodingSize size, RegisterList registers);
pop(RegisterList registers)2805   void pop(RegisterList registers) { pop(al, Best, registers); }
pop(Condition cond,RegisterList registers)2806   void pop(Condition cond, RegisterList registers) {
2807     pop(cond, Best, registers);
2808   }
pop(EncodingSize size,RegisterList registers)2809   void pop(EncodingSize size, RegisterList registers) {
2810     pop(al, size, registers);
2811   }
2812 
2813   void pop(Condition cond, EncodingSize size, Register rt);
pop(Register rt)2814   void pop(Register rt) { pop(al, Best, rt); }
pop(Condition cond,Register rt)2815   void pop(Condition cond, Register rt) { pop(cond, Best, rt); }
pop(EncodingSize size,Register rt)2816   void pop(EncodingSize size, Register rt) { pop(al, size, rt); }
2817 
2818   void push(Condition cond, EncodingSize size, RegisterList registers);
push(RegisterList registers)2819   void push(RegisterList registers) { push(al, Best, registers); }
push(Condition cond,RegisterList registers)2820   void push(Condition cond, RegisterList registers) {
2821     push(cond, Best, registers);
2822   }
push(EncodingSize size,RegisterList registers)2823   void push(EncodingSize size, RegisterList registers) {
2824     push(al, size, registers);
2825   }
2826 
2827   void push(Condition cond, EncodingSize size, Register rt);
push(Register rt)2828   void push(Register rt) { push(al, Best, rt); }
push(Condition cond,Register rt)2829   void push(Condition cond, Register rt) { push(cond, Best, rt); }
push(EncodingSize size,Register rt)2830   void push(EncodingSize size, Register rt) { push(al, size, rt); }
2831 
2832   void qadd(Condition cond, Register rd, Register rm, Register rn);
qadd(Register rd,Register rm,Register rn)2833   void qadd(Register rd, Register rm, Register rn) { qadd(al, rd, rm, rn); }
2834 
2835   void qadd16(Condition cond, Register rd, Register rn, Register rm);
qadd16(Register rd,Register rn,Register rm)2836   void qadd16(Register rd, Register rn, Register rm) { qadd16(al, rd, rn, rm); }
2837 
2838   void qadd8(Condition cond, Register rd, Register rn, Register rm);
qadd8(Register rd,Register rn,Register rm)2839   void qadd8(Register rd, Register rn, Register rm) { qadd8(al, rd, rn, rm); }
2840 
2841   void qasx(Condition cond, Register rd, Register rn, Register rm);
qasx(Register rd,Register rn,Register rm)2842   void qasx(Register rd, Register rn, Register rm) { qasx(al, rd, rn, rm); }
2843 
2844   void qdadd(Condition cond, Register rd, Register rm, Register rn);
qdadd(Register rd,Register rm,Register rn)2845   void qdadd(Register rd, Register rm, Register rn) { qdadd(al, rd, rm, rn); }
2846 
2847   void qdsub(Condition cond, Register rd, Register rm, Register rn);
qdsub(Register rd,Register rm,Register rn)2848   void qdsub(Register rd, Register rm, Register rn) { qdsub(al, rd, rm, rn); }
2849 
2850   void qsax(Condition cond, Register rd, Register rn, Register rm);
qsax(Register rd,Register rn,Register rm)2851   void qsax(Register rd, Register rn, Register rm) { qsax(al, rd, rn, rm); }
2852 
2853   void qsub(Condition cond, Register rd, Register rm, Register rn);
qsub(Register rd,Register rm,Register rn)2854   void qsub(Register rd, Register rm, Register rn) { qsub(al, rd, rm, rn); }
2855 
2856   void qsub16(Condition cond, Register rd, Register rn, Register rm);
qsub16(Register rd,Register rn,Register rm)2857   void qsub16(Register rd, Register rn, Register rm) { qsub16(al, rd, rn, rm); }
2858 
2859   void qsub8(Condition cond, Register rd, Register rn, Register rm);
qsub8(Register rd,Register rn,Register rm)2860   void qsub8(Register rd, Register rn, Register rm) { qsub8(al, rd, rn, rm); }
2861 
2862   void rbit(Condition cond, Register rd, Register rm);
rbit(Register rd,Register rm)2863   void rbit(Register rd, Register rm) { rbit(al, rd, rm); }
2864 
2865   void rev(Condition cond, EncodingSize size, Register rd, Register rm);
rev(Register rd,Register rm)2866   void rev(Register rd, Register rm) { rev(al, Best, rd, rm); }
rev(Condition cond,Register rd,Register rm)2867   void rev(Condition cond, Register rd, Register rm) {
2868     rev(cond, Best, rd, rm);
2869   }
rev(EncodingSize size,Register rd,Register rm)2870   void rev(EncodingSize size, Register rd, Register rm) {
2871     rev(al, size, rd, rm);
2872   }
2873 
2874   void rev16(Condition cond, EncodingSize size, Register rd, Register rm);
rev16(Register rd,Register rm)2875   void rev16(Register rd, Register rm) { rev16(al, Best, rd, rm); }
rev16(Condition cond,Register rd,Register rm)2876   void rev16(Condition cond, Register rd, Register rm) {
2877     rev16(cond, Best, rd, rm);
2878   }
rev16(EncodingSize size,Register rd,Register rm)2879   void rev16(EncodingSize size, Register rd, Register rm) {
2880     rev16(al, size, rd, rm);
2881   }
2882 
2883   void revsh(Condition cond, EncodingSize size, Register rd, Register rm);
revsh(Register rd,Register rm)2884   void revsh(Register rd, Register rm) { revsh(al, Best, rd, rm); }
revsh(Condition cond,Register rd,Register rm)2885   void revsh(Condition cond, Register rd, Register rm) {
2886     revsh(cond, Best, rd, rm);
2887   }
revsh(EncodingSize size,Register rd,Register rm)2888   void revsh(EncodingSize size, Register rd, Register rm) {
2889     revsh(al, size, rd, rm);
2890   }
2891 
2892   void ror(Condition cond,
2893            EncodingSize size,
2894            Register rd,
2895            Register rm,
2896            const Operand& operand);
ror(Register rd,Register rm,const Operand & operand)2897   void ror(Register rd, Register rm, const Operand& operand) {
2898     ror(al, Best, rd, rm, operand);
2899   }
ror(Condition cond,Register rd,Register rm,const Operand & operand)2900   void ror(Condition cond, Register rd, Register rm, const Operand& operand) {
2901     ror(cond, Best, rd, rm, operand);
2902   }
ror(EncodingSize size,Register rd,Register rm,const Operand & operand)2903   void ror(EncodingSize size,
2904            Register rd,
2905            Register rm,
2906            const Operand& operand) {
2907     ror(al, size, rd, rm, operand);
2908   }
2909 
2910   void rors(Condition cond,
2911             EncodingSize size,
2912             Register rd,
2913             Register rm,
2914             const Operand& operand);
rors(Register rd,Register rm,const Operand & operand)2915   void rors(Register rd, Register rm, const Operand& operand) {
2916     rors(al, Best, rd, rm, operand);
2917   }
rors(Condition cond,Register rd,Register rm,const Operand & operand)2918   void rors(Condition cond, Register rd, Register rm, const Operand& operand) {
2919     rors(cond, Best, rd, rm, operand);
2920   }
rors(EncodingSize size,Register rd,Register rm,const Operand & operand)2921   void rors(EncodingSize size,
2922             Register rd,
2923             Register rm,
2924             const Operand& operand) {
2925     rors(al, size, rd, rm, operand);
2926   }
2927 
2928   void rrx(Condition cond, Register rd, Register rm);
rrx(Register rd,Register rm)2929   void rrx(Register rd, Register rm) { rrx(al, rd, rm); }
2930 
2931   void rrxs(Condition cond, Register rd, Register rm);
rrxs(Register rd,Register rm)2932   void rrxs(Register rd, Register rm) { rrxs(al, rd, rm); }
2933 
2934   void rsb(Condition cond,
2935            EncodingSize size,
2936            Register rd,
2937            Register rn,
2938            const Operand& operand);
rsb(Register rd,Register rn,const Operand & operand)2939   void rsb(Register rd, Register rn, const Operand& operand) {
2940     rsb(al, Best, rd, rn, operand);
2941   }
rsb(Condition cond,Register rd,Register rn,const Operand & operand)2942   void rsb(Condition cond, Register rd, Register rn, const Operand& operand) {
2943     rsb(cond, Best, rd, rn, operand);
2944   }
rsb(EncodingSize size,Register rd,Register rn,const Operand & operand)2945   void rsb(EncodingSize size,
2946            Register rd,
2947            Register rn,
2948            const Operand& operand) {
2949     rsb(al, size, rd, rn, operand);
2950   }
2951 
2952   void rsbs(Condition cond,
2953             EncodingSize size,
2954             Register rd,
2955             Register rn,
2956             const Operand& operand);
rsbs(Register rd,Register rn,const Operand & operand)2957   void rsbs(Register rd, Register rn, const Operand& operand) {
2958     rsbs(al, Best, rd, rn, operand);
2959   }
rsbs(Condition cond,Register rd,Register rn,const Operand & operand)2960   void rsbs(Condition cond, Register rd, Register rn, const Operand& operand) {
2961     rsbs(cond, Best, rd, rn, operand);
2962   }
rsbs(EncodingSize size,Register rd,Register rn,const Operand & operand)2963   void rsbs(EncodingSize size,
2964             Register rd,
2965             Register rn,
2966             const Operand& operand) {
2967     rsbs(al, size, rd, rn, operand);
2968   }
2969 
2970   void rsc(Condition cond, Register rd, Register rn, const Operand& operand);
rsc(Register rd,Register rn,const Operand & operand)2971   void rsc(Register rd, Register rn, const Operand& operand) {
2972     rsc(al, rd, rn, operand);
2973   }
2974 
2975   void rscs(Condition cond, Register rd, Register rn, const Operand& operand);
rscs(Register rd,Register rn,const Operand & operand)2976   void rscs(Register rd, Register rn, const Operand& operand) {
2977     rscs(al, rd, rn, operand);
2978   }
2979 
2980   void sadd16(Condition cond, Register rd, Register rn, Register rm);
sadd16(Register rd,Register rn,Register rm)2981   void sadd16(Register rd, Register rn, Register rm) { sadd16(al, rd, rn, rm); }
2982 
2983   void sadd8(Condition cond, Register rd, Register rn, Register rm);
sadd8(Register rd,Register rn,Register rm)2984   void sadd8(Register rd, Register rn, Register rm) { sadd8(al, rd, rn, rm); }
2985 
2986   void sasx(Condition cond, Register rd, Register rn, Register rm);
sasx(Register rd,Register rn,Register rm)2987   void sasx(Register rd, Register rn, Register rm) { sasx(al, rd, rn, rm); }
2988 
2989   void sbc(Condition cond,
2990            EncodingSize size,
2991            Register rd,
2992            Register rn,
2993            const Operand& operand);
sbc(Register rd,Register rn,const Operand & operand)2994   void sbc(Register rd, Register rn, const Operand& operand) {
2995     sbc(al, Best, rd, rn, operand);
2996   }
sbc(Condition cond,Register rd,Register rn,const Operand & operand)2997   void sbc(Condition cond, Register rd, Register rn, const Operand& operand) {
2998     sbc(cond, Best, rd, rn, operand);
2999   }
sbc(EncodingSize size,Register rd,Register rn,const Operand & operand)3000   void sbc(EncodingSize size,
3001            Register rd,
3002            Register rn,
3003            const Operand& operand) {
3004     sbc(al, size, rd, rn, operand);
3005   }
3006 
3007   void sbcs(Condition cond,
3008             EncodingSize size,
3009             Register rd,
3010             Register rn,
3011             const Operand& operand);
sbcs(Register rd,Register rn,const Operand & operand)3012   void sbcs(Register rd, Register rn, const Operand& operand) {
3013     sbcs(al, Best, rd, rn, operand);
3014   }
sbcs(Condition cond,Register rd,Register rn,const Operand & operand)3015   void sbcs(Condition cond, Register rd, Register rn, const Operand& operand) {
3016     sbcs(cond, Best, rd, rn, operand);
3017   }
sbcs(EncodingSize size,Register rd,Register rn,const Operand & operand)3018   void sbcs(EncodingSize size,
3019             Register rd,
3020             Register rn,
3021             const Operand& operand) {
3022     sbcs(al, size, rd, rn, operand);
3023   }
3024 
3025   void sbfx(
3026       Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
sbfx(Register rd,Register rn,uint32_t lsb,uint32_t width)3027   void sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width) {
3028     sbfx(al, rd, rn, lsb, width);
3029   }
3030 
3031   void sdiv(Condition cond, Register rd, Register rn, Register rm);
sdiv(Register rd,Register rn,Register rm)3032   void sdiv(Register rd, Register rn, Register rm) { sdiv(al, rd, rn, rm); }
3033 
3034   void sel(Condition cond, Register rd, Register rn, Register rm);
sel(Register rd,Register rn,Register rm)3035   void sel(Register rd, Register rn, Register rm) { sel(al, rd, rn, rm); }
3036 
3037   void shadd16(Condition cond, Register rd, Register rn, Register rm);
shadd16(Register rd,Register rn,Register rm)3038   void shadd16(Register rd, Register rn, Register rm) {
3039     shadd16(al, rd, rn, rm);
3040   }
3041 
3042   void shadd8(Condition cond, Register rd, Register rn, Register rm);
shadd8(Register rd,Register rn,Register rm)3043   void shadd8(Register rd, Register rn, Register rm) { shadd8(al, rd, rn, rm); }
3044 
3045   void shasx(Condition cond, Register rd, Register rn, Register rm);
shasx(Register rd,Register rn,Register rm)3046   void shasx(Register rd, Register rn, Register rm) { shasx(al, rd, rn, rm); }
3047 
3048   void shsax(Condition cond, Register rd, Register rn, Register rm);
shsax(Register rd,Register rn,Register rm)3049   void shsax(Register rd, Register rn, Register rm) { shsax(al, rd, rn, rm); }
3050 
3051   void shsub16(Condition cond, Register rd, Register rn, Register rm);
shsub16(Register rd,Register rn,Register rm)3052   void shsub16(Register rd, Register rn, Register rm) {
3053     shsub16(al, rd, rn, rm);
3054   }
3055 
3056   void shsub8(Condition cond, Register rd, Register rn, Register rm);
shsub8(Register rd,Register rn,Register rm)3057   void shsub8(Register rd, Register rn, Register rm) { shsub8(al, rd, rn, rm); }
3058 
3059   void smlabb(
3060       Condition cond, Register rd, Register rn, Register rm, Register ra);
smlabb(Register rd,Register rn,Register rm,Register ra)3061   void smlabb(Register rd, Register rn, Register rm, Register ra) {
3062     smlabb(al, rd, rn, rm, ra);
3063   }
3064 
3065   void smlabt(
3066       Condition cond, Register rd, Register rn, Register rm, Register ra);
smlabt(Register rd,Register rn,Register rm,Register ra)3067   void smlabt(Register rd, Register rn, Register rm, Register ra) {
3068     smlabt(al, rd, rn, rm, ra);
3069   }
3070 
3071   void smlad(
3072       Condition cond, Register rd, Register rn, Register rm, Register ra);
smlad(Register rd,Register rn,Register rm,Register ra)3073   void smlad(Register rd, Register rn, Register rm, Register ra) {
3074     smlad(al, rd, rn, rm, ra);
3075   }
3076 
3077   void smladx(
3078       Condition cond, Register rd, Register rn, Register rm, Register ra);
smladx(Register rd,Register rn,Register rm,Register ra)3079   void smladx(Register rd, Register rn, Register rm, Register ra) {
3080     smladx(al, rd, rn, rm, ra);
3081   }
3082 
3083   void smlal(
3084       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smlal(Register rdlo,Register rdhi,Register rn,Register rm)3085   void smlal(Register rdlo, Register rdhi, Register rn, Register rm) {
3086     smlal(al, rdlo, rdhi, rn, rm);
3087   }
3088 
3089   void smlalbb(
3090       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smlalbb(Register rdlo,Register rdhi,Register rn,Register rm)3091   void smlalbb(Register rdlo, Register rdhi, Register rn, Register rm) {
3092     smlalbb(al, rdlo, rdhi, rn, rm);
3093   }
3094 
3095   void smlalbt(
3096       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smlalbt(Register rdlo,Register rdhi,Register rn,Register rm)3097   void smlalbt(Register rdlo, Register rdhi, Register rn, Register rm) {
3098     smlalbt(al, rdlo, rdhi, rn, rm);
3099   }
3100 
3101   void smlald(
3102       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smlald(Register rdlo,Register rdhi,Register rn,Register rm)3103   void smlald(Register rdlo, Register rdhi, Register rn, Register rm) {
3104     smlald(al, rdlo, rdhi, rn, rm);
3105   }
3106 
3107   void smlaldx(
3108       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smlaldx(Register rdlo,Register rdhi,Register rn,Register rm)3109   void smlaldx(Register rdlo, Register rdhi, Register rn, Register rm) {
3110     smlaldx(al, rdlo, rdhi, rn, rm);
3111   }
3112 
3113   void smlals(
3114       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smlals(Register rdlo,Register rdhi,Register rn,Register rm)3115   void smlals(Register rdlo, Register rdhi, Register rn, Register rm) {
3116     smlals(al, rdlo, rdhi, rn, rm);
3117   }
3118 
3119   void smlaltb(
3120       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smlaltb(Register rdlo,Register rdhi,Register rn,Register rm)3121   void smlaltb(Register rdlo, Register rdhi, Register rn, Register rm) {
3122     smlaltb(al, rdlo, rdhi, rn, rm);
3123   }
3124 
3125   void smlaltt(
3126       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smlaltt(Register rdlo,Register rdhi,Register rn,Register rm)3127   void smlaltt(Register rdlo, Register rdhi, Register rn, Register rm) {
3128     smlaltt(al, rdlo, rdhi, rn, rm);
3129   }
3130 
3131   void smlatb(
3132       Condition cond, Register rd, Register rn, Register rm, Register ra);
smlatb(Register rd,Register rn,Register rm,Register ra)3133   void smlatb(Register rd, Register rn, Register rm, Register ra) {
3134     smlatb(al, rd, rn, rm, ra);
3135   }
3136 
3137   void smlatt(
3138       Condition cond, Register rd, Register rn, Register rm, Register ra);
smlatt(Register rd,Register rn,Register rm,Register ra)3139   void smlatt(Register rd, Register rn, Register rm, Register ra) {
3140     smlatt(al, rd, rn, rm, ra);
3141   }
3142 
3143   void smlawb(
3144       Condition cond, Register rd, Register rn, Register rm, Register ra);
smlawb(Register rd,Register rn,Register rm,Register ra)3145   void smlawb(Register rd, Register rn, Register rm, Register ra) {
3146     smlawb(al, rd, rn, rm, ra);
3147   }
3148 
3149   void smlawt(
3150       Condition cond, Register rd, Register rn, Register rm, Register ra);
smlawt(Register rd,Register rn,Register rm,Register ra)3151   void smlawt(Register rd, Register rn, Register rm, Register ra) {
3152     smlawt(al, rd, rn, rm, ra);
3153   }
3154 
3155   void smlsd(
3156       Condition cond, Register rd, Register rn, Register rm, Register ra);
smlsd(Register rd,Register rn,Register rm,Register ra)3157   void smlsd(Register rd, Register rn, Register rm, Register ra) {
3158     smlsd(al, rd, rn, rm, ra);
3159   }
3160 
3161   void smlsdx(
3162       Condition cond, Register rd, Register rn, Register rm, Register ra);
smlsdx(Register rd,Register rn,Register rm,Register ra)3163   void smlsdx(Register rd, Register rn, Register rm, Register ra) {
3164     smlsdx(al, rd, rn, rm, ra);
3165   }
3166 
3167   void smlsld(
3168       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smlsld(Register rdlo,Register rdhi,Register rn,Register rm)3169   void smlsld(Register rdlo, Register rdhi, Register rn, Register rm) {
3170     smlsld(al, rdlo, rdhi, rn, rm);
3171   }
3172 
3173   void smlsldx(
3174       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smlsldx(Register rdlo,Register rdhi,Register rn,Register rm)3175   void smlsldx(Register rdlo, Register rdhi, Register rn, Register rm) {
3176     smlsldx(al, rdlo, rdhi, rn, rm);
3177   }
3178 
3179   void smmla(
3180       Condition cond, Register rd, Register rn, Register rm, Register ra);
smmla(Register rd,Register rn,Register rm,Register ra)3181   void smmla(Register rd, Register rn, Register rm, Register ra) {
3182     smmla(al, rd, rn, rm, ra);
3183   }
3184 
3185   void smmlar(
3186       Condition cond, Register rd, Register rn, Register rm, Register ra);
smmlar(Register rd,Register rn,Register rm,Register ra)3187   void smmlar(Register rd, Register rn, Register rm, Register ra) {
3188     smmlar(al, rd, rn, rm, ra);
3189   }
3190 
3191   void smmls(
3192       Condition cond, Register rd, Register rn, Register rm, Register ra);
smmls(Register rd,Register rn,Register rm,Register ra)3193   void smmls(Register rd, Register rn, Register rm, Register ra) {
3194     smmls(al, rd, rn, rm, ra);
3195   }
3196 
3197   void smmlsr(
3198       Condition cond, Register rd, Register rn, Register rm, Register ra);
smmlsr(Register rd,Register rn,Register rm,Register ra)3199   void smmlsr(Register rd, Register rn, Register rm, Register ra) {
3200     smmlsr(al, rd, rn, rm, ra);
3201   }
3202 
3203   void smmul(Condition cond, Register rd, Register rn, Register rm);
smmul(Register rd,Register rn,Register rm)3204   void smmul(Register rd, Register rn, Register rm) { smmul(al, rd, rn, rm); }
3205 
3206   void smmulr(Condition cond, Register rd, Register rn, Register rm);
smmulr(Register rd,Register rn,Register rm)3207   void smmulr(Register rd, Register rn, Register rm) { smmulr(al, rd, rn, rm); }
3208 
3209   void smuad(Condition cond, Register rd, Register rn, Register rm);
smuad(Register rd,Register rn,Register rm)3210   void smuad(Register rd, Register rn, Register rm) { smuad(al, rd, rn, rm); }
3211 
3212   void smuadx(Condition cond, Register rd, Register rn, Register rm);
smuadx(Register rd,Register rn,Register rm)3213   void smuadx(Register rd, Register rn, Register rm) { smuadx(al, rd, rn, rm); }
3214 
3215   void smulbb(Condition cond, Register rd, Register rn, Register rm);
smulbb(Register rd,Register rn,Register rm)3216   void smulbb(Register rd, Register rn, Register rm) { smulbb(al, rd, rn, rm); }
3217 
3218   void smulbt(Condition cond, Register rd, Register rn, Register rm);
smulbt(Register rd,Register rn,Register rm)3219   void smulbt(Register rd, Register rn, Register rm) { smulbt(al, rd, rn, rm); }
3220 
3221   void smull(
3222       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smull(Register rdlo,Register rdhi,Register rn,Register rm)3223   void smull(Register rdlo, Register rdhi, Register rn, Register rm) {
3224     smull(al, rdlo, rdhi, rn, rm);
3225   }
3226 
3227   void smulls(
3228       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
smulls(Register rdlo,Register rdhi,Register rn,Register rm)3229   void smulls(Register rdlo, Register rdhi, Register rn, Register rm) {
3230     smulls(al, rdlo, rdhi, rn, rm);
3231   }
3232 
3233   void smultb(Condition cond, Register rd, Register rn, Register rm);
smultb(Register rd,Register rn,Register rm)3234   void smultb(Register rd, Register rn, Register rm) { smultb(al, rd, rn, rm); }
3235 
3236   void smultt(Condition cond, Register rd, Register rn, Register rm);
smultt(Register rd,Register rn,Register rm)3237   void smultt(Register rd, Register rn, Register rm) { smultt(al, rd, rn, rm); }
3238 
3239   void smulwb(Condition cond, Register rd, Register rn, Register rm);
smulwb(Register rd,Register rn,Register rm)3240   void smulwb(Register rd, Register rn, Register rm) { smulwb(al, rd, rn, rm); }
3241 
3242   void smulwt(Condition cond, Register rd, Register rn, Register rm);
smulwt(Register rd,Register rn,Register rm)3243   void smulwt(Register rd, Register rn, Register rm) { smulwt(al, rd, rn, rm); }
3244 
3245   void smusd(Condition cond, Register rd, Register rn, Register rm);
smusd(Register rd,Register rn,Register rm)3246   void smusd(Register rd, Register rn, Register rm) { smusd(al, rd, rn, rm); }
3247 
3248   void smusdx(Condition cond, Register rd, Register rn, Register rm);
smusdx(Register rd,Register rn,Register rm)3249   void smusdx(Register rd, Register rn, Register rm) { smusdx(al, rd, rn, rm); }
3250 
3251   void ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand);
ssat(Register rd,uint32_t imm,const Operand & operand)3252   void ssat(Register rd, uint32_t imm, const Operand& operand) {
3253     ssat(al, rd, imm, operand);
3254   }
3255 
3256   void ssat16(Condition cond, Register rd, uint32_t imm, Register rn);
ssat16(Register rd,uint32_t imm,Register rn)3257   void ssat16(Register rd, uint32_t imm, Register rn) {
3258     ssat16(al, rd, imm, rn);
3259   }
3260 
3261   void ssax(Condition cond, Register rd, Register rn, Register rm);
ssax(Register rd,Register rn,Register rm)3262   void ssax(Register rd, Register rn, Register rm) { ssax(al, rd, rn, rm); }
3263 
3264   void ssub16(Condition cond, Register rd, Register rn, Register rm);
ssub16(Register rd,Register rn,Register rm)3265   void ssub16(Register rd, Register rn, Register rm) { ssub16(al, rd, rn, rm); }
3266 
3267   void ssub8(Condition cond, Register rd, Register rn, Register rm);
ssub8(Register rd,Register rn,Register rm)3268   void ssub8(Register rd, Register rn, Register rm) { ssub8(al, rd, rn, rm); }
3269 
3270   void stl(Condition cond, Register rt, const MemOperand& operand);
stl(Register rt,const MemOperand & operand)3271   void stl(Register rt, const MemOperand& operand) { stl(al, rt, operand); }
3272 
3273   void stlb(Condition cond, Register rt, const MemOperand& operand);
stlb(Register rt,const MemOperand & operand)3274   void stlb(Register rt, const MemOperand& operand) { stlb(al, rt, operand); }
3275 
3276   void stlex(Condition cond,
3277              Register rd,
3278              Register rt,
3279              const MemOperand& operand);
stlex(Register rd,Register rt,const MemOperand & operand)3280   void stlex(Register rd, Register rt, const MemOperand& operand) {
3281     stlex(al, rd, rt, operand);
3282   }
3283 
3284   void stlexb(Condition cond,
3285               Register rd,
3286               Register rt,
3287               const MemOperand& operand);
stlexb(Register rd,Register rt,const MemOperand & operand)3288   void stlexb(Register rd, Register rt, const MemOperand& operand) {
3289     stlexb(al, rd, rt, operand);
3290   }
3291 
3292   void stlexd(Condition cond,
3293               Register rd,
3294               Register rt,
3295               Register rt2,
3296               const MemOperand& operand);
stlexd(Register rd,Register rt,Register rt2,const MemOperand & operand)3297   void stlexd(Register rd,
3298               Register rt,
3299               Register rt2,
3300               const MemOperand& operand) {
3301     stlexd(al, rd, rt, rt2, operand);
3302   }
3303 
3304   void stlexh(Condition cond,
3305               Register rd,
3306               Register rt,
3307               const MemOperand& operand);
stlexh(Register rd,Register rt,const MemOperand & operand)3308   void stlexh(Register rd, Register rt, const MemOperand& operand) {
3309     stlexh(al, rd, rt, operand);
3310   }
3311 
3312   void stlh(Condition cond, Register rt, const MemOperand& operand);
stlh(Register rt,const MemOperand & operand)3313   void stlh(Register rt, const MemOperand& operand) { stlh(al, rt, operand); }
3314 
3315   void stm(Condition cond,
3316            EncodingSize size,
3317            Register rn,
3318            WriteBack write_back,
3319            RegisterList registers);
stm(Register rn,WriteBack write_back,RegisterList registers)3320   void stm(Register rn, WriteBack write_back, RegisterList registers) {
3321     stm(al, Best, rn, write_back, registers);
3322   }
stm(Condition cond,Register rn,WriteBack write_back,RegisterList registers)3323   void stm(Condition cond,
3324            Register rn,
3325            WriteBack write_back,
3326            RegisterList registers) {
3327     stm(cond, Best, rn, write_back, registers);
3328   }
stm(EncodingSize size,Register rn,WriteBack write_back,RegisterList registers)3329   void stm(EncodingSize size,
3330            Register rn,
3331            WriteBack write_back,
3332            RegisterList registers) {
3333     stm(al, size, rn, write_back, registers);
3334   }
3335 
3336   void stmda(Condition cond,
3337              Register rn,
3338              WriteBack write_back,
3339              RegisterList registers);
stmda(Register rn,WriteBack write_back,RegisterList registers)3340   void stmda(Register rn, WriteBack write_back, RegisterList registers) {
3341     stmda(al, rn, write_back, registers);
3342   }
3343 
3344   void stmdb(Condition cond,
3345              EncodingSize size,
3346              Register rn,
3347              WriteBack write_back,
3348              RegisterList registers);
stmdb(Register rn,WriteBack write_back,RegisterList registers)3349   void stmdb(Register rn, WriteBack write_back, RegisterList registers) {
3350     stmdb(al, Best, rn, write_back, registers);
3351   }
stmdb(Condition cond,Register rn,WriteBack write_back,RegisterList registers)3352   void stmdb(Condition cond,
3353              Register rn,
3354              WriteBack write_back,
3355              RegisterList registers) {
3356     stmdb(cond, Best, rn, write_back, registers);
3357   }
stmdb(EncodingSize size,Register rn,WriteBack write_back,RegisterList registers)3358   void stmdb(EncodingSize size,
3359              Register rn,
3360              WriteBack write_back,
3361              RegisterList registers) {
3362     stmdb(al, size, rn, write_back, registers);
3363   }
3364 
3365   void stmea(Condition cond,
3366              EncodingSize size,
3367              Register rn,
3368              WriteBack write_back,
3369              RegisterList registers);
stmea(Register rn,WriteBack write_back,RegisterList registers)3370   void stmea(Register rn, WriteBack write_back, RegisterList registers) {
3371     stmea(al, Best, rn, write_back, registers);
3372   }
stmea(Condition cond,Register rn,WriteBack write_back,RegisterList registers)3373   void stmea(Condition cond,
3374              Register rn,
3375              WriteBack write_back,
3376              RegisterList registers) {
3377     stmea(cond, Best, rn, write_back, registers);
3378   }
stmea(EncodingSize size,Register rn,WriteBack write_back,RegisterList registers)3379   void stmea(EncodingSize size,
3380              Register rn,
3381              WriteBack write_back,
3382              RegisterList registers) {
3383     stmea(al, size, rn, write_back, registers);
3384   }
3385 
3386   void stmed(Condition cond,
3387              Register rn,
3388              WriteBack write_back,
3389              RegisterList registers);
stmed(Register rn,WriteBack write_back,RegisterList registers)3390   void stmed(Register rn, WriteBack write_back, RegisterList registers) {
3391     stmed(al, rn, write_back, registers);
3392   }
3393 
3394   void stmfa(Condition cond,
3395              Register rn,
3396              WriteBack write_back,
3397              RegisterList registers);
stmfa(Register rn,WriteBack write_back,RegisterList registers)3398   void stmfa(Register rn, WriteBack write_back, RegisterList registers) {
3399     stmfa(al, rn, write_back, registers);
3400   }
3401 
3402   void stmfd(Condition cond,
3403              Register rn,
3404              WriteBack write_back,
3405              RegisterList registers);
stmfd(Register rn,WriteBack write_back,RegisterList registers)3406   void stmfd(Register rn, WriteBack write_back, RegisterList registers) {
3407     stmfd(al, rn, write_back, registers);
3408   }
3409 
3410   void stmib(Condition cond,
3411              Register rn,
3412              WriteBack write_back,
3413              RegisterList registers);
stmib(Register rn,WriteBack write_back,RegisterList registers)3414   void stmib(Register rn, WriteBack write_back, RegisterList registers) {
3415     stmib(al, rn, write_back, registers);
3416   }
3417 
3418   void str(Condition cond,
3419            EncodingSize size,
3420            Register rt,
3421            const MemOperand& operand);
str(Register rt,const MemOperand & operand)3422   void str(Register rt, const MemOperand& operand) {
3423     str(al, Best, rt, operand);
3424   }
str(Condition cond,Register rt,const MemOperand & operand)3425   void str(Condition cond, Register rt, const MemOperand& operand) {
3426     str(cond, Best, rt, operand);
3427   }
str(EncodingSize size,Register rt,const MemOperand & operand)3428   void str(EncodingSize size, Register rt, const MemOperand& operand) {
3429     str(al, size, rt, operand);
3430   }
3431 
3432   void strb(Condition cond,
3433             EncodingSize size,
3434             Register rt,
3435             const MemOperand& operand);
strb(Register rt,const MemOperand & operand)3436   void strb(Register rt, const MemOperand& operand) {
3437     strb(al, Best, rt, operand);
3438   }
strb(Condition cond,Register rt,const MemOperand & operand)3439   void strb(Condition cond, Register rt, const MemOperand& operand) {
3440     strb(cond, Best, rt, operand);
3441   }
strb(EncodingSize size,Register rt,const MemOperand & operand)3442   void strb(EncodingSize size, Register rt, const MemOperand& operand) {
3443     strb(al, size, rt, operand);
3444   }
3445 
3446   void strd(Condition cond,
3447             Register rt,
3448             Register rt2,
3449             const MemOperand& operand);
strd(Register rt,Register rt2,const MemOperand & operand)3450   void strd(Register rt, Register rt2, const MemOperand& operand) {
3451     strd(al, rt, rt2, operand);
3452   }
3453 
3454   void strex(Condition cond,
3455              Register rd,
3456              Register rt,
3457              const MemOperand& operand);
strex(Register rd,Register rt,const MemOperand & operand)3458   void strex(Register rd, Register rt, const MemOperand& operand) {
3459     strex(al, rd, rt, operand);
3460   }
3461 
3462   void strexb(Condition cond,
3463               Register rd,
3464               Register rt,
3465               const MemOperand& operand);
strexb(Register rd,Register rt,const MemOperand & operand)3466   void strexb(Register rd, Register rt, const MemOperand& operand) {
3467     strexb(al, rd, rt, operand);
3468   }
3469 
3470   void strexd(Condition cond,
3471               Register rd,
3472               Register rt,
3473               Register rt2,
3474               const MemOperand& operand);
strexd(Register rd,Register rt,Register rt2,const MemOperand & operand)3475   void strexd(Register rd,
3476               Register rt,
3477               Register rt2,
3478               const MemOperand& operand) {
3479     strexd(al, rd, rt, rt2, operand);
3480   }
3481 
3482   void strexh(Condition cond,
3483               Register rd,
3484               Register rt,
3485               const MemOperand& operand);
strexh(Register rd,Register rt,const MemOperand & operand)3486   void strexh(Register rd, Register rt, const MemOperand& operand) {
3487     strexh(al, rd, rt, operand);
3488   }
3489 
3490   void strh(Condition cond,
3491             EncodingSize size,
3492             Register rt,
3493             const MemOperand& operand);
strh(Register rt,const MemOperand & operand)3494   void strh(Register rt, const MemOperand& operand) {
3495     strh(al, Best, rt, operand);
3496   }
strh(Condition cond,Register rt,const MemOperand & operand)3497   void strh(Condition cond, Register rt, const MemOperand& operand) {
3498     strh(cond, Best, rt, operand);
3499   }
strh(EncodingSize size,Register rt,const MemOperand & operand)3500   void strh(EncodingSize size, Register rt, const MemOperand& operand) {
3501     strh(al, size, rt, operand);
3502   }
3503 
3504   void sub(Condition cond,
3505            EncodingSize size,
3506            Register rd,
3507            Register rn,
3508            const Operand& operand);
sub(Register rd,Register rn,const Operand & operand)3509   void sub(Register rd, Register rn, const Operand& operand) {
3510     sub(al, Best, rd, rn, operand);
3511   }
sub(Condition cond,Register rd,Register rn,const Operand & operand)3512   void sub(Condition cond, Register rd, Register rn, const Operand& operand) {
3513     sub(cond, Best, rd, rn, operand);
3514   }
sub(EncodingSize size,Register rd,Register rn,const Operand & operand)3515   void sub(EncodingSize size,
3516            Register rd,
3517            Register rn,
3518            const Operand& operand) {
3519     sub(al, size, rd, rn, operand);
3520   }
3521 
3522   void sub(Condition cond, Register rd, const Operand& operand);
sub(Register rd,const Operand & operand)3523   void sub(Register rd, const Operand& operand) { sub(al, rd, operand); }
3524 
3525   void subs(Condition cond,
3526             EncodingSize size,
3527             Register rd,
3528             Register rn,
3529             const Operand& operand);
subs(Register rd,Register rn,const Operand & operand)3530   void subs(Register rd, Register rn, const Operand& operand) {
3531     subs(al, Best, rd, rn, operand);
3532   }
subs(Condition cond,Register rd,Register rn,const Operand & operand)3533   void subs(Condition cond, Register rd, Register rn, const Operand& operand) {
3534     subs(cond, Best, rd, rn, operand);
3535   }
subs(EncodingSize size,Register rd,Register rn,const Operand & operand)3536   void subs(EncodingSize size,
3537             Register rd,
3538             Register rn,
3539             const Operand& operand) {
3540     subs(al, size, rd, rn, operand);
3541   }
3542 
3543   void subs(Register rd, const Operand& operand);
3544 
3545   void subw(Condition cond, Register rd, Register rn, const Operand& operand);
subw(Register rd,Register rn,const Operand & operand)3546   void subw(Register rd, Register rn, const Operand& operand) {
3547     subw(al, rd, rn, operand);
3548   }
3549 
3550   void svc(Condition cond, uint32_t imm);
svc(uint32_t imm)3551   void svc(uint32_t imm) { svc(al, imm); }
3552 
3553   void sxtab(Condition cond, Register rd, Register rn, const Operand& operand);
sxtab(Register rd,Register rn,const Operand & operand)3554   void sxtab(Register rd, Register rn, const Operand& operand) {
3555     sxtab(al, rd, rn, operand);
3556   }
3557 
3558   void sxtab16(Condition cond,
3559                Register rd,
3560                Register rn,
3561                const Operand& operand);
sxtab16(Register rd,Register rn,const Operand & operand)3562   void sxtab16(Register rd, Register rn, const Operand& operand) {
3563     sxtab16(al, rd, rn, operand);
3564   }
3565 
3566   void sxtah(Condition cond, Register rd, Register rn, const Operand& operand);
sxtah(Register rd,Register rn,const Operand & operand)3567   void sxtah(Register rd, Register rn, const Operand& operand) {
3568     sxtah(al, rd, rn, operand);
3569   }
3570 
3571   void sxtb(Condition cond,
3572             EncodingSize size,
3573             Register rd,
3574             const Operand& operand);
sxtb(Register rd,const Operand & operand)3575   void sxtb(Register rd, const Operand& operand) {
3576     sxtb(al, Best, rd, operand);
3577   }
sxtb(Condition cond,Register rd,const Operand & operand)3578   void sxtb(Condition cond, Register rd, const Operand& operand) {
3579     sxtb(cond, Best, rd, operand);
3580   }
sxtb(EncodingSize size,Register rd,const Operand & operand)3581   void sxtb(EncodingSize size, Register rd, const Operand& operand) {
3582     sxtb(al, size, rd, operand);
3583   }
3584 
3585   void sxtb16(Condition cond, Register rd, const Operand& operand);
sxtb16(Register rd,const Operand & operand)3586   void sxtb16(Register rd, const Operand& operand) { sxtb16(al, rd, operand); }
3587 
3588   void sxth(Condition cond,
3589             EncodingSize size,
3590             Register rd,
3591             const Operand& operand);
sxth(Register rd,const Operand & operand)3592   void sxth(Register rd, const Operand& operand) {
3593     sxth(al, Best, rd, operand);
3594   }
sxth(Condition cond,Register rd,const Operand & operand)3595   void sxth(Condition cond, Register rd, const Operand& operand) {
3596     sxth(cond, Best, rd, operand);
3597   }
sxth(EncodingSize size,Register rd,const Operand & operand)3598   void sxth(EncodingSize size, Register rd, const Operand& operand) {
3599     sxth(al, size, rd, operand);
3600   }
3601 
3602   void tbb(Condition cond, Register rn, Register rm);
tbb(Register rn,Register rm)3603   void tbb(Register rn, Register rm) { tbb(al, rn, rm); }
3604 
3605   void tbh(Condition cond, Register rn, Register rm);
tbh(Register rn,Register rm)3606   void tbh(Register rn, Register rm) { tbh(al, rn, rm); }
3607 
3608   void teq(Condition cond, Register rn, const Operand& operand);
teq(Register rn,const Operand & operand)3609   void teq(Register rn, const Operand& operand) { teq(al, rn, operand); }
3610 
3611   void tst(Condition cond,
3612            EncodingSize size,
3613            Register rn,
3614            const Operand& operand);
tst(Register rn,const Operand & operand)3615   void tst(Register rn, const Operand& operand) { tst(al, Best, rn, operand); }
tst(Condition cond,Register rn,const Operand & operand)3616   void tst(Condition cond, Register rn, const Operand& operand) {
3617     tst(cond, Best, rn, operand);
3618   }
tst(EncodingSize size,Register rn,const Operand & operand)3619   void tst(EncodingSize size, Register rn, const Operand& operand) {
3620     tst(al, size, rn, operand);
3621   }
3622 
3623   void uadd16(Condition cond, Register rd, Register rn, Register rm);
uadd16(Register rd,Register rn,Register rm)3624   void uadd16(Register rd, Register rn, Register rm) { uadd16(al, rd, rn, rm); }
3625 
3626   void uadd8(Condition cond, Register rd, Register rn, Register rm);
uadd8(Register rd,Register rn,Register rm)3627   void uadd8(Register rd, Register rn, Register rm) { uadd8(al, rd, rn, rm); }
3628 
3629   void uasx(Condition cond, Register rd, Register rn, Register rm);
uasx(Register rd,Register rn,Register rm)3630   void uasx(Register rd, Register rn, Register rm) { uasx(al, rd, rn, rm); }
3631 
3632   void ubfx(
3633       Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
ubfx(Register rd,Register rn,uint32_t lsb,uint32_t width)3634   void ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width) {
3635     ubfx(al, rd, rn, lsb, width);
3636   }
3637 
3638   void udf(Condition cond, EncodingSize size, uint32_t imm);
udf(uint32_t imm)3639   void udf(uint32_t imm) { udf(al, Best, imm); }
udf(Condition cond,uint32_t imm)3640   void udf(Condition cond, uint32_t imm) { udf(cond, Best, imm); }
udf(EncodingSize size,uint32_t imm)3641   void udf(EncodingSize size, uint32_t imm) { udf(al, size, imm); }
3642 
3643   void udiv(Condition cond, Register rd, Register rn, Register rm);
udiv(Register rd,Register rn,Register rm)3644   void udiv(Register rd, Register rn, Register rm) { udiv(al, rd, rn, rm); }
3645 
3646   void uhadd16(Condition cond, Register rd, Register rn, Register rm);
uhadd16(Register rd,Register rn,Register rm)3647   void uhadd16(Register rd, Register rn, Register rm) {
3648     uhadd16(al, rd, rn, rm);
3649   }
3650 
3651   void uhadd8(Condition cond, Register rd, Register rn, Register rm);
uhadd8(Register rd,Register rn,Register rm)3652   void uhadd8(Register rd, Register rn, Register rm) { uhadd8(al, rd, rn, rm); }
3653 
3654   void uhasx(Condition cond, Register rd, Register rn, Register rm);
uhasx(Register rd,Register rn,Register rm)3655   void uhasx(Register rd, Register rn, Register rm) { uhasx(al, rd, rn, rm); }
3656 
3657   void uhsax(Condition cond, Register rd, Register rn, Register rm);
uhsax(Register rd,Register rn,Register rm)3658   void uhsax(Register rd, Register rn, Register rm) { uhsax(al, rd, rn, rm); }
3659 
3660   void uhsub16(Condition cond, Register rd, Register rn, Register rm);
uhsub16(Register rd,Register rn,Register rm)3661   void uhsub16(Register rd, Register rn, Register rm) {
3662     uhsub16(al, rd, rn, rm);
3663   }
3664 
3665   void uhsub8(Condition cond, Register rd, Register rn, Register rm);
uhsub8(Register rd,Register rn,Register rm)3666   void uhsub8(Register rd, Register rn, Register rm) { uhsub8(al, rd, rn, rm); }
3667 
3668   void umaal(
3669       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
umaal(Register rdlo,Register rdhi,Register rn,Register rm)3670   void umaal(Register rdlo, Register rdhi, Register rn, Register rm) {
3671     umaal(al, rdlo, rdhi, rn, rm);
3672   }
3673 
3674   void umlal(
3675       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
umlal(Register rdlo,Register rdhi,Register rn,Register rm)3676   void umlal(Register rdlo, Register rdhi, Register rn, Register rm) {
3677     umlal(al, rdlo, rdhi, rn, rm);
3678   }
3679 
3680   void umlals(
3681       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
umlals(Register rdlo,Register rdhi,Register rn,Register rm)3682   void umlals(Register rdlo, Register rdhi, Register rn, Register rm) {
3683     umlals(al, rdlo, rdhi, rn, rm);
3684   }
3685 
3686   void umull(
3687       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
umull(Register rdlo,Register rdhi,Register rn,Register rm)3688   void umull(Register rdlo, Register rdhi, Register rn, Register rm) {
3689     umull(al, rdlo, rdhi, rn, rm);
3690   }
3691 
3692   void umulls(
3693       Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
umulls(Register rdlo,Register rdhi,Register rn,Register rm)3694   void umulls(Register rdlo, Register rdhi, Register rn, Register rm) {
3695     umulls(al, rdlo, rdhi, rn, rm);
3696   }
3697 
3698   void uqadd16(Condition cond, Register rd, Register rn, Register rm);
uqadd16(Register rd,Register rn,Register rm)3699   void uqadd16(Register rd, Register rn, Register rm) {
3700     uqadd16(al, rd, rn, rm);
3701   }
3702 
3703   void uqadd8(Condition cond, Register rd, Register rn, Register rm);
uqadd8(Register rd,Register rn,Register rm)3704   void uqadd8(Register rd, Register rn, Register rm) { uqadd8(al, rd, rn, rm); }
3705 
3706   void uqasx(Condition cond, Register rd, Register rn, Register rm);
uqasx(Register rd,Register rn,Register rm)3707   void uqasx(Register rd, Register rn, Register rm) { uqasx(al, rd, rn, rm); }
3708 
3709   void uqsax(Condition cond, Register rd, Register rn, Register rm);
uqsax(Register rd,Register rn,Register rm)3710   void uqsax(Register rd, Register rn, Register rm) { uqsax(al, rd, rn, rm); }
3711 
3712   void uqsub16(Condition cond, Register rd, Register rn, Register rm);
uqsub16(Register rd,Register rn,Register rm)3713   void uqsub16(Register rd, Register rn, Register rm) {
3714     uqsub16(al, rd, rn, rm);
3715   }
3716 
3717   void uqsub8(Condition cond, Register rd, Register rn, Register rm);
uqsub8(Register rd,Register rn,Register rm)3718   void uqsub8(Register rd, Register rn, Register rm) { uqsub8(al, rd, rn, rm); }
3719 
3720   void usad8(Condition cond, Register rd, Register rn, Register rm);
usad8(Register rd,Register rn,Register rm)3721   void usad8(Register rd, Register rn, Register rm) { usad8(al, rd, rn, rm); }
3722 
3723   void usada8(
3724       Condition cond, Register rd, Register rn, Register rm, Register ra);
usada8(Register rd,Register rn,Register rm,Register ra)3725   void usada8(Register rd, Register rn, Register rm, Register ra) {
3726     usada8(al, rd, rn, rm, ra);
3727   }
3728 
3729   void usat(Condition cond, Register rd, uint32_t imm, const Operand& operand);
usat(Register rd,uint32_t imm,const Operand & operand)3730   void usat(Register rd, uint32_t imm, const Operand& operand) {
3731     usat(al, rd, imm, operand);
3732   }
3733 
3734   void usat16(Condition cond, Register rd, uint32_t imm, Register rn);
usat16(Register rd,uint32_t imm,Register rn)3735   void usat16(Register rd, uint32_t imm, Register rn) {
3736     usat16(al, rd, imm, rn);
3737   }
3738 
3739   void usax(Condition cond, Register rd, Register rn, Register rm);
usax(Register rd,Register rn,Register rm)3740   void usax(Register rd, Register rn, Register rm) { usax(al, rd, rn, rm); }
3741 
3742   void usub16(Condition cond, Register rd, Register rn, Register rm);
usub16(Register rd,Register rn,Register rm)3743   void usub16(Register rd, Register rn, Register rm) { usub16(al, rd, rn, rm); }
3744 
3745   void usub8(Condition cond, Register rd, Register rn, Register rm);
usub8(Register rd,Register rn,Register rm)3746   void usub8(Register rd, Register rn, Register rm) { usub8(al, rd, rn, rm); }
3747 
3748   void uxtab(Condition cond, Register rd, Register rn, const Operand& operand);
uxtab(Register rd,Register rn,const Operand & operand)3749   void uxtab(Register rd, Register rn, const Operand& operand) {
3750     uxtab(al, rd, rn, operand);
3751   }
3752 
3753   void uxtab16(Condition cond,
3754                Register rd,
3755                Register rn,
3756                const Operand& operand);
uxtab16(Register rd,Register rn,const Operand & operand)3757   void uxtab16(Register rd, Register rn, const Operand& operand) {
3758     uxtab16(al, rd, rn, operand);
3759   }
3760 
3761   void uxtah(Condition cond, Register rd, Register rn, const Operand& operand);
uxtah(Register rd,Register rn,const Operand & operand)3762   void uxtah(Register rd, Register rn, const Operand& operand) {
3763     uxtah(al, rd, rn, operand);
3764   }
3765 
3766   void uxtb(Condition cond,
3767             EncodingSize size,
3768             Register rd,
3769             const Operand& operand);
uxtb(Register rd,const Operand & operand)3770   void uxtb(Register rd, const Operand& operand) {
3771     uxtb(al, Best, rd, operand);
3772   }
uxtb(Condition cond,Register rd,const Operand & operand)3773   void uxtb(Condition cond, Register rd, const Operand& operand) {
3774     uxtb(cond, Best, rd, operand);
3775   }
uxtb(EncodingSize size,Register rd,const Operand & operand)3776   void uxtb(EncodingSize size, Register rd, const Operand& operand) {
3777     uxtb(al, size, rd, operand);
3778   }
3779 
3780   void uxtb16(Condition cond, Register rd, const Operand& operand);
uxtb16(Register rd,const Operand & operand)3781   void uxtb16(Register rd, const Operand& operand) { uxtb16(al, rd, operand); }
3782 
3783   void uxth(Condition cond,
3784             EncodingSize size,
3785             Register rd,
3786             const Operand& operand);
uxth(Register rd,const Operand & operand)3787   void uxth(Register rd, const Operand& operand) {
3788     uxth(al, Best, rd, operand);
3789   }
uxth(Condition cond,Register rd,const Operand & operand)3790   void uxth(Condition cond, Register rd, const Operand& operand) {
3791     uxth(cond, Best, rd, operand);
3792   }
uxth(EncodingSize size,Register rd,const Operand & operand)3793   void uxth(EncodingSize size, Register rd, const Operand& operand) {
3794     uxth(al, size, rd, operand);
3795   }
3796 
3797   void vaba(
3798       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vaba(DataType dt,DRegister rd,DRegister rn,DRegister rm)3799   void vaba(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
3800     vaba(al, dt, rd, rn, rm);
3801   }
3802 
3803   void vaba(
3804       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vaba(DataType dt,QRegister rd,QRegister rn,QRegister rm)3805   void vaba(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
3806     vaba(al, dt, rd, rn, rm);
3807   }
3808 
3809   void vabal(
3810       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
vabal(DataType dt,QRegister rd,DRegister rn,DRegister rm)3811   void vabal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
3812     vabal(al, dt, rd, rn, rm);
3813   }
3814 
3815   void vabd(
3816       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vabd(DataType dt,DRegister rd,DRegister rn,DRegister rm)3817   void vabd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
3818     vabd(al, dt, rd, rn, rm);
3819   }
3820 
3821   void vabd(
3822       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vabd(DataType dt,QRegister rd,QRegister rn,QRegister rm)3823   void vabd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
3824     vabd(al, dt, rd, rn, rm);
3825   }
3826 
3827   void vabdl(
3828       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
vabdl(DataType dt,QRegister rd,DRegister rn,DRegister rm)3829   void vabdl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
3830     vabdl(al, dt, rd, rn, rm);
3831   }
3832 
3833   void vabs(Condition cond, DataType dt, DRegister rd, DRegister rm);
vabs(DataType dt,DRegister rd,DRegister rm)3834   void vabs(DataType dt, DRegister rd, DRegister rm) { vabs(al, dt, rd, rm); }
3835 
3836   void vabs(Condition cond, DataType dt, QRegister rd, QRegister rm);
vabs(DataType dt,QRegister rd,QRegister rm)3837   void vabs(DataType dt, QRegister rd, QRegister rm) { vabs(al, dt, rd, rm); }
3838 
3839   void vabs(Condition cond, DataType dt, SRegister rd, SRegister rm);
vabs(DataType dt,SRegister rd,SRegister rm)3840   void vabs(DataType dt, SRegister rd, SRegister rm) { vabs(al, dt, rd, rm); }
3841 
3842   void vacge(
3843       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vacge(DataType dt,DRegister rd,DRegister rn,DRegister rm)3844   void vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
3845     vacge(al, dt, rd, rn, rm);
3846   }
3847 
3848   void vacge(
3849       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vacge(DataType dt,QRegister rd,QRegister rn,QRegister rm)3850   void vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
3851     vacge(al, dt, rd, rn, rm);
3852   }
3853 
3854   void vacgt(
3855       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vacgt(DataType dt,DRegister rd,DRegister rn,DRegister rm)3856   void vacgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
3857     vacgt(al, dt, rd, rn, rm);
3858   }
3859 
3860   void vacgt(
3861       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vacgt(DataType dt,QRegister rd,QRegister rn,QRegister rm)3862   void vacgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
3863     vacgt(al, dt, rd, rn, rm);
3864   }
3865 
3866   void vacle(
3867       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vacle(DataType dt,DRegister rd,DRegister rn,DRegister rm)3868   void vacle(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
3869     vacle(al, dt, rd, rn, rm);
3870   }
3871 
3872   void vacle(
3873       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vacle(DataType dt,QRegister rd,QRegister rn,QRegister rm)3874   void vacle(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
3875     vacle(al, dt, rd, rn, rm);
3876   }
3877 
3878   void vaclt(
3879       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vaclt(DataType dt,DRegister rd,DRegister rn,DRegister rm)3880   void vaclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
3881     vaclt(al, dt, rd, rn, rm);
3882   }
3883 
3884   void vaclt(
3885       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vaclt(DataType dt,QRegister rd,QRegister rn,QRegister rm)3886   void vaclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
3887     vaclt(al, dt, rd, rn, rm);
3888   }
3889 
3890   void vadd(
3891       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vadd(DataType dt,DRegister rd,DRegister rn,DRegister rm)3892   void vadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
3893     vadd(al, dt, rd, rn, rm);
3894   }
3895 
3896   void vadd(
3897       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vadd(DataType dt,QRegister rd,QRegister rn,QRegister rm)3898   void vadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
3899     vadd(al, dt, rd, rn, rm);
3900   }
3901 
3902   void vadd(
3903       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vadd(DataType dt,SRegister rd,SRegister rn,SRegister rm)3904   void vadd(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
3905     vadd(al, dt, rd, rn, rm);
3906   }
3907 
3908   void vaddhn(
3909       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
vaddhn(DataType dt,DRegister rd,QRegister rn,QRegister rm)3910   void vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
3911     vaddhn(al, dt, rd, rn, rm);
3912   }
3913 
3914   void vaddl(
3915       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
vaddl(DataType dt,QRegister rd,DRegister rn,DRegister rm)3916   void vaddl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
3917     vaddl(al, dt, rd, rn, rm);
3918   }
3919 
3920   void vaddw(
3921       Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm);
vaddw(DataType dt,QRegister rd,QRegister rn,DRegister rm)3922   void vaddw(DataType dt, QRegister rd, QRegister rn, DRegister rm) {
3923     vaddw(al, dt, rd, rn, rm);
3924   }
3925 
3926   void vand(Condition cond,
3927             DataType dt,
3928             DRegister rd,
3929             DRegister rn,
3930             const DOperand& operand);
vand(DataType dt,DRegister rd,DRegister rn,const DOperand & operand)3931   void vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
3932     vand(al, dt, rd, rn, operand);
3933   }
3934 
3935   void vand(Condition cond,
3936             DataType dt,
3937             QRegister rd,
3938             QRegister rn,
3939             const QOperand& operand);
vand(DataType dt,QRegister rd,QRegister rn,const QOperand & operand)3940   void vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
3941     vand(al, dt, rd, rn, operand);
3942   }
3943 
3944   void vbic(Condition cond,
3945             DataType dt,
3946             DRegister rd,
3947             DRegister rn,
3948             const DOperand& operand);
vbic(DataType dt,DRegister rd,DRegister rn,const DOperand & operand)3949   void vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
3950     vbic(al, dt, rd, rn, operand);
3951   }
3952 
3953   void vbic(Condition cond,
3954             DataType dt,
3955             QRegister rd,
3956             QRegister rn,
3957             const QOperand& operand);
vbic(DataType dt,QRegister rd,QRegister rn,const QOperand & operand)3958   void vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
3959     vbic(al, dt, rd, rn, operand);
3960   }
3961 
3962   void vbif(
3963       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vbif(DataType dt,DRegister rd,DRegister rn,DRegister rm)3964   void vbif(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
3965     vbif(al, dt, rd, rn, rm);
3966   }
vbif(DRegister rd,DRegister rn,DRegister rm)3967   void vbif(DRegister rd, DRegister rn, DRegister rm) {
3968     vbif(al, kDataTypeValueNone, rd, rn, rm);
3969   }
vbif(Condition cond,DRegister rd,DRegister rn,DRegister rm)3970   void vbif(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
3971     vbif(cond, kDataTypeValueNone, rd, rn, rm);
3972   }
3973 
3974   void vbif(
3975       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vbif(DataType dt,QRegister rd,QRegister rn,QRegister rm)3976   void vbif(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
3977     vbif(al, dt, rd, rn, rm);
3978   }
vbif(QRegister rd,QRegister rn,QRegister rm)3979   void vbif(QRegister rd, QRegister rn, QRegister rm) {
3980     vbif(al, kDataTypeValueNone, rd, rn, rm);
3981   }
vbif(Condition cond,QRegister rd,QRegister rn,QRegister rm)3982   void vbif(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
3983     vbif(cond, kDataTypeValueNone, rd, rn, rm);
3984   }
3985 
3986   void vbit(
3987       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vbit(DataType dt,DRegister rd,DRegister rn,DRegister rm)3988   void vbit(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
3989     vbit(al, dt, rd, rn, rm);
3990   }
vbit(DRegister rd,DRegister rn,DRegister rm)3991   void vbit(DRegister rd, DRegister rn, DRegister rm) {
3992     vbit(al, kDataTypeValueNone, rd, rn, rm);
3993   }
vbit(Condition cond,DRegister rd,DRegister rn,DRegister rm)3994   void vbit(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
3995     vbit(cond, kDataTypeValueNone, rd, rn, rm);
3996   }
3997 
3998   void vbit(
3999       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vbit(DataType dt,QRegister rd,QRegister rn,QRegister rm)4000   void vbit(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4001     vbit(al, dt, rd, rn, rm);
4002   }
vbit(QRegister rd,QRegister rn,QRegister rm)4003   void vbit(QRegister rd, QRegister rn, QRegister rm) {
4004     vbit(al, kDataTypeValueNone, rd, rn, rm);
4005   }
vbit(Condition cond,QRegister rd,QRegister rn,QRegister rm)4006   void vbit(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
4007     vbit(cond, kDataTypeValueNone, rd, rn, rm);
4008   }
4009 
4010   void vbsl(
4011       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vbsl(DataType dt,DRegister rd,DRegister rn,DRegister rm)4012   void vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4013     vbsl(al, dt, rd, rn, rm);
4014   }
vbsl(DRegister rd,DRegister rn,DRegister rm)4015   void vbsl(DRegister rd, DRegister rn, DRegister rm) {
4016     vbsl(al, kDataTypeValueNone, rd, rn, rm);
4017   }
vbsl(Condition cond,DRegister rd,DRegister rn,DRegister rm)4018   void vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
4019     vbsl(cond, kDataTypeValueNone, rd, rn, rm);
4020   }
4021 
4022   void vbsl(
4023       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vbsl(DataType dt,QRegister rd,QRegister rn,QRegister rm)4024   void vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4025     vbsl(al, dt, rd, rn, rm);
4026   }
vbsl(QRegister rd,QRegister rn,QRegister rm)4027   void vbsl(QRegister rd, QRegister rn, QRegister rm) {
4028     vbsl(al, kDataTypeValueNone, rd, rn, rm);
4029   }
vbsl(Condition cond,QRegister rd,QRegister rn,QRegister rm)4030   void vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
4031     vbsl(cond, kDataTypeValueNone, rd, rn, rm);
4032   }
4033 
4034   void vceq(Condition cond,
4035             DataType dt,
4036             DRegister rd,
4037             DRegister rm,
4038             const DOperand& operand);
vceq(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)4039   void vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
4040     vceq(al, dt, rd, rm, operand);
4041   }
4042 
4043   void vceq(Condition cond,
4044             DataType dt,
4045             QRegister rd,
4046             QRegister rm,
4047             const QOperand& operand);
vceq(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)4048   void vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
4049     vceq(al, dt, rd, rm, operand);
4050   }
4051 
4052   void vceq(
4053       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vceq(DataType dt,DRegister rd,DRegister rn,DRegister rm)4054   void vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4055     vceq(al, dt, rd, rn, rm);
4056   }
4057 
4058   void vceq(
4059       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vceq(DataType dt,QRegister rd,QRegister rn,QRegister rm)4060   void vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4061     vceq(al, dt, rd, rn, rm);
4062   }
4063 
4064   void vcge(Condition cond,
4065             DataType dt,
4066             DRegister rd,
4067             DRegister rm,
4068             const DOperand& operand);
vcge(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)4069   void vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
4070     vcge(al, dt, rd, rm, operand);
4071   }
4072 
4073   void vcge(Condition cond,
4074             DataType dt,
4075             QRegister rd,
4076             QRegister rm,
4077             const QOperand& operand);
vcge(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)4078   void vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
4079     vcge(al, dt, rd, rm, operand);
4080   }
4081 
4082   void vcge(
4083       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vcge(DataType dt,DRegister rd,DRegister rn,DRegister rm)4084   void vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4085     vcge(al, dt, rd, rn, rm);
4086   }
4087 
4088   void vcge(
4089       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vcge(DataType dt,QRegister rd,QRegister rn,QRegister rm)4090   void vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4091     vcge(al, dt, rd, rn, rm);
4092   }
4093 
4094   void vcgt(Condition cond,
4095             DataType dt,
4096             DRegister rd,
4097             DRegister rm,
4098             const DOperand& operand);
vcgt(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)4099   void vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
4100     vcgt(al, dt, rd, rm, operand);
4101   }
4102 
4103   void vcgt(Condition cond,
4104             DataType dt,
4105             QRegister rd,
4106             QRegister rm,
4107             const QOperand& operand);
vcgt(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)4108   void vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
4109     vcgt(al, dt, rd, rm, operand);
4110   }
4111 
4112   void vcgt(
4113       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vcgt(DataType dt,DRegister rd,DRegister rn,DRegister rm)4114   void vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4115     vcgt(al, dt, rd, rn, rm);
4116   }
4117 
4118   void vcgt(
4119       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vcgt(DataType dt,QRegister rd,QRegister rn,QRegister rm)4120   void vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4121     vcgt(al, dt, rd, rn, rm);
4122   }
4123 
4124   void vcle(Condition cond,
4125             DataType dt,
4126             DRegister rd,
4127             DRegister rm,
4128             const DOperand& operand);
vcle(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)4129   void vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
4130     vcle(al, dt, rd, rm, operand);
4131   }
4132 
4133   void vcle(Condition cond,
4134             DataType dt,
4135             QRegister rd,
4136             QRegister rm,
4137             const QOperand& operand);
vcle(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)4138   void vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
4139     vcle(al, dt, rd, rm, operand);
4140   }
4141 
4142   void vcle(
4143       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vcle(DataType dt,DRegister rd,DRegister rn,DRegister rm)4144   void vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4145     vcle(al, dt, rd, rn, rm);
4146   }
4147 
4148   void vcle(
4149       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vcle(DataType dt,QRegister rd,QRegister rn,QRegister rm)4150   void vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4151     vcle(al, dt, rd, rn, rm);
4152   }
4153 
4154   void vcls(Condition cond, DataType dt, DRegister rd, DRegister rm);
vcls(DataType dt,DRegister rd,DRegister rm)4155   void vcls(DataType dt, DRegister rd, DRegister rm) { vcls(al, dt, rd, rm); }
4156 
4157   void vcls(Condition cond, DataType dt, QRegister rd, QRegister rm);
vcls(DataType dt,QRegister rd,QRegister rm)4158   void vcls(DataType dt, QRegister rd, QRegister rm) { vcls(al, dt, rd, rm); }
4159 
4160   void vclt(Condition cond,
4161             DataType dt,
4162             DRegister rd,
4163             DRegister rm,
4164             const DOperand& operand);
vclt(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)4165   void vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
4166     vclt(al, dt, rd, rm, operand);
4167   }
4168 
4169   void vclt(Condition cond,
4170             DataType dt,
4171             QRegister rd,
4172             QRegister rm,
4173             const QOperand& operand);
vclt(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)4174   void vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
4175     vclt(al, dt, rd, rm, operand);
4176   }
4177 
4178   void vclt(
4179       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vclt(DataType dt,DRegister rd,DRegister rn,DRegister rm)4180   void vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4181     vclt(al, dt, rd, rn, rm);
4182   }
4183 
4184   void vclt(
4185       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vclt(DataType dt,QRegister rd,QRegister rn,QRegister rm)4186   void vclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4187     vclt(al, dt, rd, rn, rm);
4188   }
4189 
4190   void vclz(Condition cond, DataType dt, DRegister rd, DRegister rm);
vclz(DataType dt,DRegister rd,DRegister rm)4191   void vclz(DataType dt, DRegister rd, DRegister rm) { vclz(al, dt, rd, rm); }
4192 
4193   void vclz(Condition cond, DataType dt, QRegister rd, QRegister rm);
vclz(DataType dt,QRegister rd,QRegister rm)4194   void vclz(DataType dt, QRegister rd, QRegister rm) { vclz(al, dt, rd, rm); }
4195 
4196   void vcmp(Condition cond, DataType dt, SRegister rd, const SOperand& operand);
vcmp(DataType dt,SRegister rd,const SOperand & operand)4197   void vcmp(DataType dt, SRegister rd, const SOperand& operand) {
4198     vcmp(al, dt, rd, operand);
4199   }
4200 
4201   void vcmp(Condition cond, DataType dt, DRegister rd, const DOperand& operand);
vcmp(DataType dt,DRegister rd,const DOperand & operand)4202   void vcmp(DataType dt, DRegister rd, const DOperand& operand) {
4203     vcmp(al, dt, rd, operand);
4204   }
4205 
4206   void vcmpe(Condition cond,
4207              DataType dt,
4208              SRegister rd,
4209              const SOperand& operand);
vcmpe(DataType dt,SRegister rd,const SOperand & operand)4210   void vcmpe(DataType dt, SRegister rd, const SOperand& operand) {
4211     vcmpe(al, dt, rd, operand);
4212   }
4213 
4214   void vcmpe(Condition cond,
4215              DataType dt,
4216              DRegister rd,
4217              const DOperand& operand);
vcmpe(DataType dt,DRegister rd,const DOperand & operand)4218   void vcmpe(DataType dt, DRegister rd, const DOperand& operand) {
4219     vcmpe(al, dt, rd, operand);
4220   }
4221 
4222   void vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm);
vcnt(DataType dt,DRegister rd,DRegister rm)4223   void vcnt(DataType dt, DRegister rd, DRegister rm) { vcnt(al, dt, rd, rm); }
4224 
4225   void vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm);
vcnt(DataType dt,QRegister rd,QRegister rm)4226   void vcnt(DataType dt, QRegister rd, QRegister rm) { vcnt(al, dt, rd, rm); }
4227 
4228   void vcvt(
4229       Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
vcvt(DataType dt1,DataType dt2,DRegister rd,SRegister rm)4230   void vcvt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
4231     vcvt(al, dt1, dt2, rd, rm);
4232   }
4233 
4234   void vcvt(
4235       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
vcvt(DataType dt1,DataType dt2,SRegister rd,DRegister rm)4236   void vcvt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
4237     vcvt(al, dt1, dt2, rd, rm);
4238   }
4239 
4240   void vcvt(Condition cond,
4241             DataType dt1,
4242             DataType dt2,
4243             DRegister rd,
4244             DRegister rm,
4245             int32_t fbits);
vcvt(DataType dt1,DataType dt2,DRegister rd,DRegister rm,int32_t fbits)4246   void vcvt(
4247       DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) {
4248     vcvt(al, dt1, dt2, rd, rm, fbits);
4249   }
4250 
4251   void vcvt(Condition cond,
4252             DataType dt1,
4253             DataType dt2,
4254             QRegister rd,
4255             QRegister rm,
4256             int32_t fbits);
vcvt(DataType dt1,DataType dt2,QRegister rd,QRegister rm,int32_t fbits)4257   void vcvt(
4258       DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) {
4259     vcvt(al, dt1, dt2, rd, rm, fbits);
4260   }
4261 
4262   void vcvt(Condition cond,
4263             DataType dt1,
4264             DataType dt2,
4265             SRegister rd,
4266             SRegister rm,
4267             int32_t fbits);
vcvt(DataType dt1,DataType dt2,SRegister rd,SRegister rm,int32_t fbits)4268   void vcvt(
4269       DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) {
4270     vcvt(al, dt1, dt2, rd, rm, fbits);
4271   }
4272 
4273   void vcvt(
4274       Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm);
vcvt(DataType dt1,DataType dt2,DRegister rd,DRegister rm)4275   void vcvt(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
4276     vcvt(al, dt1, dt2, rd, rm);
4277   }
4278 
4279   void vcvt(
4280       Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm);
vcvt(DataType dt1,DataType dt2,QRegister rd,QRegister rm)4281   void vcvt(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
4282     vcvt(al, dt1, dt2, rd, rm);
4283   }
4284 
4285   void vcvt(
4286       Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm);
vcvt(DataType dt1,DataType dt2,DRegister rd,QRegister rm)4287   void vcvt(DataType dt1, DataType dt2, DRegister rd, QRegister rm) {
4288     vcvt(al, dt1, dt2, rd, rm);
4289   }
4290 
4291   void vcvt(
4292       Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm);
vcvt(DataType dt1,DataType dt2,QRegister rd,DRegister rm)4293   void vcvt(DataType dt1, DataType dt2, QRegister rd, DRegister rm) {
4294     vcvt(al, dt1, dt2, rd, rm);
4295   }
4296 
4297   void vcvt(
4298       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
vcvt(DataType dt1,DataType dt2,SRegister rd,SRegister rm)4299   void vcvt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
4300     vcvt(al, dt1, dt2, rd, rm);
4301   }
4302 
4303   void vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
4304 
4305   void vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
4306 
4307   void vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
4308 
4309   void vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
4310 
4311   void vcvtb(
4312       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
vcvtb(DataType dt1,DataType dt2,SRegister rd,SRegister rm)4313   void vcvtb(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
4314     vcvtb(al, dt1, dt2, rd, rm);
4315   }
4316 
4317   void vcvtb(
4318       Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
vcvtb(DataType dt1,DataType dt2,DRegister rd,SRegister rm)4319   void vcvtb(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
4320     vcvtb(al, dt1, dt2, rd, rm);
4321   }
4322 
4323   void vcvtb(
4324       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
vcvtb(DataType dt1,DataType dt2,SRegister rd,DRegister rm)4325   void vcvtb(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
4326     vcvtb(al, dt1, dt2, rd, rm);
4327   }
4328 
4329   void vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
4330 
4331   void vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
4332 
4333   void vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
4334 
4335   void vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
4336 
4337   void vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
4338 
4339   void vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
4340 
4341   void vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
4342 
4343   void vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
4344 
4345   void vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
4346 
4347   void vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
4348 
4349   void vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
4350 
4351   void vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
4352 
4353   void vcvtr(
4354       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
vcvtr(DataType dt1,DataType dt2,SRegister rd,SRegister rm)4355   void vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
4356     vcvtr(al, dt1, dt2, rd, rm);
4357   }
4358 
4359   void vcvtr(
4360       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
vcvtr(DataType dt1,DataType dt2,SRegister rd,DRegister rm)4361   void vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
4362     vcvtr(al, dt1, dt2, rd, rm);
4363   }
4364 
4365   void vcvtt(
4366       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
vcvtt(DataType dt1,DataType dt2,SRegister rd,SRegister rm)4367   void vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
4368     vcvtt(al, dt1, dt2, rd, rm);
4369   }
4370 
4371   void vcvtt(
4372       Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
vcvtt(DataType dt1,DataType dt2,DRegister rd,SRegister rm)4373   void vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
4374     vcvtt(al, dt1, dt2, rd, rm);
4375   }
4376 
4377   void vcvtt(
4378       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
vcvtt(DataType dt1,DataType dt2,SRegister rd,DRegister rm)4379   void vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
4380     vcvtt(al, dt1, dt2, rd, rm);
4381   }
4382 
4383   void vdiv(
4384       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vdiv(DataType dt,SRegister rd,SRegister rn,SRegister rm)4385   void vdiv(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
4386     vdiv(al, dt, rd, rn, rm);
4387   }
4388 
4389   void vdiv(
4390       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vdiv(DataType dt,DRegister rd,DRegister rn,DRegister rm)4391   void vdiv(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4392     vdiv(al, dt, rd, rn, rm);
4393   }
4394 
4395   void vdup(Condition cond, DataType dt, QRegister rd, Register rt);
vdup(DataType dt,QRegister rd,Register rt)4396   void vdup(DataType dt, QRegister rd, Register rt) { vdup(al, dt, rd, rt); }
4397 
4398   void vdup(Condition cond, DataType dt, DRegister rd, Register rt);
vdup(DataType dt,DRegister rd,Register rt)4399   void vdup(DataType dt, DRegister rd, Register rt) { vdup(al, dt, rd, rt); }
4400 
4401   void vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm);
vdup(DataType dt,DRegister rd,DRegisterLane rm)4402   void vdup(DataType dt, DRegister rd, DRegisterLane rm) {
4403     vdup(al, dt, rd, rm);
4404   }
4405 
4406   void vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm);
vdup(DataType dt,QRegister rd,DRegisterLane rm)4407   void vdup(DataType dt, QRegister rd, DRegisterLane rm) {
4408     vdup(al, dt, rd, rm);
4409   }
4410 
4411   void veor(
4412       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
veor(DataType dt,DRegister rd,DRegister rn,DRegister rm)4413   void veor(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4414     veor(al, dt, rd, rn, rm);
4415   }
veor(DRegister rd,DRegister rn,DRegister rm)4416   void veor(DRegister rd, DRegister rn, DRegister rm) {
4417     veor(al, kDataTypeValueNone, rd, rn, rm);
4418   }
veor(Condition cond,DRegister rd,DRegister rn,DRegister rm)4419   void veor(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
4420     veor(cond, kDataTypeValueNone, rd, rn, rm);
4421   }
4422 
4423   void veor(
4424       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
veor(DataType dt,QRegister rd,QRegister rn,QRegister rm)4425   void veor(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4426     veor(al, dt, rd, rn, rm);
4427   }
veor(QRegister rd,QRegister rn,QRegister rm)4428   void veor(QRegister rd, QRegister rn, QRegister rm) {
4429     veor(al, kDataTypeValueNone, rd, rn, rm);
4430   }
veor(Condition cond,QRegister rd,QRegister rn,QRegister rm)4431   void veor(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
4432     veor(cond, kDataTypeValueNone, rd, rn, rm);
4433   }
4434 
4435   void vext(Condition cond,
4436             DataType dt,
4437             DRegister rd,
4438             DRegister rn,
4439             DRegister rm,
4440             const DOperand& operand);
vext(DataType dt,DRegister rd,DRegister rn,DRegister rm,const DOperand & operand)4441   void vext(DataType dt,
4442             DRegister rd,
4443             DRegister rn,
4444             DRegister rm,
4445             const DOperand& operand) {
4446     vext(al, dt, rd, rn, rm, operand);
4447   }
4448 
4449   void vext(Condition cond,
4450             DataType dt,
4451             QRegister rd,
4452             QRegister rn,
4453             QRegister rm,
4454             const QOperand& operand);
vext(DataType dt,QRegister rd,QRegister rn,QRegister rm,const QOperand & operand)4455   void vext(DataType dt,
4456             QRegister rd,
4457             QRegister rn,
4458             QRegister rm,
4459             const QOperand& operand) {
4460     vext(al, dt, rd, rn, rm, operand);
4461   }
4462 
4463   void vfma(
4464       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vfma(DataType dt,DRegister rd,DRegister rn,DRegister rm)4465   void vfma(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4466     vfma(al, dt, rd, rn, rm);
4467   }
4468 
4469   void vfma(
4470       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vfma(DataType dt,QRegister rd,QRegister rn,QRegister rm)4471   void vfma(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4472     vfma(al, dt, rd, rn, rm);
4473   }
4474 
4475   void vfma(
4476       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vfma(DataType dt,SRegister rd,SRegister rn,SRegister rm)4477   void vfma(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
4478     vfma(al, dt, rd, rn, rm);
4479   }
4480 
4481   void vfms(
4482       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vfms(DataType dt,DRegister rd,DRegister rn,DRegister rm)4483   void vfms(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4484     vfms(al, dt, rd, rn, rm);
4485   }
4486 
4487   void vfms(
4488       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vfms(DataType dt,QRegister rd,QRegister rn,QRegister rm)4489   void vfms(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4490     vfms(al, dt, rd, rn, rm);
4491   }
4492 
4493   void vfms(
4494       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vfms(DataType dt,SRegister rd,SRegister rn,SRegister rm)4495   void vfms(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
4496     vfms(al, dt, rd, rn, rm);
4497   }
4498 
4499   void vfnma(
4500       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vfnma(DataType dt,SRegister rd,SRegister rn,SRegister rm)4501   void vfnma(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
4502     vfnma(al, dt, rd, rn, rm);
4503   }
4504 
4505   void vfnma(
4506       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vfnma(DataType dt,DRegister rd,DRegister rn,DRegister rm)4507   void vfnma(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4508     vfnma(al, dt, rd, rn, rm);
4509   }
4510 
4511   void vfnms(
4512       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vfnms(DataType dt,SRegister rd,SRegister rn,SRegister rm)4513   void vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
4514     vfnms(al, dt, rd, rn, rm);
4515   }
4516 
4517   void vfnms(
4518       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vfnms(DataType dt,DRegister rd,DRegister rn,DRegister rm)4519   void vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4520     vfnms(al, dt, rd, rn, rm);
4521   }
4522 
4523   void vhadd(
4524       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vhadd(DataType dt,DRegister rd,DRegister rn,DRegister rm)4525   void vhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4526     vhadd(al, dt, rd, rn, rm);
4527   }
4528 
4529   void vhadd(
4530       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vhadd(DataType dt,QRegister rd,QRegister rn,QRegister rm)4531   void vhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4532     vhadd(al, dt, rd, rn, rm);
4533   }
4534 
4535   void vhsub(
4536       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vhsub(DataType dt,DRegister rd,DRegister rn,DRegister rm)4537   void vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4538     vhsub(al, dt, rd, rn, rm);
4539   }
4540 
4541   void vhsub(
4542       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vhsub(DataType dt,QRegister rd,QRegister rn,QRegister rm)4543   void vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4544     vhsub(al, dt, rd, rn, rm);
4545   }
4546 
4547   void vld1(Condition cond,
4548             DataType dt,
4549             const NeonRegisterList& nreglist,
4550             const AlignedMemOperand& operand);
vld1(DataType dt,const NeonRegisterList & nreglist,const AlignedMemOperand & operand)4551   void vld1(DataType dt,
4552             const NeonRegisterList& nreglist,
4553             const AlignedMemOperand& operand) {
4554     vld1(al, dt, nreglist, operand);
4555   }
4556 
4557   void vld2(Condition cond,
4558             DataType dt,
4559             const NeonRegisterList& nreglist,
4560             const AlignedMemOperand& operand);
vld2(DataType dt,const NeonRegisterList & nreglist,const AlignedMemOperand & operand)4561   void vld2(DataType dt,
4562             const NeonRegisterList& nreglist,
4563             const AlignedMemOperand& operand) {
4564     vld2(al, dt, nreglist, operand);
4565   }
4566 
4567   void vld3(Condition cond,
4568             DataType dt,
4569             const NeonRegisterList& nreglist,
4570             const AlignedMemOperand& operand);
vld3(DataType dt,const NeonRegisterList & nreglist,const AlignedMemOperand & operand)4571   void vld3(DataType dt,
4572             const NeonRegisterList& nreglist,
4573             const AlignedMemOperand& operand) {
4574     vld3(al, dt, nreglist, operand);
4575   }
4576 
4577   void vld3(Condition cond,
4578             DataType dt,
4579             const NeonRegisterList& nreglist,
4580             const MemOperand& operand);
vld3(DataType dt,const NeonRegisterList & nreglist,const MemOperand & operand)4581   void vld3(DataType dt,
4582             const NeonRegisterList& nreglist,
4583             const MemOperand& operand) {
4584     vld3(al, dt, nreglist, operand);
4585   }
4586 
4587   void vld4(Condition cond,
4588             DataType dt,
4589             const NeonRegisterList& nreglist,
4590             const AlignedMemOperand& operand);
vld4(DataType dt,const NeonRegisterList & nreglist,const AlignedMemOperand & operand)4591   void vld4(DataType dt,
4592             const NeonRegisterList& nreglist,
4593             const AlignedMemOperand& operand) {
4594     vld4(al, dt, nreglist, operand);
4595   }
4596 
4597   void vldm(Condition cond,
4598             DataType dt,
4599             Register rn,
4600             WriteBack write_back,
4601             DRegisterList dreglist);
vldm(DataType dt,Register rn,WriteBack write_back,DRegisterList dreglist)4602   void vldm(DataType dt,
4603             Register rn,
4604             WriteBack write_back,
4605             DRegisterList dreglist) {
4606     vldm(al, dt, rn, write_back, dreglist);
4607   }
vldm(Register rn,WriteBack write_back,DRegisterList dreglist)4608   void vldm(Register rn, WriteBack write_back, DRegisterList dreglist) {
4609     vldm(al, kDataTypeValueNone, rn, write_back, dreglist);
4610   }
vldm(Condition cond,Register rn,WriteBack write_back,DRegisterList dreglist)4611   void vldm(Condition cond,
4612             Register rn,
4613             WriteBack write_back,
4614             DRegisterList dreglist) {
4615     vldm(cond, kDataTypeValueNone, rn, write_back, dreglist);
4616   }
4617 
4618   void vldm(Condition cond,
4619             DataType dt,
4620             Register rn,
4621             WriteBack write_back,
4622             SRegisterList sreglist);
vldm(DataType dt,Register rn,WriteBack write_back,SRegisterList sreglist)4623   void vldm(DataType dt,
4624             Register rn,
4625             WriteBack write_back,
4626             SRegisterList sreglist) {
4627     vldm(al, dt, rn, write_back, sreglist);
4628   }
vldm(Register rn,WriteBack write_back,SRegisterList sreglist)4629   void vldm(Register rn, WriteBack write_back, SRegisterList sreglist) {
4630     vldm(al, kDataTypeValueNone, rn, write_back, sreglist);
4631   }
vldm(Condition cond,Register rn,WriteBack write_back,SRegisterList sreglist)4632   void vldm(Condition cond,
4633             Register rn,
4634             WriteBack write_back,
4635             SRegisterList sreglist) {
4636     vldm(cond, kDataTypeValueNone, rn, write_back, sreglist);
4637   }
4638 
4639   void vldmdb(Condition cond,
4640               DataType dt,
4641               Register rn,
4642               WriteBack write_back,
4643               DRegisterList dreglist);
vldmdb(DataType dt,Register rn,WriteBack write_back,DRegisterList dreglist)4644   void vldmdb(DataType dt,
4645               Register rn,
4646               WriteBack write_back,
4647               DRegisterList dreglist) {
4648     vldmdb(al, dt, rn, write_back, dreglist);
4649   }
vldmdb(Register rn,WriteBack write_back,DRegisterList dreglist)4650   void vldmdb(Register rn, WriteBack write_back, DRegisterList dreglist) {
4651     vldmdb(al, kDataTypeValueNone, rn, write_back, dreglist);
4652   }
vldmdb(Condition cond,Register rn,WriteBack write_back,DRegisterList dreglist)4653   void vldmdb(Condition cond,
4654               Register rn,
4655               WriteBack write_back,
4656               DRegisterList dreglist) {
4657     vldmdb(cond, kDataTypeValueNone, rn, write_back, dreglist);
4658   }
4659 
4660   void vldmdb(Condition cond,
4661               DataType dt,
4662               Register rn,
4663               WriteBack write_back,
4664               SRegisterList sreglist);
vldmdb(DataType dt,Register rn,WriteBack write_back,SRegisterList sreglist)4665   void vldmdb(DataType dt,
4666               Register rn,
4667               WriteBack write_back,
4668               SRegisterList sreglist) {
4669     vldmdb(al, dt, rn, write_back, sreglist);
4670   }
vldmdb(Register rn,WriteBack write_back,SRegisterList sreglist)4671   void vldmdb(Register rn, WriteBack write_back, SRegisterList sreglist) {
4672     vldmdb(al, kDataTypeValueNone, rn, write_back, sreglist);
4673   }
vldmdb(Condition cond,Register rn,WriteBack write_back,SRegisterList sreglist)4674   void vldmdb(Condition cond,
4675               Register rn,
4676               WriteBack write_back,
4677               SRegisterList sreglist) {
4678     vldmdb(cond, kDataTypeValueNone, rn, write_back, sreglist);
4679   }
4680 
4681   void vldmia(Condition cond,
4682               DataType dt,
4683               Register rn,
4684               WriteBack write_back,
4685               DRegisterList dreglist);
vldmia(DataType dt,Register rn,WriteBack write_back,DRegisterList dreglist)4686   void vldmia(DataType dt,
4687               Register rn,
4688               WriteBack write_back,
4689               DRegisterList dreglist) {
4690     vldmia(al, dt, rn, write_back, dreglist);
4691   }
vldmia(Register rn,WriteBack write_back,DRegisterList dreglist)4692   void vldmia(Register rn, WriteBack write_back, DRegisterList dreglist) {
4693     vldmia(al, kDataTypeValueNone, rn, write_back, dreglist);
4694   }
vldmia(Condition cond,Register rn,WriteBack write_back,DRegisterList dreglist)4695   void vldmia(Condition cond,
4696               Register rn,
4697               WriteBack write_back,
4698               DRegisterList dreglist) {
4699     vldmia(cond, kDataTypeValueNone, rn, write_back, dreglist);
4700   }
4701 
4702   void vldmia(Condition cond,
4703               DataType dt,
4704               Register rn,
4705               WriteBack write_back,
4706               SRegisterList sreglist);
vldmia(DataType dt,Register rn,WriteBack write_back,SRegisterList sreglist)4707   void vldmia(DataType dt,
4708               Register rn,
4709               WriteBack write_back,
4710               SRegisterList sreglist) {
4711     vldmia(al, dt, rn, write_back, sreglist);
4712   }
vldmia(Register rn,WriteBack write_back,SRegisterList sreglist)4713   void vldmia(Register rn, WriteBack write_back, SRegisterList sreglist) {
4714     vldmia(al, kDataTypeValueNone, rn, write_back, sreglist);
4715   }
vldmia(Condition cond,Register rn,WriteBack write_back,SRegisterList sreglist)4716   void vldmia(Condition cond,
4717               Register rn,
4718               WriteBack write_back,
4719               SRegisterList sreglist) {
4720     vldmia(cond, kDataTypeValueNone, rn, write_back, sreglist);
4721   }
4722 
4723   void vldr(Condition cond, DataType dt, DRegister rd, Location* location);
4724   bool vldr_info(Condition cond,
4725                  DataType dt,
4726                  DRegister rd,
4727                  Location* location,
4728                  const struct ReferenceInfo** info);
vldr(DataType dt,DRegister rd,Location * location)4729   void vldr(DataType dt, DRegister rd, Location* location) {
4730     vldr(al, dt, rd, location);
4731   }
vldr(DRegister rd,Location * location)4732   void vldr(DRegister rd, Location* location) {
4733     vldr(al, Untyped64, rd, location);
4734   }
vldr(Condition cond,DRegister rd,Location * location)4735   void vldr(Condition cond, DRegister rd, Location* location) {
4736     vldr(cond, Untyped64, rd, location);
4737   }
4738 
4739   void vldr(Condition cond,
4740             DataType dt,
4741             DRegister rd,
4742             const MemOperand& operand);
vldr(DataType dt,DRegister rd,const MemOperand & operand)4743   void vldr(DataType dt, DRegister rd, const MemOperand& operand) {
4744     vldr(al, dt, rd, operand);
4745   }
vldr(DRegister rd,const MemOperand & operand)4746   void vldr(DRegister rd, const MemOperand& operand) {
4747     vldr(al, Untyped64, rd, operand);
4748   }
vldr(Condition cond,DRegister rd,const MemOperand & operand)4749   void vldr(Condition cond, DRegister rd, const MemOperand& operand) {
4750     vldr(cond, Untyped64, rd, operand);
4751   }
4752 
4753   void vldr(Condition cond, DataType dt, SRegister rd, Location* location);
4754   bool vldr_info(Condition cond,
4755                  DataType dt,
4756                  SRegister rd,
4757                  Location* location,
4758                  const struct ReferenceInfo** info);
vldr(DataType dt,SRegister rd,Location * location)4759   void vldr(DataType dt, SRegister rd, Location* location) {
4760     vldr(al, dt, rd, location);
4761   }
vldr(SRegister rd,Location * location)4762   void vldr(SRegister rd, Location* location) {
4763     vldr(al, Untyped32, rd, location);
4764   }
vldr(Condition cond,SRegister rd,Location * location)4765   void vldr(Condition cond, SRegister rd, Location* location) {
4766     vldr(cond, Untyped32, rd, location);
4767   }
4768 
4769   void vldr(Condition cond,
4770             DataType dt,
4771             SRegister rd,
4772             const MemOperand& operand);
vldr(DataType dt,SRegister rd,const MemOperand & operand)4773   void vldr(DataType dt, SRegister rd, const MemOperand& operand) {
4774     vldr(al, dt, rd, operand);
4775   }
vldr(SRegister rd,const MemOperand & operand)4776   void vldr(SRegister rd, const MemOperand& operand) {
4777     vldr(al, Untyped32, rd, operand);
4778   }
vldr(Condition cond,SRegister rd,const MemOperand & operand)4779   void vldr(Condition cond, SRegister rd, const MemOperand& operand) {
4780     vldr(cond, Untyped32, rd, operand);
4781   }
4782 
4783   void vmax(
4784       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vmax(DataType dt,DRegister rd,DRegister rn,DRegister rm)4785   void vmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4786     vmax(al, dt, rd, rn, rm);
4787   }
4788 
4789   void vmax(
4790       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vmax(DataType dt,QRegister rd,QRegister rn,QRegister rm)4791   void vmax(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4792     vmax(al, dt, rd, rn, rm);
4793   }
4794 
4795   void vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm);
4796 
4797   void vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm);
4798 
4799   void vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm);
4800 
4801   void vmin(
4802       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vmin(DataType dt,DRegister rd,DRegister rn,DRegister rm)4803   void vmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4804     vmin(al, dt, rd, rn, rm);
4805   }
4806 
4807   void vmin(
4808       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vmin(DataType dt,QRegister rd,QRegister rn,QRegister rm)4809   void vmin(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4810     vmin(al, dt, rd, rn, rm);
4811   }
4812 
4813   void vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm);
4814 
4815   void vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm);
4816 
4817   void vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm);
4818 
4819   void vmla(Condition cond,
4820             DataType dt,
4821             DRegister rd,
4822             DRegister rn,
4823             DRegisterLane rm);
vmla(DataType dt,DRegister rd,DRegister rn,DRegisterLane rm)4824   void vmla(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
4825     vmla(al, dt, rd, rn, rm);
4826   }
4827 
4828   void vmla(Condition cond,
4829             DataType dt,
4830             QRegister rd,
4831             QRegister rn,
4832             DRegisterLane rm);
vmla(DataType dt,QRegister rd,QRegister rn,DRegisterLane rm)4833   void vmla(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
4834     vmla(al, dt, rd, rn, rm);
4835   }
4836 
4837   void vmla(
4838       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vmla(DataType dt,DRegister rd,DRegister rn,DRegister rm)4839   void vmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4840     vmla(al, dt, rd, rn, rm);
4841   }
4842 
4843   void vmla(
4844       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vmla(DataType dt,QRegister rd,QRegister rn,QRegister rm)4845   void vmla(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4846     vmla(al, dt, rd, rn, rm);
4847   }
4848 
4849   void vmla(
4850       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vmla(DataType dt,SRegister rd,SRegister rn,SRegister rm)4851   void vmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
4852     vmla(al, dt, rd, rn, rm);
4853   }
4854 
4855   void vmlal(Condition cond,
4856              DataType dt,
4857              QRegister rd,
4858              DRegister rn,
4859              DRegisterLane rm);
vmlal(DataType dt,QRegister rd,DRegister rn,DRegisterLane rm)4860   void vmlal(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
4861     vmlal(al, dt, rd, rn, rm);
4862   }
4863 
4864   void vmlal(
4865       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
vmlal(DataType dt,QRegister rd,DRegister rn,DRegister rm)4866   void vmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
4867     vmlal(al, dt, rd, rn, rm);
4868   }
4869 
4870   void vmls(Condition cond,
4871             DataType dt,
4872             DRegister rd,
4873             DRegister rn,
4874             DRegisterLane rm);
vmls(DataType dt,DRegister rd,DRegister rn,DRegisterLane rm)4875   void vmls(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
4876     vmls(al, dt, rd, rn, rm);
4877   }
4878 
4879   void vmls(Condition cond,
4880             DataType dt,
4881             QRegister rd,
4882             QRegister rn,
4883             DRegisterLane rm);
vmls(DataType dt,QRegister rd,QRegister rn,DRegisterLane rm)4884   void vmls(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
4885     vmls(al, dt, rd, rn, rm);
4886   }
4887 
4888   void vmls(
4889       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vmls(DataType dt,DRegister rd,DRegister rn,DRegister rm)4890   void vmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
4891     vmls(al, dt, rd, rn, rm);
4892   }
4893 
4894   void vmls(
4895       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vmls(DataType dt,QRegister rd,QRegister rn,QRegister rm)4896   void vmls(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
4897     vmls(al, dt, rd, rn, rm);
4898   }
4899 
4900   void vmls(
4901       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vmls(DataType dt,SRegister rd,SRegister rn,SRegister rm)4902   void vmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
4903     vmls(al, dt, rd, rn, rm);
4904   }
4905 
4906   void vmlsl(Condition cond,
4907              DataType dt,
4908              QRegister rd,
4909              DRegister rn,
4910              DRegisterLane rm);
vmlsl(DataType dt,QRegister rd,DRegister rn,DRegisterLane rm)4911   void vmlsl(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
4912     vmlsl(al, dt, rd, rn, rm);
4913   }
4914 
4915   void vmlsl(
4916       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
vmlsl(DataType dt,QRegister rd,DRegister rn,DRegister rm)4917   void vmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
4918     vmlsl(al, dt, rd, rn, rm);
4919   }
4920 
4921   void vmov(Condition cond, Register rt, SRegister rn);
vmov(Register rt,SRegister rn)4922   void vmov(Register rt, SRegister rn) { vmov(al, rt, rn); }
4923 
4924   void vmov(Condition cond, SRegister rn, Register rt);
vmov(SRegister rn,Register rt)4925   void vmov(SRegister rn, Register rt) { vmov(al, rn, rt); }
4926 
4927   void vmov(Condition cond, Register rt, Register rt2, DRegister rm);
vmov(Register rt,Register rt2,DRegister rm)4928   void vmov(Register rt, Register rt2, DRegister rm) { vmov(al, rt, rt2, rm); }
4929 
4930   void vmov(Condition cond, DRegister rm, Register rt, Register rt2);
vmov(DRegister rm,Register rt,Register rt2)4931   void vmov(DRegister rm, Register rt, Register rt2) { vmov(al, rm, rt, rt2); }
4932 
4933   void vmov(
4934       Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1);
vmov(Register rt,Register rt2,SRegister rm,SRegister rm1)4935   void vmov(Register rt, Register rt2, SRegister rm, SRegister rm1) {
4936     vmov(al, rt, rt2, rm, rm1);
4937   }
4938 
4939   void vmov(
4940       Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2);
vmov(SRegister rm,SRegister rm1,Register rt,Register rt2)4941   void vmov(SRegister rm, SRegister rm1, Register rt, Register rt2) {
4942     vmov(al, rm, rm1, rt, rt2);
4943   }
4944 
4945   void vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt);
vmov(DataType dt,DRegisterLane rd,Register rt)4946   void vmov(DataType dt, DRegisterLane rd, Register rt) {
4947     vmov(al, dt, rd, rt);
4948   }
vmov(DRegisterLane rd,Register rt)4949   void vmov(DRegisterLane rd, Register rt) {
4950     vmov(al, kDataTypeValueNone, rd, rt);
4951   }
vmov(Condition cond,DRegisterLane rd,Register rt)4952   void vmov(Condition cond, DRegisterLane rd, Register rt) {
4953     vmov(cond, kDataTypeValueNone, rd, rt);
4954   }
4955 
4956   void vmov(Condition cond, DataType dt, DRegister rd, const DOperand& operand);
vmov(DataType dt,DRegister rd,const DOperand & operand)4957   void vmov(DataType dt, DRegister rd, const DOperand& operand) {
4958     vmov(al, dt, rd, operand);
4959   }
4960 
4961   void vmov(Condition cond, DataType dt, QRegister rd, const QOperand& operand);
vmov(DataType dt,QRegister rd,const QOperand & operand)4962   void vmov(DataType dt, QRegister rd, const QOperand& operand) {
4963     vmov(al, dt, rd, operand);
4964   }
4965 
4966   void vmov(Condition cond, DataType dt, SRegister rd, const SOperand& operand);
vmov(DataType dt,SRegister rd,const SOperand & operand)4967   void vmov(DataType dt, SRegister rd, const SOperand& operand) {
4968     vmov(al, dt, rd, operand);
4969   }
4970 
4971   void vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn);
vmov(DataType dt,Register rt,DRegisterLane rn)4972   void vmov(DataType dt, Register rt, DRegisterLane rn) {
4973     vmov(al, dt, rt, rn);
4974   }
vmov(Register rt,DRegisterLane rn)4975   void vmov(Register rt, DRegisterLane rn) {
4976     vmov(al, kDataTypeValueNone, rt, rn);
4977   }
vmov(Condition cond,Register rt,DRegisterLane rn)4978   void vmov(Condition cond, Register rt, DRegisterLane rn) {
4979     vmov(cond, kDataTypeValueNone, rt, rn);
4980   }
4981 
4982   void vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm);
vmovl(DataType dt,QRegister rd,DRegister rm)4983   void vmovl(DataType dt, QRegister rd, DRegister rm) { vmovl(al, dt, rd, rm); }
4984 
4985   void vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm);
vmovn(DataType dt,DRegister rd,QRegister rm)4986   void vmovn(DataType dt, DRegister rd, QRegister rm) { vmovn(al, dt, rd, rm); }
4987 
4988   void vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg);
vmrs(RegisterOrAPSR_nzcv rt,SpecialFPRegister spec_reg)4989   void vmrs(RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) {
4990     vmrs(al, rt, spec_reg);
4991   }
4992 
4993   void vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt);
vmsr(SpecialFPRegister spec_reg,Register rt)4994   void vmsr(SpecialFPRegister spec_reg, Register rt) { vmsr(al, spec_reg, rt); }
4995 
4996   void vmul(Condition cond,
4997             DataType dt,
4998             DRegister rd,
4999             DRegister rn,
5000             DRegister dm,
5001             unsigned index);
vmul(DataType dt,DRegister rd,DRegister rn,DRegister dm,unsigned index)5002   void vmul(
5003       DataType dt, DRegister rd, DRegister rn, DRegister dm, unsigned index) {
5004     vmul(al, dt, rd, rn, dm, index);
5005   }
5006 
5007   void vmul(Condition cond,
5008             DataType dt,
5009             QRegister rd,
5010             QRegister rn,
5011             DRegister dm,
5012             unsigned index);
vmul(DataType dt,QRegister rd,QRegister rn,DRegister dm,unsigned index)5013   void vmul(
5014       DataType dt, QRegister rd, QRegister rn, DRegister dm, unsigned index) {
5015     vmul(al, dt, rd, rn, dm, index);
5016   }
5017 
5018   void vmul(
5019       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vmul(DataType dt,DRegister rd,DRegister rn,DRegister rm)5020   void vmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5021     vmul(al, dt, rd, rn, rm);
5022   }
5023 
5024   void vmul(
5025       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vmul(DataType dt,QRegister rd,QRegister rn,QRegister rm)5026   void vmul(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5027     vmul(al, dt, rd, rn, rm);
5028   }
5029 
5030   void vmul(
5031       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vmul(DataType dt,SRegister rd,SRegister rn,SRegister rm)5032   void vmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5033     vmul(al, dt, rd, rn, rm);
5034   }
5035 
5036   void vmull(Condition cond,
5037              DataType dt,
5038              QRegister rd,
5039              DRegister rn,
5040              DRegister dm,
5041              unsigned index);
vmull(DataType dt,QRegister rd,DRegister rn,DRegister dm,unsigned index)5042   void vmull(
5043       DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
5044     vmull(al, dt, rd, rn, dm, index);
5045   }
5046 
5047   void vmull(
5048       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
vmull(DataType dt,QRegister rd,DRegister rn,DRegister rm)5049   void vmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
5050     vmull(al, dt, rd, rn, rm);
5051   }
5052 
5053   void vmvn(Condition cond, DataType dt, DRegister rd, const DOperand& operand);
vmvn(DataType dt,DRegister rd,const DOperand & operand)5054   void vmvn(DataType dt, DRegister rd, const DOperand& operand) {
5055     vmvn(al, dt, rd, operand);
5056   }
5057 
5058   void vmvn(Condition cond, DataType dt, QRegister rd, const QOperand& operand);
vmvn(DataType dt,QRegister rd,const QOperand & operand)5059   void vmvn(DataType dt, QRegister rd, const QOperand& operand) {
5060     vmvn(al, dt, rd, operand);
5061   }
5062 
5063   void vneg(Condition cond, DataType dt, DRegister rd, DRegister rm);
vneg(DataType dt,DRegister rd,DRegister rm)5064   void vneg(DataType dt, DRegister rd, DRegister rm) { vneg(al, dt, rd, rm); }
5065 
5066   void vneg(Condition cond, DataType dt, QRegister rd, QRegister rm);
vneg(DataType dt,QRegister rd,QRegister rm)5067   void vneg(DataType dt, QRegister rd, QRegister rm) { vneg(al, dt, rd, rm); }
5068 
5069   void vneg(Condition cond, DataType dt, SRegister rd, SRegister rm);
vneg(DataType dt,SRegister rd,SRegister rm)5070   void vneg(DataType dt, SRegister rd, SRegister rm) { vneg(al, dt, rd, rm); }
5071 
5072   void vnmla(
5073       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vnmla(DataType dt,SRegister rd,SRegister rn,SRegister rm)5074   void vnmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5075     vnmla(al, dt, rd, rn, rm);
5076   }
5077 
5078   void vnmla(
5079       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vnmla(DataType dt,DRegister rd,DRegister rn,DRegister rm)5080   void vnmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5081     vnmla(al, dt, rd, rn, rm);
5082   }
5083 
5084   void vnmls(
5085       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vnmls(DataType dt,SRegister rd,SRegister rn,SRegister rm)5086   void vnmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5087     vnmls(al, dt, rd, rn, rm);
5088   }
5089 
5090   void vnmls(
5091       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vnmls(DataType dt,DRegister rd,DRegister rn,DRegister rm)5092   void vnmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5093     vnmls(al, dt, rd, rn, rm);
5094   }
5095 
5096   void vnmul(
5097       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vnmul(DataType dt,SRegister rd,SRegister rn,SRegister rm)5098   void vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5099     vnmul(al, dt, rd, rn, rm);
5100   }
5101 
5102   void vnmul(
5103       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vnmul(DataType dt,DRegister rd,DRegister rn,DRegister rm)5104   void vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5105     vnmul(al, dt, rd, rn, rm);
5106   }
5107 
5108   void vorn(Condition cond,
5109             DataType dt,
5110             DRegister rd,
5111             DRegister rn,
5112             const DOperand& operand);
vorn(DataType dt,DRegister rd,DRegister rn,const DOperand & operand)5113   void vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
5114     vorn(al, dt, rd, rn, operand);
5115   }
5116 
5117   void vorn(Condition cond,
5118             DataType dt,
5119             QRegister rd,
5120             QRegister rn,
5121             const QOperand& operand);
vorn(DataType dt,QRegister rd,QRegister rn,const QOperand & operand)5122   void vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
5123     vorn(al, dt, rd, rn, operand);
5124   }
5125 
5126   void vorr(Condition cond,
5127             DataType dt,
5128             DRegister rd,
5129             DRegister rn,
5130             const DOperand& operand);
vorr(DataType dt,DRegister rd,DRegister rn,const DOperand & operand)5131   void vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
5132     vorr(al, dt, rd, rn, operand);
5133   }
vorr(DRegister rd,DRegister rn,const DOperand & operand)5134   void vorr(DRegister rd, DRegister rn, const DOperand& operand) {
5135     vorr(al, kDataTypeValueNone, rd, rn, operand);
5136   }
vorr(Condition cond,DRegister rd,DRegister rn,const DOperand & operand)5137   void vorr(Condition cond,
5138             DRegister rd,
5139             DRegister rn,
5140             const DOperand& operand) {
5141     vorr(cond, kDataTypeValueNone, rd, rn, operand);
5142   }
5143 
5144   void vorr(Condition cond,
5145             DataType dt,
5146             QRegister rd,
5147             QRegister rn,
5148             const QOperand& operand);
vorr(DataType dt,QRegister rd,QRegister rn,const QOperand & operand)5149   void vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
5150     vorr(al, dt, rd, rn, operand);
5151   }
vorr(QRegister rd,QRegister rn,const QOperand & operand)5152   void vorr(QRegister rd, QRegister rn, const QOperand& operand) {
5153     vorr(al, kDataTypeValueNone, rd, rn, operand);
5154   }
vorr(Condition cond,QRegister rd,QRegister rn,const QOperand & operand)5155   void vorr(Condition cond,
5156             QRegister rd,
5157             QRegister rn,
5158             const QOperand& operand) {
5159     vorr(cond, kDataTypeValueNone, rd, rn, operand);
5160   }
5161 
5162   void vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm);
vpadal(DataType dt,DRegister rd,DRegister rm)5163   void vpadal(DataType dt, DRegister rd, DRegister rm) {
5164     vpadal(al, dt, rd, rm);
5165   }
5166 
5167   void vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm);
vpadal(DataType dt,QRegister rd,QRegister rm)5168   void vpadal(DataType dt, QRegister rd, QRegister rm) {
5169     vpadal(al, dt, rd, rm);
5170   }
5171 
5172   void vpadd(
5173       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vpadd(DataType dt,DRegister rd,DRegister rn,DRegister rm)5174   void vpadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5175     vpadd(al, dt, rd, rn, rm);
5176   }
5177 
5178   void vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm);
vpaddl(DataType dt,DRegister rd,DRegister rm)5179   void vpaddl(DataType dt, DRegister rd, DRegister rm) {
5180     vpaddl(al, dt, rd, rm);
5181   }
5182 
5183   void vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm);
vpaddl(DataType dt,QRegister rd,QRegister rm)5184   void vpaddl(DataType dt, QRegister rd, QRegister rm) {
5185     vpaddl(al, dt, rd, rm);
5186   }
5187 
5188   void vpmax(
5189       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vpmax(DataType dt,DRegister rd,DRegister rn,DRegister rm)5190   void vpmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5191     vpmax(al, dt, rd, rn, rm);
5192   }
5193 
5194   void vpmin(
5195       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vpmin(DataType dt,DRegister rd,DRegister rn,DRegister rm)5196   void vpmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5197     vpmin(al, dt, rd, rn, rm);
5198   }
5199 
5200   void vpop(Condition cond, DataType dt, DRegisterList dreglist);
vpop(DataType dt,DRegisterList dreglist)5201   void vpop(DataType dt, DRegisterList dreglist) { vpop(al, dt, dreglist); }
vpop(DRegisterList dreglist)5202   void vpop(DRegisterList dreglist) { vpop(al, kDataTypeValueNone, dreglist); }
vpop(Condition cond,DRegisterList dreglist)5203   void vpop(Condition cond, DRegisterList dreglist) {
5204     vpop(cond, kDataTypeValueNone, dreglist);
5205   }
5206 
5207   void vpop(Condition cond, DataType dt, SRegisterList sreglist);
vpop(DataType dt,SRegisterList sreglist)5208   void vpop(DataType dt, SRegisterList sreglist) { vpop(al, dt, sreglist); }
vpop(SRegisterList sreglist)5209   void vpop(SRegisterList sreglist) { vpop(al, kDataTypeValueNone, sreglist); }
vpop(Condition cond,SRegisterList sreglist)5210   void vpop(Condition cond, SRegisterList sreglist) {
5211     vpop(cond, kDataTypeValueNone, sreglist);
5212   }
5213 
5214   void vpush(Condition cond, DataType dt, DRegisterList dreglist);
vpush(DataType dt,DRegisterList dreglist)5215   void vpush(DataType dt, DRegisterList dreglist) { vpush(al, dt, dreglist); }
vpush(DRegisterList dreglist)5216   void vpush(DRegisterList dreglist) {
5217     vpush(al, kDataTypeValueNone, dreglist);
5218   }
vpush(Condition cond,DRegisterList dreglist)5219   void vpush(Condition cond, DRegisterList dreglist) {
5220     vpush(cond, kDataTypeValueNone, dreglist);
5221   }
5222 
5223   void vpush(Condition cond, DataType dt, SRegisterList sreglist);
vpush(DataType dt,SRegisterList sreglist)5224   void vpush(DataType dt, SRegisterList sreglist) { vpush(al, dt, sreglist); }
vpush(SRegisterList sreglist)5225   void vpush(SRegisterList sreglist) {
5226     vpush(al, kDataTypeValueNone, sreglist);
5227   }
vpush(Condition cond,SRegisterList sreglist)5228   void vpush(Condition cond, SRegisterList sreglist) {
5229     vpush(cond, kDataTypeValueNone, sreglist);
5230   }
5231 
5232   void vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm);
vqabs(DataType dt,DRegister rd,DRegister rm)5233   void vqabs(DataType dt, DRegister rd, DRegister rm) { vqabs(al, dt, rd, rm); }
5234 
5235   void vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm);
vqabs(DataType dt,QRegister rd,QRegister rm)5236   void vqabs(DataType dt, QRegister rd, QRegister rm) { vqabs(al, dt, rd, rm); }
5237 
5238   void vqadd(
5239       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vqadd(DataType dt,DRegister rd,DRegister rn,DRegister rm)5240   void vqadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5241     vqadd(al, dt, rd, rn, rm);
5242   }
5243 
5244   void vqadd(
5245       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vqadd(DataType dt,QRegister rd,QRegister rn,QRegister rm)5246   void vqadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5247     vqadd(al, dt, rd, rn, rm);
5248   }
5249 
5250   void vqdmlal(
5251       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
vqdmlal(DataType dt,QRegister rd,DRegister rn,DRegister rm)5252   void vqdmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
5253     vqdmlal(al, dt, rd, rn, rm);
5254   }
5255 
5256   void vqdmlal(Condition cond,
5257                DataType dt,
5258                QRegister rd,
5259                DRegister rn,
5260                DRegister dm,
5261                unsigned index);
vqdmlal(DataType dt,QRegister rd,DRegister rn,DRegister dm,unsigned index)5262   void vqdmlal(
5263       DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
5264     vqdmlal(al, dt, rd, rn, dm, index);
5265   }
5266 
5267   void vqdmlsl(
5268       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
vqdmlsl(DataType dt,QRegister rd,DRegister rn,DRegister rm)5269   void vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
5270     vqdmlsl(al, dt, rd, rn, rm);
5271   }
5272 
5273   void vqdmlsl(Condition cond,
5274                DataType dt,
5275                QRegister rd,
5276                DRegister rn,
5277                DRegister dm,
5278                unsigned index);
vqdmlsl(DataType dt,QRegister rd,DRegister rn,DRegister dm,unsigned index)5279   void vqdmlsl(
5280       DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
5281     vqdmlsl(al, dt, rd, rn, dm, index);
5282   }
5283 
5284   void vqdmulh(
5285       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vqdmulh(DataType dt,DRegister rd,DRegister rn,DRegister rm)5286   void vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5287     vqdmulh(al, dt, rd, rn, rm);
5288   }
5289 
5290   void vqdmulh(
5291       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vqdmulh(DataType dt,QRegister rd,QRegister rn,QRegister rm)5292   void vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5293     vqdmulh(al, dt, rd, rn, rm);
5294   }
5295 
5296   void vqdmulh(Condition cond,
5297                DataType dt,
5298                DRegister rd,
5299                DRegister rn,
5300                DRegisterLane rm);
vqdmulh(DataType dt,DRegister rd,DRegister rn,DRegisterLane rm)5301   void vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
5302     vqdmulh(al, dt, rd, rn, rm);
5303   }
5304 
5305   void vqdmulh(Condition cond,
5306                DataType dt,
5307                QRegister rd,
5308                QRegister rn,
5309                DRegisterLane rm);
vqdmulh(DataType dt,QRegister rd,QRegister rn,DRegisterLane rm)5310   void vqdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
5311     vqdmulh(al, dt, rd, rn, rm);
5312   }
5313 
5314   void vqdmull(
5315       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
vqdmull(DataType dt,QRegister rd,DRegister rn,DRegister rm)5316   void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
5317     vqdmull(al, dt, rd, rn, rm);
5318   }
5319 
5320   void vqdmull(Condition cond,
5321                DataType dt,
5322                QRegister rd,
5323                DRegister rn,
5324                DRegisterLane rm);
vqdmull(DataType dt,QRegister rd,DRegister rn,DRegisterLane rm)5325   void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
5326     vqdmull(al, dt, rd, rn, rm);
5327   }
5328 
5329   void vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm);
vqmovn(DataType dt,DRegister rd,QRegister rm)5330   void vqmovn(DataType dt, DRegister rd, QRegister rm) {
5331     vqmovn(al, dt, rd, rm);
5332   }
5333 
5334   void vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm);
vqmovun(DataType dt,DRegister rd,QRegister rm)5335   void vqmovun(DataType dt, DRegister rd, QRegister rm) {
5336     vqmovun(al, dt, rd, rm);
5337   }
5338 
5339   void vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm);
vqneg(DataType dt,DRegister rd,DRegister rm)5340   void vqneg(DataType dt, DRegister rd, DRegister rm) { vqneg(al, dt, rd, rm); }
5341 
5342   void vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm);
vqneg(DataType dt,QRegister rd,QRegister rm)5343   void vqneg(DataType dt, QRegister rd, QRegister rm) { vqneg(al, dt, rd, rm); }
5344 
5345   void vqrdmulh(
5346       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vqrdmulh(DataType dt,DRegister rd,DRegister rn,DRegister rm)5347   void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5348     vqrdmulh(al, dt, rd, rn, rm);
5349   }
5350 
5351   void vqrdmulh(
5352       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vqrdmulh(DataType dt,QRegister rd,QRegister rn,QRegister rm)5353   void vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5354     vqrdmulh(al, dt, rd, rn, rm);
5355   }
5356 
5357   void vqrdmulh(Condition cond,
5358                 DataType dt,
5359                 DRegister rd,
5360                 DRegister rn,
5361                 DRegisterLane rm);
vqrdmulh(DataType dt,DRegister rd,DRegister rn,DRegisterLane rm)5362   void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
5363     vqrdmulh(al, dt, rd, rn, rm);
5364   }
5365 
5366   void vqrdmulh(Condition cond,
5367                 DataType dt,
5368                 QRegister rd,
5369                 QRegister rn,
5370                 DRegisterLane rm);
vqrdmulh(DataType dt,QRegister rd,QRegister rn,DRegisterLane rm)5371   void vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
5372     vqrdmulh(al, dt, rd, rn, rm);
5373   }
5374 
5375   void vqrshl(
5376       Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn);
vqrshl(DataType dt,DRegister rd,DRegister rm,DRegister rn)5377   void vqrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) {
5378     vqrshl(al, dt, rd, rm, rn);
5379   }
5380 
5381   void vqrshl(
5382       Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn);
vqrshl(DataType dt,QRegister rd,QRegister rm,QRegister rn)5383   void vqrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) {
5384     vqrshl(al, dt, rd, rm, rn);
5385   }
5386 
5387   void vqrshrn(Condition cond,
5388                DataType dt,
5389                DRegister rd,
5390                QRegister rm,
5391                const QOperand& operand);
vqrshrn(DataType dt,DRegister rd,QRegister rm,const QOperand & operand)5392   void vqrshrn(DataType dt,
5393                DRegister rd,
5394                QRegister rm,
5395                const QOperand& operand) {
5396     vqrshrn(al, dt, rd, rm, operand);
5397   }
5398 
5399   void vqrshrun(Condition cond,
5400                 DataType dt,
5401                 DRegister rd,
5402                 QRegister rm,
5403                 const QOperand& operand);
vqrshrun(DataType dt,DRegister rd,QRegister rm,const QOperand & operand)5404   void vqrshrun(DataType dt,
5405                 DRegister rd,
5406                 QRegister rm,
5407                 const QOperand& operand) {
5408     vqrshrun(al, dt, rd, rm, operand);
5409   }
5410 
5411   void vqshl(Condition cond,
5412              DataType dt,
5413              DRegister rd,
5414              DRegister rm,
5415              const DOperand& operand);
vqshl(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)5416   void vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5417     vqshl(al, dt, rd, rm, operand);
5418   }
5419 
5420   void vqshl(Condition cond,
5421              DataType dt,
5422              QRegister rd,
5423              QRegister rm,
5424              const QOperand& operand);
vqshl(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)5425   void vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5426     vqshl(al, dt, rd, rm, operand);
5427   }
5428 
5429   void vqshlu(Condition cond,
5430               DataType dt,
5431               DRegister rd,
5432               DRegister rm,
5433               const DOperand& operand);
vqshlu(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)5434   void vqshlu(DataType dt,
5435               DRegister rd,
5436               DRegister rm,
5437               const DOperand& operand) {
5438     vqshlu(al, dt, rd, rm, operand);
5439   }
5440 
5441   void vqshlu(Condition cond,
5442               DataType dt,
5443               QRegister rd,
5444               QRegister rm,
5445               const QOperand& operand);
vqshlu(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)5446   void vqshlu(DataType dt,
5447               QRegister rd,
5448               QRegister rm,
5449               const QOperand& operand) {
5450     vqshlu(al, dt, rd, rm, operand);
5451   }
5452 
5453   void vqshrn(Condition cond,
5454               DataType dt,
5455               DRegister rd,
5456               QRegister rm,
5457               const QOperand& operand);
vqshrn(DataType dt,DRegister rd,QRegister rm,const QOperand & operand)5458   void vqshrn(DataType dt,
5459               DRegister rd,
5460               QRegister rm,
5461               const QOperand& operand) {
5462     vqshrn(al, dt, rd, rm, operand);
5463   }
5464 
5465   void vqshrun(Condition cond,
5466                DataType dt,
5467                DRegister rd,
5468                QRegister rm,
5469                const QOperand& operand);
vqshrun(DataType dt,DRegister rd,QRegister rm,const QOperand & operand)5470   void vqshrun(DataType dt,
5471                DRegister rd,
5472                QRegister rm,
5473                const QOperand& operand) {
5474     vqshrun(al, dt, rd, rm, operand);
5475   }
5476 
5477   void vqsub(
5478       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vqsub(DataType dt,DRegister rd,DRegister rn,DRegister rm)5479   void vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5480     vqsub(al, dt, rd, rn, rm);
5481   }
5482 
5483   void vqsub(
5484       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vqsub(DataType dt,QRegister rd,QRegister rn,QRegister rm)5485   void vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5486     vqsub(al, dt, rd, rn, rm);
5487   }
5488 
5489   void vraddhn(
5490       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
vraddhn(DataType dt,DRegister rd,QRegister rn,QRegister rm)5491   void vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
5492     vraddhn(al, dt, rd, rn, rm);
5493   }
5494 
5495   void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm);
vrecpe(DataType dt,DRegister rd,DRegister rm)5496   void vrecpe(DataType dt, DRegister rd, DRegister rm) {
5497     vrecpe(al, dt, rd, rm);
5498   }
5499 
5500   void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm);
vrecpe(DataType dt,QRegister rd,QRegister rm)5501   void vrecpe(DataType dt, QRegister rd, QRegister rm) {
5502     vrecpe(al, dt, rd, rm);
5503   }
5504 
5505   void vrecps(
5506       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vrecps(DataType dt,DRegister rd,DRegister rn,DRegister rm)5507   void vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5508     vrecps(al, dt, rd, rn, rm);
5509   }
5510 
5511   void vrecps(
5512       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vrecps(DataType dt,QRegister rd,QRegister rn,QRegister rm)5513   void vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5514     vrecps(al, dt, rd, rn, rm);
5515   }
5516 
5517   void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm);
vrev16(DataType dt,DRegister rd,DRegister rm)5518   void vrev16(DataType dt, DRegister rd, DRegister rm) {
5519     vrev16(al, dt, rd, rm);
5520   }
5521 
5522   void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm);
vrev16(DataType dt,QRegister rd,QRegister rm)5523   void vrev16(DataType dt, QRegister rd, QRegister rm) {
5524     vrev16(al, dt, rd, rm);
5525   }
5526 
5527   void vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm);
vrev32(DataType dt,DRegister rd,DRegister rm)5528   void vrev32(DataType dt, DRegister rd, DRegister rm) {
5529     vrev32(al, dt, rd, rm);
5530   }
5531 
5532   void vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm);
vrev32(DataType dt,QRegister rd,QRegister rm)5533   void vrev32(DataType dt, QRegister rd, QRegister rm) {
5534     vrev32(al, dt, rd, rm);
5535   }
5536 
5537   void vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm);
vrev64(DataType dt,DRegister rd,DRegister rm)5538   void vrev64(DataType dt, DRegister rd, DRegister rm) {
5539     vrev64(al, dt, rd, rm);
5540   }
5541 
5542   void vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm);
vrev64(DataType dt,QRegister rd,QRegister rm)5543   void vrev64(DataType dt, QRegister rd, QRegister rm) {
5544     vrev64(al, dt, rd, rm);
5545   }
5546 
5547   void vrhadd(
5548       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vrhadd(DataType dt,DRegister rd,DRegister rn,DRegister rm)5549   void vrhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5550     vrhadd(al, dt, rd, rn, rm);
5551   }
5552 
5553   void vrhadd(
5554       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vrhadd(DataType dt,QRegister rd,QRegister rn,QRegister rm)5555   void vrhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5556     vrhadd(al, dt, rd, rn, rm);
5557   }
5558 
5559   void vrinta(DataType dt, DRegister rd, DRegister rm);
5560 
5561   void vrinta(DataType dt, QRegister rd, QRegister rm);
5562 
5563   void vrinta(DataType dt, SRegister rd, SRegister rm);
5564 
5565   void vrintm(DataType dt, DRegister rd, DRegister rm);
5566 
5567   void vrintm(DataType dt, QRegister rd, QRegister rm);
5568 
5569   void vrintm(DataType dt, SRegister rd, SRegister rm);
5570 
5571   void vrintn(DataType dt, DRegister rd, DRegister rm);
5572 
5573   void vrintn(DataType dt, QRegister rd, QRegister rm);
5574 
5575   void vrintn(DataType dt, SRegister rd, SRegister rm);
5576 
5577   void vrintp(DataType dt, DRegister rd, DRegister rm);
5578 
5579   void vrintp(DataType dt, QRegister rd, QRegister rm);
5580 
5581   void vrintp(DataType dt, SRegister rd, SRegister rm);
5582 
5583   void vrintr(Condition cond, DataType dt, SRegister rd, SRegister rm);
vrintr(DataType dt,SRegister rd,SRegister rm)5584   void vrintr(DataType dt, SRegister rd, SRegister rm) {
5585     vrintr(al, dt, rd, rm);
5586   }
5587 
5588   void vrintr(Condition cond, DataType dt, DRegister rd, DRegister rm);
vrintr(DataType dt,DRegister rd,DRegister rm)5589   void vrintr(DataType dt, DRegister rd, DRegister rm) {
5590     vrintr(al, dt, rd, rm);
5591   }
5592 
5593   void vrintx(Condition cond, DataType dt, DRegister rd, DRegister rm);
vrintx(DataType dt,DRegister rd,DRegister rm)5594   void vrintx(DataType dt, DRegister rd, DRegister rm) {
5595     vrintx(al, dt, rd, rm);
5596   }
5597 
5598   void vrintx(DataType dt, QRegister rd, QRegister rm);
5599 
5600   void vrintx(Condition cond, DataType dt, SRegister rd, SRegister rm);
vrintx(DataType dt,SRegister rd,SRegister rm)5601   void vrintx(DataType dt, SRegister rd, SRegister rm) {
5602     vrintx(al, dt, rd, rm);
5603   }
5604 
5605   void vrintz(Condition cond, DataType dt, DRegister rd, DRegister rm);
vrintz(DataType dt,DRegister rd,DRegister rm)5606   void vrintz(DataType dt, DRegister rd, DRegister rm) {
5607     vrintz(al, dt, rd, rm);
5608   }
5609 
5610   void vrintz(DataType dt, QRegister rd, QRegister rm);
5611 
5612   void vrintz(Condition cond, DataType dt, SRegister rd, SRegister rm);
vrintz(DataType dt,SRegister rd,SRegister rm)5613   void vrintz(DataType dt, SRegister rd, SRegister rm) {
5614     vrintz(al, dt, rd, rm);
5615   }
5616 
5617   void vrshl(
5618       Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn);
vrshl(DataType dt,DRegister rd,DRegister rm,DRegister rn)5619   void vrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) {
5620     vrshl(al, dt, rd, rm, rn);
5621   }
5622 
5623   void vrshl(
5624       Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn);
vrshl(DataType dt,QRegister rd,QRegister rm,QRegister rn)5625   void vrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) {
5626     vrshl(al, dt, rd, rm, rn);
5627   }
5628 
5629   void vrshr(Condition cond,
5630              DataType dt,
5631              DRegister rd,
5632              DRegister rm,
5633              const DOperand& operand);
vrshr(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)5634   void vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5635     vrshr(al, dt, rd, rm, operand);
5636   }
5637 
5638   void vrshr(Condition cond,
5639              DataType dt,
5640              QRegister rd,
5641              QRegister rm,
5642              const QOperand& operand);
vrshr(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)5643   void vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5644     vrshr(al, dt, rd, rm, operand);
5645   }
5646 
5647   void vrshrn(Condition cond,
5648               DataType dt,
5649               DRegister rd,
5650               QRegister rm,
5651               const QOperand& operand);
vrshrn(DataType dt,DRegister rd,QRegister rm,const QOperand & operand)5652   void vrshrn(DataType dt,
5653               DRegister rd,
5654               QRegister rm,
5655               const QOperand& operand) {
5656     vrshrn(al, dt, rd, rm, operand);
5657   }
5658 
5659   void vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm);
vrsqrte(DataType dt,DRegister rd,DRegister rm)5660   void vrsqrte(DataType dt, DRegister rd, DRegister rm) {
5661     vrsqrte(al, dt, rd, rm);
5662   }
5663 
5664   void vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm);
vrsqrte(DataType dt,QRegister rd,QRegister rm)5665   void vrsqrte(DataType dt, QRegister rd, QRegister rm) {
5666     vrsqrte(al, dt, rd, rm);
5667   }
5668 
5669   void vrsqrts(
5670       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vrsqrts(DataType dt,DRegister rd,DRegister rn,DRegister rm)5671   void vrsqrts(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5672     vrsqrts(al, dt, rd, rn, rm);
5673   }
5674 
5675   void vrsqrts(
5676       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vrsqrts(DataType dt,QRegister rd,QRegister rn,QRegister rm)5677   void vrsqrts(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5678     vrsqrts(al, dt, rd, rn, rm);
5679   }
5680 
5681   void vrsra(Condition cond,
5682              DataType dt,
5683              DRegister rd,
5684              DRegister rm,
5685              const DOperand& operand);
vrsra(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)5686   void vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5687     vrsra(al, dt, rd, rm, operand);
5688   }
5689 
5690   void vrsra(Condition cond,
5691              DataType dt,
5692              QRegister rd,
5693              QRegister rm,
5694              const QOperand& operand);
vrsra(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)5695   void vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5696     vrsra(al, dt, rd, rm, operand);
5697   }
5698 
5699   void vrsubhn(
5700       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
vrsubhn(DataType dt,DRegister rd,QRegister rn,QRegister rm)5701   void vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
5702     vrsubhn(al, dt, rd, rn, rm);
5703   }
5704 
5705   void vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm);
5706 
5707   void vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm);
5708 
5709   void vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm);
5710 
5711   void vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm);
5712 
5713   void vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm);
5714 
5715   void vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm);
5716 
5717   void vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm);
5718 
5719   void vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm);
5720 
5721   void vshl(Condition cond,
5722             DataType dt,
5723             DRegister rd,
5724             DRegister rm,
5725             const DOperand& operand);
vshl(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)5726   void vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5727     vshl(al, dt, rd, rm, operand);
5728   }
5729 
5730   void vshl(Condition cond,
5731             DataType dt,
5732             QRegister rd,
5733             QRegister rm,
5734             const QOperand& operand);
vshl(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)5735   void vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5736     vshl(al, dt, rd, rm, operand);
5737   }
5738 
5739   void vshll(Condition cond,
5740              DataType dt,
5741              QRegister rd,
5742              DRegister rm,
5743              const DOperand& operand);
vshll(DataType dt,QRegister rd,DRegister rm,const DOperand & operand)5744   void vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) {
5745     vshll(al, dt, rd, rm, operand);
5746   }
5747 
5748   void vshr(Condition cond,
5749             DataType dt,
5750             DRegister rd,
5751             DRegister rm,
5752             const DOperand& operand);
vshr(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)5753   void vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5754     vshr(al, dt, rd, rm, operand);
5755   }
5756 
5757   void vshr(Condition cond,
5758             DataType dt,
5759             QRegister rd,
5760             QRegister rm,
5761             const QOperand& operand);
vshr(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)5762   void vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5763     vshr(al, dt, rd, rm, operand);
5764   }
5765 
5766   void vshrn(Condition cond,
5767              DataType dt,
5768              DRegister rd,
5769              QRegister rm,
5770              const QOperand& operand);
vshrn(DataType dt,DRegister rd,QRegister rm,const QOperand & operand)5771   void vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) {
5772     vshrn(al, dt, rd, rm, operand);
5773   }
5774 
5775   void vsli(Condition cond,
5776             DataType dt,
5777             DRegister rd,
5778             DRegister rm,
5779             const DOperand& operand);
vsli(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)5780   void vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5781     vsli(al, dt, rd, rm, operand);
5782   }
5783 
5784   void vsli(Condition cond,
5785             DataType dt,
5786             QRegister rd,
5787             QRegister rm,
5788             const QOperand& operand);
vsli(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)5789   void vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5790     vsli(al, dt, rd, rm, operand);
5791   }
5792 
5793   void vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm);
vsqrt(DataType dt,SRegister rd,SRegister rm)5794   void vsqrt(DataType dt, SRegister rd, SRegister rm) { vsqrt(al, dt, rd, rm); }
5795 
5796   void vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm);
vsqrt(DataType dt,DRegister rd,DRegister rm)5797   void vsqrt(DataType dt, DRegister rd, DRegister rm) { vsqrt(al, dt, rd, rm); }
5798 
5799   void vsra(Condition cond,
5800             DataType dt,
5801             DRegister rd,
5802             DRegister rm,
5803             const DOperand& operand);
vsra(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)5804   void vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5805     vsra(al, dt, rd, rm, operand);
5806   }
5807 
5808   void vsra(Condition cond,
5809             DataType dt,
5810             QRegister rd,
5811             QRegister rm,
5812             const QOperand& operand);
vsra(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)5813   void vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5814     vsra(al, dt, rd, rm, operand);
5815   }
5816 
5817   void vsri(Condition cond,
5818             DataType dt,
5819             DRegister rd,
5820             DRegister rm,
5821             const DOperand& operand);
vsri(DataType dt,DRegister rd,DRegister rm,const DOperand & operand)5822   void vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5823     vsri(al, dt, rd, rm, operand);
5824   }
5825 
5826   void vsri(Condition cond,
5827             DataType dt,
5828             QRegister rd,
5829             QRegister rm,
5830             const QOperand& operand);
vsri(DataType dt,QRegister rd,QRegister rm,const QOperand & operand)5831   void vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5832     vsri(al, dt, rd, rm, operand);
5833   }
5834 
5835   void vst1(Condition cond,
5836             DataType dt,
5837             const NeonRegisterList& nreglist,
5838             const AlignedMemOperand& operand);
vst1(DataType dt,const NeonRegisterList & nreglist,const AlignedMemOperand & operand)5839   void vst1(DataType dt,
5840             const NeonRegisterList& nreglist,
5841             const AlignedMemOperand& operand) {
5842     vst1(al, dt, nreglist, operand);
5843   }
5844 
5845   void vst2(Condition cond,
5846             DataType dt,
5847             const NeonRegisterList& nreglist,
5848             const AlignedMemOperand& operand);
vst2(DataType dt,const NeonRegisterList & nreglist,const AlignedMemOperand & operand)5849   void vst2(DataType dt,
5850             const NeonRegisterList& nreglist,
5851             const AlignedMemOperand& operand) {
5852     vst2(al, dt, nreglist, operand);
5853   }
5854 
5855   void vst3(Condition cond,
5856             DataType dt,
5857             const NeonRegisterList& nreglist,
5858             const AlignedMemOperand& operand);
vst3(DataType dt,const NeonRegisterList & nreglist,const AlignedMemOperand & operand)5859   void vst3(DataType dt,
5860             const NeonRegisterList& nreglist,
5861             const AlignedMemOperand& operand) {
5862     vst3(al, dt, nreglist, operand);
5863   }
5864 
5865   void vst3(Condition cond,
5866             DataType dt,
5867             const NeonRegisterList& nreglist,
5868             const MemOperand& operand);
vst3(DataType dt,const NeonRegisterList & nreglist,const MemOperand & operand)5869   void vst3(DataType dt,
5870             const NeonRegisterList& nreglist,
5871             const MemOperand& operand) {
5872     vst3(al, dt, nreglist, operand);
5873   }
5874 
5875   void vst4(Condition cond,
5876             DataType dt,
5877             const NeonRegisterList& nreglist,
5878             const AlignedMemOperand& operand);
vst4(DataType dt,const NeonRegisterList & nreglist,const AlignedMemOperand & operand)5879   void vst4(DataType dt,
5880             const NeonRegisterList& nreglist,
5881             const AlignedMemOperand& operand) {
5882     vst4(al, dt, nreglist, operand);
5883   }
5884 
5885   void vstm(Condition cond,
5886             DataType dt,
5887             Register rn,
5888             WriteBack write_back,
5889             DRegisterList dreglist);
vstm(DataType dt,Register rn,WriteBack write_back,DRegisterList dreglist)5890   void vstm(DataType dt,
5891             Register rn,
5892             WriteBack write_back,
5893             DRegisterList dreglist) {
5894     vstm(al, dt, rn, write_back, dreglist);
5895   }
vstm(Register rn,WriteBack write_back,DRegisterList dreglist)5896   void vstm(Register rn, WriteBack write_back, DRegisterList dreglist) {
5897     vstm(al, kDataTypeValueNone, rn, write_back, dreglist);
5898   }
vstm(Condition cond,Register rn,WriteBack write_back,DRegisterList dreglist)5899   void vstm(Condition cond,
5900             Register rn,
5901             WriteBack write_back,
5902             DRegisterList dreglist) {
5903     vstm(cond, kDataTypeValueNone, rn, write_back, dreglist);
5904   }
5905 
5906   void vstm(Condition cond,
5907             DataType dt,
5908             Register rn,
5909             WriteBack write_back,
5910             SRegisterList sreglist);
vstm(DataType dt,Register rn,WriteBack write_back,SRegisterList sreglist)5911   void vstm(DataType dt,
5912             Register rn,
5913             WriteBack write_back,
5914             SRegisterList sreglist) {
5915     vstm(al, dt, rn, write_back, sreglist);
5916   }
vstm(Register rn,WriteBack write_back,SRegisterList sreglist)5917   void vstm(Register rn, WriteBack write_back, SRegisterList sreglist) {
5918     vstm(al, kDataTypeValueNone, rn, write_back, sreglist);
5919   }
vstm(Condition cond,Register rn,WriteBack write_back,SRegisterList sreglist)5920   void vstm(Condition cond,
5921             Register rn,
5922             WriteBack write_back,
5923             SRegisterList sreglist) {
5924     vstm(cond, kDataTypeValueNone, rn, write_back, sreglist);
5925   }
5926 
5927   void vstmdb(Condition cond,
5928               DataType dt,
5929               Register rn,
5930               WriteBack write_back,
5931               DRegisterList dreglist);
vstmdb(DataType dt,Register rn,WriteBack write_back,DRegisterList dreglist)5932   void vstmdb(DataType dt,
5933               Register rn,
5934               WriteBack write_back,
5935               DRegisterList dreglist) {
5936     vstmdb(al, dt, rn, write_back, dreglist);
5937   }
vstmdb(Register rn,WriteBack write_back,DRegisterList dreglist)5938   void vstmdb(Register rn, WriteBack write_back, DRegisterList dreglist) {
5939     vstmdb(al, kDataTypeValueNone, rn, write_back, dreglist);
5940   }
vstmdb(Condition cond,Register rn,WriteBack write_back,DRegisterList dreglist)5941   void vstmdb(Condition cond,
5942               Register rn,
5943               WriteBack write_back,
5944               DRegisterList dreglist) {
5945     vstmdb(cond, kDataTypeValueNone, rn, write_back, dreglist);
5946   }
5947 
5948   void vstmdb(Condition cond,
5949               DataType dt,
5950               Register rn,
5951               WriteBack write_back,
5952               SRegisterList sreglist);
vstmdb(DataType dt,Register rn,WriteBack write_back,SRegisterList sreglist)5953   void vstmdb(DataType dt,
5954               Register rn,
5955               WriteBack write_back,
5956               SRegisterList sreglist) {
5957     vstmdb(al, dt, rn, write_back, sreglist);
5958   }
vstmdb(Register rn,WriteBack write_back,SRegisterList sreglist)5959   void vstmdb(Register rn, WriteBack write_back, SRegisterList sreglist) {
5960     vstmdb(al, kDataTypeValueNone, rn, write_back, sreglist);
5961   }
vstmdb(Condition cond,Register rn,WriteBack write_back,SRegisterList sreglist)5962   void vstmdb(Condition cond,
5963               Register rn,
5964               WriteBack write_back,
5965               SRegisterList sreglist) {
5966     vstmdb(cond, kDataTypeValueNone, rn, write_back, sreglist);
5967   }
5968 
5969   void vstmia(Condition cond,
5970               DataType dt,
5971               Register rn,
5972               WriteBack write_back,
5973               DRegisterList dreglist);
vstmia(DataType dt,Register rn,WriteBack write_back,DRegisterList dreglist)5974   void vstmia(DataType dt,
5975               Register rn,
5976               WriteBack write_back,
5977               DRegisterList dreglist) {
5978     vstmia(al, dt, rn, write_back, dreglist);
5979   }
vstmia(Register rn,WriteBack write_back,DRegisterList dreglist)5980   void vstmia(Register rn, WriteBack write_back, DRegisterList dreglist) {
5981     vstmia(al, kDataTypeValueNone, rn, write_back, dreglist);
5982   }
vstmia(Condition cond,Register rn,WriteBack write_back,DRegisterList dreglist)5983   void vstmia(Condition cond,
5984               Register rn,
5985               WriteBack write_back,
5986               DRegisterList dreglist) {
5987     vstmia(cond, kDataTypeValueNone, rn, write_back, dreglist);
5988   }
5989 
5990   void vstmia(Condition cond,
5991               DataType dt,
5992               Register rn,
5993               WriteBack write_back,
5994               SRegisterList sreglist);
vstmia(DataType dt,Register rn,WriteBack write_back,SRegisterList sreglist)5995   void vstmia(DataType dt,
5996               Register rn,
5997               WriteBack write_back,
5998               SRegisterList sreglist) {
5999     vstmia(al, dt, rn, write_back, sreglist);
6000   }
vstmia(Register rn,WriteBack write_back,SRegisterList sreglist)6001   void vstmia(Register rn, WriteBack write_back, SRegisterList sreglist) {
6002     vstmia(al, kDataTypeValueNone, rn, write_back, sreglist);
6003   }
vstmia(Condition cond,Register rn,WriteBack write_back,SRegisterList sreglist)6004   void vstmia(Condition cond,
6005               Register rn,
6006               WriteBack write_back,
6007               SRegisterList sreglist) {
6008     vstmia(cond, kDataTypeValueNone, rn, write_back, sreglist);
6009   }
6010 
6011   void vstr(Condition cond,
6012             DataType dt,
6013             DRegister rd,
6014             const MemOperand& operand);
vstr(DataType dt,DRegister rd,const MemOperand & operand)6015   void vstr(DataType dt, DRegister rd, const MemOperand& operand) {
6016     vstr(al, dt, rd, operand);
6017   }
vstr(DRegister rd,const MemOperand & operand)6018   void vstr(DRegister rd, const MemOperand& operand) {
6019     vstr(al, Untyped64, rd, operand);
6020   }
vstr(Condition cond,DRegister rd,const MemOperand & operand)6021   void vstr(Condition cond, DRegister rd, const MemOperand& operand) {
6022     vstr(cond, Untyped64, rd, operand);
6023   }
6024 
6025   void vstr(Condition cond,
6026             DataType dt,
6027             SRegister rd,
6028             const MemOperand& operand);
vstr(DataType dt,SRegister rd,const MemOperand & operand)6029   void vstr(DataType dt, SRegister rd, const MemOperand& operand) {
6030     vstr(al, dt, rd, operand);
6031   }
vstr(SRegister rd,const MemOperand & operand)6032   void vstr(SRegister rd, const MemOperand& operand) {
6033     vstr(al, Untyped32, rd, operand);
6034   }
vstr(Condition cond,SRegister rd,const MemOperand & operand)6035   void vstr(Condition cond, SRegister rd, const MemOperand& operand) {
6036     vstr(cond, Untyped32, rd, operand);
6037   }
6038 
6039   void vsub(
6040       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vsub(DataType dt,DRegister rd,DRegister rn,DRegister rm)6041   void vsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6042     vsub(al, dt, rd, rn, rm);
6043   }
6044 
6045   void vsub(
6046       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vsub(DataType dt,QRegister rd,QRegister rn,QRegister rm)6047   void vsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6048     vsub(al, dt, rd, rn, rm);
6049   }
6050 
6051   void vsub(
6052       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
vsub(DataType dt,SRegister rd,SRegister rn,SRegister rm)6053   void vsub(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6054     vsub(al, dt, rd, rn, rm);
6055   }
6056 
6057   void vsubhn(
6058       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
vsubhn(DataType dt,DRegister rd,QRegister rn,QRegister rm)6059   void vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
6060     vsubhn(al, dt, rd, rn, rm);
6061   }
6062 
6063   void vsubl(
6064       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
vsubl(DataType dt,QRegister rd,DRegister rn,DRegister rm)6065   void vsubl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6066     vsubl(al, dt, rd, rn, rm);
6067   }
6068 
6069   void vsubw(
6070       Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm);
vsubw(DataType dt,QRegister rd,QRegister rn,DRegister rm)6071   void vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) {
6072     vsubw(al, dt, rd, rn, rm);
6073   }
6074 
6075   void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
vswp(DataType dt,DRegister rd,DRegister rm)6076   void vswp(DataType dt, DRegister rd, DRegister rm) { vswp(al, dt, rd, rm); }
vswp(DRegister rd,DRegister rm)6077   void vswp(DRegister rd, DRegister rm) {
6078     vswp(al, kDataTypeValueNone, rd, rm);
6079   }
vswp(Condition cond,DRegister rd,DRegister rm)6080   void vswp(Condition cond, DRegister rd, DRegister rm) {
6081     vswp(cond, kDataTypeValueNone, rd, rm);
6082   }
6083 
6084   void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
vswp(DataType dt,QRegister rd,QRegister rm)6085   void vswp(DataType dt, QRegister rd, QRegister rm) { vswp(al, dt, rd, rm); }
vswp(QRegister rd,QRegister rm)6086   void vswp(QRegister rd, QRegister rm) {
6087     vswp(al, kDataTypeValueNone, rd, rm);
6088   }
vswp(Condition cond,QRegister rd,QRegister rm)6089   void vswp(Condition cond, QRegister rd, QRegister rm) {
6090     vswp(cond, kDataTypeValueNone, rd, rm);
6091   }
6092 
6093   void vtbl(Condition cond,
6094             DataType dt,
6095             DRegister rd,
6096             const NeonRegisterList& nreglist,
6097             DRegister rm);
vtbl(DataType dt,DRegister rd,const NeonRegisterList & nreglist,DRegister rm)6098   void vtbl(DataType dt,
6099             DRegister rd,
6100             const NeonRegisterList& nreglist,
6101             DRegister rm) {
6102     vtbl(al, dt, rd, nreglist, rm);
6103   }
6104 
6105   void vtbx(Condition cond,
6106             DataType dt,
6107             DRegister rd,
6108             const NeonRegisterList& nreglist,
6109             DRegister rm);
vtbx(DataType dt,DRegister rd,const NeonRegisterList & nreglist,DRegister rm)6110   void vtbx(DataType dt,
6111             DRegister rd,
6112             const NeonRegisterList& nreglist,
6113             DRegister rm) {
6114     vtbx(al, dt, rd, nreglist, rm);
6115   }
6116 
6117   void vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm);
vtrn(DataType dt,DRegister rd,DRegister rm)6118   void vtrn(DataType dt, DRegister rd, DRegister rm) { vtrn(al, dt, rd, rm); }
6119 
6120   void vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm);
vtrn(DataType dt,QRegister rd,QRegister rm)6121   void vtrn(DataType dt, QRegister rd, QRegister rm) { vtrn(al, dt, rd, rm); }
6122 
6123   void vtst(
6124       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
vtst(DataType dt,DRegister rd,DRegister rn,DRegister rm)6125   void vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6126     vtst(al, dt, rd, rn, rm);
6127   }
6128 
6129   void vtst(
6130       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
vtst(DataType dt,QRegister rd,QRegister rn,QRegister rm)6131   void vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6132     vtst(al, dt, rd, rn, rm);
6133   }
6134 
6135   void vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm);
vuzp(DataType dt,DRegister rd,DRegister rm)6136   void vuzp(DataType dt, DRegister rd, DRegister rm) { vuzp(al, dt, rd, rm); }
6137 
6138   void vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm);
vuzp(DataType dt,QRegister rd,QRegister rm)6139   void vuzp(DataType dt, QRegister rd, QRegister rm) { vuzp(al, dt, rd, rm); }
6140 
6141   void vzip(Condition cond, DataType dt, DRegister rd, DRegister rm);
vzip(DataType dt,DRegister rd,DRegister rm)6142   void vzip(DataType dt, DRegister rd, DRegister rm) { vzip(al, dt, rd, rm); }
6143 
6144   void vzip(Condition cond, DataType dt, QRegister rd, QRegister rm);
vzip(DataType dt,QRegister rd,QRegister rm)6145   void vzip(DataType dt, QRegister rd, QRegister rm) { vzip(al, dt, rd, rm); }
6146 
6147   void yield(Condition cond, EncodingSize size);
yield()6148   void yield() { yield(al, Best); }
yield(Condition cond)6149   void yield(Condition cond) { yield(cond, Best); }
yield(EncodingSize size)6150   void yield(EncodingSize size) { yield(al, size); }
6151   // End of generated code.
UnimplementedDelegate(InstructionType type)6152   virtual void UnimplementedDelegate(InstructionType type) {
6153     std::string error_message(std::string("Ill-formed '") +
6154                               std::string(ToCString(type)) +
6155                               std::string("' instruction.\n"));
6156     VIXL_ABORT_WITH_MSG(error_message.c_str());
6157   }
AllowUnpredictable()6158   virtual bool AllowUnpredictable() { return allow_unpredictable_; }
AllowStronglyDiscouraged()6159   virtual bool AllowStronglyDiscouraged() {
6160     return allow_strongly_discouraged_;
6161   }
6162 };
6163 
6164 }  // namespace aarch32
6165 }  // namespace vixl
6166 
6167 #endif  // VIXL_AARCH32_ASSEMBLER_AARCH32_H_
6168