1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include <linux/types.h>
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/netdevice.h>
8 #include <linux/vmalloc.h>
9 #include <linux/string.h>
10 #include <linux/in.h>
11 #include <linux/interrupt.h>
12 #include <linux/ip.h>
13 #include <linux/tcp.h>
14 #include <linux/sctp.h>
15 #include <linux/pkt_sched.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/etherdevice.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/if_macvlan.h>
25 #include <linux/if_bridge.h>
26 #include <linux/prefetch.h>
27 #include <linux/bpf.h>
28 #include <linux/bpf_trace.h>
29 #include <linux/atomic.h>
30 #include <linux/numa.h>
31 #include <generated/utsrelease.h>
32 #include <scsi/fc/fc_fcoe.h>
33 #include <net/udp_tunnel.h>
34 #include <net/pkt_cls.h>
35 #include <net/tc_act/tc_gact.h>
36 #include <net/tc_act/tc_mirred.h>
37 #include <net/vxlan.h>
38 #include <net/mpls.h>
39 #include <net/xdp_sock_drv.h>
40 #include <net/xfrm.h>
41
42 #include "ixgbe.h"
43 #include "ixgbe_common.h"
44 #include "ixgbe_dcb_82599.h"
45 #include "ixgbe_phy.h"
46 #include "ixgbe_sriov.h"
47 #include "ixgbe_model.h"
48 #include "ixgbe_txrx_common.h"
49
50 char ixgbe_driver_name[] = "ixgbe";
51 static const char ixgbe_driver_string[] =
52 "Intel(R) 10 Gigabit PCI Express Network Driver";
53 #ifdef IXGBE_FCOE
54 char ixgbe_default_device_descr[] =
55 "Intel(R) 10 Gigabit Network Connection";
56 #else
57 static char ixgbe_default_device_descr[] =
58 "Intel(R) 10 Gigabit Network Connection";
59 #endif
60 static const char ixgbe_copyright[] =
61 "Copyright (c) 1999-2016 Intel Corporation.";
62
63 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
64
65 static const struct ixgbe_info *ixgbe_info_tbl[] = {
66 [board_82598] = &ixgbe_82598_info,
67 [board_82599] = &ixgbe_82599_info,
68 [board_X540] = &ixgbe_X540_info,
69 [board_X550] = &ixgbe_X550_info,
70 [board_X550EM_x] = &ixgbe_X550EM_x_info,
71 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info,
72 [board_x550em_a] = &ixgbe_x550em_a_info,
73 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info,
74 };
75
76 /* ixgbe_pci_tbl - PCI Device ID Table
77 *
78 * Wildcard entries (PCI_ANY_ID) should come last
79 * Last entry must be all 0s
80 *
81 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
82 * Class, Class Mask, private data (not used) }
83 */
84 static const struct pci_device_id ixgbe_pci_tbl[] = {
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x},
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw},
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw },
132 /* required last entry */
133 {0, }
134 };
135 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
136
137 #ifdef CONFIG_IXGBE_DCA
138 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
139 void *p);
140 static struct notifier_block dca_notifier = {
141 .notifier_call = ixgbe_notify_dca,
142 .next = NULL,
143 .priority = 0
144 };
145 #endif
146
147 #ifdef CONFIG_PCI_IOV
148 static unsigned int max_vfs;
149 module_param(max_vfs, uint, 0);
150 MODULE_PARM_DESC(max_vfs,
151 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
152 #endif /* CONFIG_PCI_IOV */
153
154 static unsigned int allow_unsupported_sfp;
155 module_param(allow_unsupported_sfp, uint, 0);
156 MODULE_PARM_DESC(allow_unsupported_sfp,
157 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
158
159 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
160 static int debug = -1;
161 module_param(debug, int, 0);
162 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
163
164 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
165 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
166 MODULE_LICENSE("GPL v2");
167
168 static struct workqueue_struct *ixgbe_wq;
169
170 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
171 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *);
172
173 static const struct net_device_ops ixgbe_netdev_ops;
174
netif_is_ixgbe(struct net_device * dev)175 static bool netif_is_ixgbe(struct net_device *dev)
176 {
177 return dev && (dev->netdev_ops == &ixgbe_netdev_ops);
178 }
179
ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter * adapter,u32 reg,u16 * value)180 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
181 u32 reg, u16 *value)
182 {
183 struct pci_dev *parent_dev;
184 struct pci_bus *parent_bus;
185
186 parent_bus = adapter->pdev->bus->parent;
187 if (!parent_bus)
188 return -1;
189
190 parent_dev = parent_bus->self;
191 if (!parent_dev)
192 return -1;
193
194 if (!pci_is_pcie(parent_dev))
195 return -1;
196
197 pcie_capability_read_word(parent_dev, reg, value);
198 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
199 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
200 return -1;
201 return 0;
202 }
203
ixgbe_get_parent_bus_info(struct ixgbe_adapter * adapter)204 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
205 {
206 struct ixgbe_hw *hw = &adapter->hw;
207 u16 link_status = 0;
208 int err;
209
210 hw->bus.type = ixgbe_bus_type_pci_express;
211
212 /* Get the negotiated link width and speed from PCI config space of the
213 * parent, as this device is behind a switch
214 */
215 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
216
217 /* assume caller will handle error case */
218 if (err)
219 return err;
220
221 hw->bus.width = ixgbe_convert_bus_width(link_status);
222 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
223
224 return 0;
225 }
226
227 /**
228 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
229 * @hw: hw specific details
230 *
231 * This function is used by probe to determine whether a device's PCI-Express
232 * bandwidth details should be gathered from the parent bus instead of from the
233 * device. Used to ensure that various locations all have the correct device ID
234 * checks.
235 */
ixgbe_pcie_from_parent(struct ixgbe_hw * hw)236 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
237 {
238 switch (hw->device_id) {
239 case IXGBE_DEV_ID_82599_SFP_SF_QP:
240 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
241 return true;
242 default:
243 return false;
244 }
245 }
246
ixgbe_check_minimum_link(struct ixgbe_adapter * adapter,int expected_gts)247 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
248 int expected_gts)
249 {
250 struct ixgbe_hw *hw = &adapter->hw;
251 struct pci_dev *pdev;
252
253 /* Some devices are not connected over PCIe and thus do not negotiate
254 * speed. These devices do not have valid bus info, and thus any report
255 * we generate may not be correct.
256 */
257 if (hw->bus.type == ixgbe_bus_type_internal)
258 return;
259
260 /* determine whether to use the parent device */
261 if (ixgbe_pcie_from_parent(&adapter->hw))
262 pdev = adapter->pdev->bus->parent->self;
263 else
264 pdev = adapter->pdev;
265
266 pcie_print_link_status(pdev);
267 }
268
ixgbe_service_event_schedule(struct ixgbe_adapter * adapter)269 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
270 {
271 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
272 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
273 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
274 queue_work(ixgbe_wq, &adapter->service_task);
275 }
276
ixgbe_remove_adapter(struct ixgbe_hw * hw)277 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
278 {
279 struct ixgbe_adapter *adapter = hw->back;
280
281 if (!hw->hw_addr)
282 return;
283 hw->hw_addr = NULL;
284 e_dev_err("Adapter removed\n");
285 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
286 ixgbe_service_event_schedule(adapter);
287 }
288
ixgbe_check_remove(struct ixgbe_hw * hw,u32 reg)289 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
290 {
291 u8 __iomem *reg_addr;
292 u32 value;
293 int i;
294
295 reg_addr = READ_ONCE(hw->hw_addr);
296 if (ixgbe_removed(reg_addr))
297 return IXGBE_FAILED_READ_REG;
298
299 /* Register read of 0xFFFFFFF can indicate the adapter has been removed,
300 * so perform several status register reads to determine if the adapter
301 * has been removed.
302 */
303 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) {
304 value = readl(reg_addr + IXGBE_STATUS);
305 if (value != IXGBE_FAILED_READ_REG)
306 break;
307 mdelay(3);
308 }
309
310 if (value == IXGBE_FAILED_READ_REG)
311 ixgbe_remove_adapter(hw);
312 else
313 value = readl(reg_addr + reg);
314 return value;
315 }
316
317 /**
318 * ixgbe_read_reg - Read from device register
319 * @hw: hw specific details
320 * @reg: offset of register to read
321 *
322 * Returns : value read or IXGBE_FAILED_READ_REG if removed
323 *
324 * This function is used to read device registers. It checks for device
325 * removal by confirming any read that returns all ones by checking the
326 * status register value for all ones. This function avoids reading from
327 * the hardware if a removal was previously detected in which case it
328 * returns IXGBE_FAILED_READ_REG (all ones).
329 */
ixgbe_read_reg(struct ixgbe_hw * hw,u32 reg)330 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
331 {
332 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
333 u32 value;
334
335 if (ixgbe_removed(reg_addr))
336 return IXGBE_FAILED_READ_REG;
337 if (unlikely(hw->phy.nw_mng_if_sel &
338 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) {
339 struct ixgbe_adapter *adapter;
340 int i;
341
342 for (i = 0; i < 200; ++i) {
343 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
344 if (likely(!value))
345 goto writes_completed;
346 if (value == IXGBE_FAILED_READ_REG) {
347 ixgbe_remove_adapter(hw);
348 return IXGBE_FAILED_READ_REG;
349 }
350 udelay(5);
351 }
352
353 adapter = hw->back;
354 e_warn(hw, "register writes incomplete %08x\n", value);
355 }
356
357 writes_completed:
358 value = readl(reg_addr + reg);
359 if (unlikely(value == IXGBE_FAILED_READ_REG))
360 value = ixgbe_check_remove(hw, reg);
361 return value;
362 }
363
ixgbe_check_cfg_remove(struct ixgbe_hw * hw,struct pci_dev * pdev)364 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
365 {
366 u16 value;
367
368 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD) {
370 ixgbe_remove_adapter(hw);
371 return true;
372 }
373 return false;
374 }
375
ixgbe_read_pci_cfg_word(struct ixgbe_hw * hw,u32 reg)376 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
377 {
378 struct ixgbe_adapter *adapter = hw->back;
379 u16 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_WORD;
383 pci_read_config_word(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_WORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_WORD;
387 return value;
388 }
389
390 #ifdef CONFIG_PCI_IOV
ixgbe_read_pci_cfg_dword(struct ixgbe_hw * hw,u32 reg)391 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
392 {
393 struct ixgbe_adapter *adapter = hw->back;
394 u32 value;
395
396 if (ixgbe_removed(hw->hw_addr))
397 return IXGBE_FAILED_READ_CFG_DWORD;
398 pci_read_config_dword(adapter->pdev, reg, &value);
399 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
400 ixgbe_check_cfg_remove(hw, adapter->pdev))
401 return IXGBE_FAILED_READ_CFG_DWORD;
402 return value;
403 }
404 #endif /* CONFIG_PCI_IOV */
405
ixgbe_write_pci_cfg_word(struct ixgbe_hw * hw,u32 reg,u16 value)406 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
407 {
408 struct ixgbe_adapter *adapter = hw->back;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return;
412 pci_write_config_word(adapter->pdev, reg, value);
413 }
414
ixgbe_service_event_complete(struct ixgbe_adapter * adapter)415 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
416 {
417 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
418
419 /* flush memory to make sure state is correct before next watchdog */
420 smp_mb__before_atomic();
421 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
422 }
423
424 struct ixgbe_reg_info {
425 u32 ofs;
426 char *name;
427 };
428
429 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
430
431 /* General Registers */
432 {IXGBE_CTRL, "CTRL"},
433 {IXGBE_STATUS, "STATUS"},
434 {IXGBE_CTRL_EXT, "CTRL_EXT"},
435
436 /* Interrupt Registers */
437 {IXGBE_EICR, "EICR"},
438
439 /* RX Registers */
440 {IXGBE_SRRCTL(0), "SRRCTL"},
441 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
442 {IXGBE_RDLEN(0), "RDLEN"},
443 {IXGBE_RDH(0), "RDH"},
444 {IXGBE_RDT(0), "RDT"},
445 {IXGBE_RXDCTL(0), "RXDCTL"},
446 {IXGBE_RDBAL(0), "RDBAL"},
447 {IXGBE_RDBAH(0), "RDBAH"},
448
449 /* TX Registers */
450 {IXGBE_TDBAL(0), "TDBAL"},
451 {IXGBE_TDBAH(0), "TDBAH"},
452 {IXGBE_TDLEN(0), "TDLEN"},
453 {IXGBE_TDH(0), "TDH"},
454 {IXGBE_TDT(0), "TDT"},
455 {IXGBE_TXDCTL(0), "TXDCTL"},
456
457 /* List Terminator */
458 { .name = NULL }
459 };
460
461
462 /*
463 * ixgbe_regdump - register printout routine
464 */
ixgbe_regdump(struct ixgbe_hw * hw,struct ixgbe_reg_info * reginfo)465 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
466 {
467 int i;
468 char rname[16];
469 u32 regs[64];
470
471 switch (reginfo->ofs) {
472 case IXGBE_SRRCTL(0):
473 for (i = 0; i < 64; i++)
474 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
475 break;
476 case IXGBE_DCA_RXCTRL(0):
477 for (i = 0; i < 64; i++)
478 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
479 break;
480 case IXGBE_RDLEN(0):
481 for (i = 0; i < 64; i++)
482 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
483 break;
484 case IXGBE_RDH(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
487 break;
488 case IXGBE_RDT(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
491 break;
492 case IXGBE_RXDCTL(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
495 break;
496 case IXGBE_RDBAL(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
499 break;
500 case IXGBE_RDBAH(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
503 break;
504 case IXGBE_TDBAL(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
507 break;
508 case IXGBE_TDBAH(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
511 break;
512 case IXGBE_TDLEN(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
515 break;
516 case IXGBE_TDH(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
519 break;
520 case IXGBE_TDT(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
523 break;
524 case IXGBE_TXDCTL(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
527 break;
528 default:
529 pr_info("%-15s %08x\n",
530 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs));
531 return;
532 }
533
534 i = 0;
535 while (i < 64) {
536 int j;
537 char buf[9 * 8 + 1];
538 char *p = buf;
539
540 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7);
541 for (j = 0; j < 8; j++)
542 p += sprintf(p, " %08x", regs[i++]);
543 pr_err("%-15s%s\n", rname, buf);
544 }
545
546 }
547
ixgbe_print_buffer(struct ixgbe_ring * ring,int n)548 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n)
549 {
550 struct ixgbe_tx_buffer *tx_buffer;
551
552 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean];
553 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
554 n, ring->next_to_use, ring->next_to_clean,
555 (u64)dma_unmap_addr(tx_buffer, dma),
556 dma_unmap_len(tx_buffer, len),
557 tx_buffer->next_to_watch,
558 (u64)tx_buffer->time_stamp);
559 }
560
561 /*
562 * ixgbe_dump - Print registers, tx-rings and rx-rings
563 */
ixgbe_dump(struct ixgbe_adapter * adapter)564 static void ixgbe_dump(struct ixgbe_adapter *adapter)
565 {
566 struct net_device *netdev = adapter->netdev;
567 struct ixgbe_hw *hw = &adapter->hw;
568 struct ixgbe_reg_info *reginfo;
569 int n = 0;
570 struct ixgbe_ring *ring;
571 struct ixgbe_tx_buffer *tx_buffer;
572 union ixgbe_adv_tx_desc *tx_desc;
573 struct my_u0 { u64 a; u64 b; } *u0;
574 struct ixgbe_ring *rx_ring;
575 union ixgbe_adv_rx_desc *rx_desc;
576 struct ixgbe_rx_buffer *rx_buffer_info;
577 int i = 0;
578
579 if (!netif_msg_hw(adapter))
580 return;
581
582 /* Print netdevice Info */
583 if (netdev) {
584 dev_info(&adapter->pdev->dev, "Net device Info\n");
585 pr_info("Device Name state "
586 "trans_start\n");
587 pr_info("%-15s %016lX %016lX\n",
588 netdev->name,
589 netdev->state,
590 dev_trans_start(netdev));
591 }
592
593 /* Print Registers */
594 dev_info(&adapter->pdev->dev, "Register Dump\n");
595 pr_info(" Register Name Value\n");
596 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
597 reginfo->name; reginfo++) {
598 ixgbe_regdump(hw, reginfo);
599 }
600
601 /* Print TX Ring Summary */
602 if (!netdev || !netif_running(netdev))
603 return;
604
605 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
606 pr_info(" %s %s %s %s\n",
607 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
608 "leng", "ntw", "timestamp");
609 for (n = 0; n < adapter->num_tx_queues; n++) {
610 ring = adapter->tx_ring[n];
611 ixgbe_print_buffer(ring, n);
612 }
613
614 for (n = 0; n < adapter->num_xdp_queues; n++) {
615 ring = adapter->xdp_ring[n];
616 ixgbe_print_buffer(ring, n);
617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
627 * 82598 Advanced Transmit Descriptor
628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
661 ring = adapter->tx_ring[n];
662 pr_info("------------------------------------\n");
663 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index);
664 pr_info("------------------------------------\n");
665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
669
670 for (i = 0; ring->desc && (i < ring->count); i++) {
671 tx_desc = IXGBE_TX_DESC(ring, i);
672 tx_buffer = &ring->tx_buffer_info[i];
673 u0 = (struct my_u0 *)tx_desc;
674 if (dma_unmap_len(tx_buffer, len) > 0) {
675 const char *ring_desc;
676
677 if (i == ring->next_to_use &&
678 i == ring->next_to_clean)
679 ring_desc = " NTC/U";
680 else if (i == ring->next_to_use)
681 ring_desc = " NTU";
682 else if (i == ring->next_to_clean)
683 ring_desc = " NTC";
684 else
685 ring_desc = "";
686 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s",
687 i,
688 le64_to_cpu((__force __le64)u0->a),
689 le64_to_cpu((__force __le64)u0->b),
690 (u64)dma_unmap_addr(tx_buffer, dma),
691 dma_unmap_len(tx_buffer, len),
692 tx_buffer->next_to_watch,
693 (u64)tx_buffer->time_stamp,
694 tx_buffer->skb,
695 ring_desc);
696
697 if (netif_msg_pktdata(adapter) &&
698 tx_buffer->skb)
699 print_hex_dump(KERN_INFO, "",
700 DUMP_PREFIX_ADDRESS, 16, 1,
701 tx_buffer->skb->data,
702 dma_unmap_len(tx_buffer, len),
703 true);
704 }
705 }
706 }
707
708 /* Print RX Rings Summary */
709 rx_ring_summary:
710 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
711 pr_info("Queue [NTU] [NTC]\n");
712 for (n = 0; n < adapter->num_rx_queues; n++) {
713 rx_ring = adapter->rx_ring[n];
714 pr_info("%5d %5X %5X\n",
715 n, rx_ring->next_to_use, rx_ring->next_to_clean);
716 }
717
718 /* Print RX Rings */
719 if (!netif_msg_rx_status(adapter))
720 return;
721
722 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
723
724 /* Receive Descriptor Formats
725 *
726 * 82598 Advanced Receive Descriptor (Read) Format
727 * 63 1 0
728 * +-----------------------------------------------------+
729 * 0 | Packet Buffer Address [63:1] |A0/NSE|
730 * +----------------------------------------------+------+
731 * 8 | Header Buffer Address [63:1] | DD |
732 * +-----------------------------------------------------+
733 *
734 *
735 * 82598 Advanced Receive Descriptor (Write-Back) Format
736 *
737 * 63 48 47 32 31 30 21 20 16 15 4 3 0
738 * +------------------------------------------------------+
739 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
740 * | Packet | IP | | | | Type | Type |
741 * | Checksum | Ident | | | | | |
742 * +------------------------------------------------------+
743 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
744 * +------------------------------------------------------+
745 * 63 48 47 32 31 20 19 0
746 *
747 * 82599+ Advanced Receive Descriptor (Read) Format
748 * 63 1 0
749 * +-----------------------------------------------------+
750 * 0 | Packet Buffer Address [63:1] |A0/NSE|
751 * +----------------------------------------------+------+
752 * 8 | Header Buffer Address [63:1] | DD |
753 * +-----------------------------------------------------+
754 *
755 *
756 * 82599+ Advanced Receive Descriptor (Write-Back) Format
757 *
758 * 63 48 47 32 31 30 21 20 17 16 4 3 0
759 * +------------------------------------------------------+
760 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
761 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
762 * |/ Flow Dir Flt ID | | | | | |
763 * +------------------------------------------------------+
764 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
765 * +------------------------------------------------------+
766 * 63 48 47 32 31 20 19 0
767 */
768
769 for (n = 0; n < adapter->num_rx_queues; n++) {
770 rx_ring = adapter->rx_ring[n];
771 pr_info("------------------------------------\n");
772 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
773 pr_info("------------------------------------\n");
774 pr_info("%s%s%s\n",
775 "R [desc] [ PktBuf A0] ",
776 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
777 "<-- Adv Rx Read format");
778 pr_info("%s%s%s\n",
779 "RWB[desc] [PcsmIpSHl PtRs] ",
780 "[vl er S cks ln] ---------------- [bi->skb ] ",
781 "<-- Adv Rx Write-Back format");
782
783 for (i = 0; i < rx_ring->count; i++) {
784 const char *ring_desc;
785
786 if (i == rx_ring->next_to_use)
787 ring_desc = " NTU";
788 else if (i == rx_ring->next_to_clean)
789 ring_desc = " NTC";
790 else
791 ring_desc = "";
792
793 rx_buffer_info = &rx_ring->rx_buffer_info[i];
794 rx_desc = IXGBE_RX_DESC(rx_ring, i);
795 u0 = (struct my_u0 *)rx_desc;
796 if (rx_desc->wb.upper.length) {
797 /* Descriptor Done */
798 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n",
799 i,
800 le64_to_cpu((__force __le64)u0->a),
801 le64_to_cpu((__force __le64)u0->b),
802 rx_buffer_info->skb,
803 ring_desc);
804 } else {
805 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n",
806 i,
807 le64_to_cpu((__force __le64)u0->a),
808 le64_to_cpu((__force __le64)u0->b),
809 (u64)rx_buffer_info->dma,
810 rx_buffer_info->skb,
811 ring_desc);
812
813 if (netif_msg_pktdata(adapter) &&
814 rx_buffer_info->dma) {
815 print_hex_dump(KERN_INFO, "",
816 DUMP_PREFIX_ADDRESS, 16, 1,
817 page_address(rx_buffer_info->page) +
818 rx_buffer_info->page_offset,
819 ixgbe_rx_bufsz(rx_ring), true);
820 }
821 }
822 }
823 }
824 }
825
ixgbe_release_hw_control(struct ixgbe_adapter * adapter)826 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
827 {
828 u32 ctrl_ext;
829
830 /* Let firmware take over control of h/w */
831 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
832 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
833 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
834 }
835
ixgbe_get_hw_control(struct ixgbe_adapter * adapter)836 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
837 {
838 u32 ctrl_ext;
839
840 /* Let firmware know the driver has taken over */
841 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
843 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
844 }
845
846 /**
847 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
848 * @adapter: pointer to adapter struct
849 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
850 * @queue: queue to map the corresponding interrupt to
851 * @msix_vector: the vector to map to the corresponding queue
852 *
853 */
ixgbe_set_ivar(struct ixgbe_adapter * adapter,s8 direction,u8 queue,u8 msix_vector)854 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
855 u8 queue, u8 msix_vector)
856 {
857 u32 ivar, index;
858 struct ixgbe_hw *hw = &adapter->hw;
859 switch (hw->mac.type) {
860 case ixgbe_mac_82598EB:
861 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
862 if (direction == -1)
863 direction = 0;
864 index = (((direction * 64) + queue) >> 2) & 0x1F;
865 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
866 ivar &= ~(0xFF << (8 * (queue & 0x3)));
867 ivar |= (msix_vector << (8 * (queue & 0x3)));
868 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
869 break;
870 case ixgbe_mac_82599EB:
871 case ixgbe_mac_X540:
872 case ixgbe_mac_X550:
873 case ixgbe_mac_X550EM_x:
874 case ixgbe_mac_x550em_a:
875 if (direction == -1) {
876 /* other causes */
877 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
878 index = ((queue & 1) * 8);
879 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
880 ivar &= ~(0xFF << index);
881 ivar |= (msix_vector << index);
882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
883 break;
884 } else {
885 /* tx or rx causes */
886 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
887 index = ((16 * (queue & 1)) + (8 * direction));
888 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
889 ivar &= ~(0xFF << index);
890 ivar |= (msix_vector << index);
891 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
892 break;
893 }
894 default:
895 break;
896 }
897 }
898
ixgbe_irq_rearm_queues(struct ixgbe_adapter * adapter,u64 qmask)899 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
900 u64 qmask)
901 {
902 u32 mask;
903
904 switch (adapter->hw.mac.type) {
905 case ixgbe_mac_82598EB:
906 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
908 break;
909 case ixgbe_mac_82599EB:
910 case ixgbe_mac_X540:
911 case ixgbe_mac_X550:
912 case ixgbe_mac_X550EM_x:
913 case ixgbe_mac_x550em_a:
914 mask = (qmask & 0xFFFFFFFF);
915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
916 mask = (qmask >> 32);
917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
918 break;
919 default:
920 break;
921 }
922 }
923
ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter * adapter)924 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
925 {
926 struct ixgbe_hw *hw = &adapter->hw;
927 struct ixgbe_hw_stats *hwstats = &adapter->stats;
928 int i;
929 u32 data;
930
931 if ((hw->fc.current_mode != ixgbe_fc_full) &&
932 (hw->fc.current_mode != ixgbe_fc_rx_pause))
933 return;
934
935 switch (hw->mac.type) {
936 case ixgbe_mac_82598EB:
937 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
938 break;
939 default:
940 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
941 }
942 hwstats->lxoffrxc += data;
943
944 /* refill credits (no tx hang) if we received xoff */
945 if (!data)
946 return;
947
948 for (i = 0; i < adapter->num_tx_queues; i++)
949 clear_bit(__IXGBE_HANG_CHECK_ARMED,
950 &adapter->tx_ring[i]->state);
951
952 for (i = 0; i < adapter->num_xdp_queues; i++)
953 clear_bit(__IXGBE_HANG_CHECK_ARMED,
954 &adapter->xdp_ring[i]->state);
955 }
956
ixgbe_update_xoff_received(struct ixgbe_adapter * adapter)957 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
958 {
959 struct ixgbe_hw *hw = &adapter->hw;
960 struct ixgbe_hw_stats *hwstats = &adapter->stats;
961 u32 xoff[8] = {0};
962 u8 tc;
963 int i;
964 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
965
966 if (adapter->ixgbe_ieee_pfc)
967 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
968
969 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
970 ixgbe_update_xoff_rx_lfc(adapter);
971 return;
972 }
973
974 /* update stats for each tc, only valid with PFC enabled */
975 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
976 u32 pxoffrxc;
977
978 switch (hw->mac.type) {
979 case ixgbe_mac_82598EB:
980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
981 break;
982 default:
983 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
984 }
985 hwstats->pxoffrxc[i] += pxoffrxc;
986 /* Get the TC for given UP */
987 tc = netdev_get_prio_tc_map(adapter->netdev, i);
988 xoff[tc] += pxoffrxc;
989 }
990
991 /* disarm tx queues that have received xoff frames */
992 for (i = 0; i < adapter->num_tx_queues; i++) {
993 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
994
995 tc = tx_ring->dcb_tc;
996 if (xoff[tc])
997 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
998 }
999
1000 for (i = 0; i < adapter->num_xdp_queues; i++) {
1001 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
1002
1003 tc = xdp_ring->dcb_tc;
1004 if (xoff[tc])
1005 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state);
1006 }
1007 }
1008
ixgbe_get_tx_completed(struct ixgbe_ring * ring)1009 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1010 {
1011 return ring->stats.packets;
1012 }
1013
ixgbe_get_tx_pending(struct ixgbe_ring * ring)1014 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1015 {
1016 unsigned int head, tail;
1017
1018 head = ring->next_to_clean;
1019 tail = ring->next_to_use;
1020
1021 return ((head <= tail) ? tail : tail + ring->count) - head;
1022 }
1023
ixgbe_check_tx_hang(struct ixgbe_ring * tx_ring)1024 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1025 {
1026 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1027 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1028 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1029
1030 clear_check_for_tx_hang(tx_ring);
1031
1032 /*
1033 * Check for a hung queue, but be thorough. This verifies
1034 * that a transmit has been completed since the previous
1035 * check AND there is at least one packet pending. The
1036 * ARMED bit is set to indicate a potential hang. The
1037 * bit is cleared if a pause frame is received to remove
1038 * false hang detection due to PFC or 802.3x frames. By
1039 * requiring this to fail twice we avoid races with
1040 * pfc clearing the ARMED bit and conditions where we
1041 * run the check_tx_hang logic with a transmit completion
1042 * pending but without time to complete it yet.
1043 */
1044 if (tx_done_old == tx_done && tx_pending)
1045 /* make sure it is true for two checks in a row */
1046 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1047 &tx_ring->state);
1048 /* update completed stats and continue */
1049 tx_ring->tx_stats.tx_done_old = tx_done;
1050 /* reset the countdown */
1051 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1052
1053 return false;
1054 }
1055
1056 /**
1057 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1058 * @adapter: driver private struct
1059 **/
ixgbe_tx_timeout_reset(struct ixgbe_adapter * adapter)1060 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1061 {
1062
1063 /* Do the reset outside of interrupt context */
1064 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1065 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
1066 e_warn(drv, "initiating reset due to tx timeout\n");
1067 ixgbe_service_event_schedule(adapter);
1068 }
1069 }
1070
1071 /**
1072 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1073 * @netdev: network interface device structure
1074 * @queue_index: Tx queue to set
1075 * @maxrate: desired maximum transmit bitrate
1076 **/
ixgbe_tx_maxrate(struct net_device * netdev,int queue_index,u32 maxrate)1077 static int ixgbe_tx_maxrate(struct net_device *netdev,
1078 int queue_index, u32 maxrate)
1079 {
1080 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1081 struct ixgbe_hw *hw = &adapter->hw;
1082 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1083
1084 if (!maxrate)
1085 return 0;
1086
1087 /* Calculate the rate factor values to set */
1088 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1089 bcnrc_val /= maxrate;
1090
1091 /* clear everything but the rate factor */
1092 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1093 IXGBE_RTTBCNRC_RF_DEC_MASK;
1094
1095 /* enable the rate scheduler */
1096 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1097
1098 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1099 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1100
1101 return 0;
1102 }
1103
1104 /**
1105 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1106 * @q_vector: structure containing interrupt and ring information
1107 * @tx_ring: tx ring to clean
1108 * @napi_budget: Used to determine if we are in netpoll
1109 **/
ixgbe_clean_tx_irq(struct ixgbe_q_vector * q_vector,struct ixgbe_ring * tx_ring,int napi_budget)1110 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1111 struct ixgbe_ring *tx_ring, int napi_budget)
1112 {
1113 struct ixgbe_adapter *adapter = q_vector->adapter;
1114 struct ixgbe_tx_buffer *tx_buffer;
1115 union ixgbe_adv_tx_desc *tx_desc;
1116 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0;
1117 unsigned int budget = q_vector->tx.work_limit;
1118 unsigned int i = tx_ring->next_to_clean;
1119
1120 if (test_bit(__IXGBE_DOWN, &adapter->state))
1121 return true;
1122
1123 tx_buffer = &tx_ring->tx_buffer_info[i];
1124 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1125 i -= tx_ring->count;
1126
1127 do {
1128 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1129
1130 /* if next_to_watch is not set then there is no work pending */
1131 if (!eop_desc)
1132 break;
1133
1134 /* prevent any other reads prior to eop_desc */
1135 smp_rmb();
1136
1137 /* if DD is not set pending work has not been completed */
1138 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1139 break;
1140
1141 /* clear next_to_watch to prevent false hangs */
1142 tx_buffer->next_to_watch = NULL;
1143
1144 /* update the statistics for this packet */
1145 total_bytes += tx_buffer->bytecount;
1146 total_packets += tx_buffer->gso_segs;
1147 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC)
1148 total_ipsec++;
1149
1150 /* free the skb */
1151 if (ring_is_xdp(tx_ring))
1152 xdp_return_frame(tx_buffer->xdpf);
1153 else
1154 napi_consume_skb(tx_buffer->skb, napi_budget);
1155
1156 /* unmap skb header data */
1157 dma_unmap_single(tx_ring->dev,
1158 dma_unmap_addr(tx_buffer, dma),
1159 dma_unmap_len(tx_buffer, len),
1160 DMA_TO_DEVICE);
1161
1162 /* clear tx_buffer data */
1163 dma_unmap_len_set(tx_buffer, len, 0);
1164
1165 /* unmap remaining buffers */
1166 while (tx_desc != eop_desc) {
1167 tx_buffer++;
1168 tx_desc++;
1169 i++;
1170 if (unlikely(!i)) {
1171 i -= tx_ring->count;
1172 tx_buffer = tx_ring->tx_buffer_info;
1173 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1174 }
1175
1176 /* unmap any remaining paged data */
1177 if (dma_unmap_len(tx_buffer, len)) {
1178 dma_unmap_page(tx_ring->dev,
1179 dma_unmap_addr(tx_buffer, dma),
1180 dma_unmap_len(tx_buffer, len),
1181 DMA_TO_DEVICE);
1182 dma_unmap_len_set(tx_buffer, len, 0);
1183 }
1184 }
1185
1186 /* move us one more past the eop_desc for start of next pkt */
1187 tx_buffer++;
1188 tx_desc++;
1189 i++;
1190 if (unlikely(!i)) {
1191 i -= tx_ring->count;
1192 tx_buffer = tx_ring->tx_buffer_info;
1193 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1194 }
1195
1196 /* issue prefetch for next Tx descriptor */
1197 prefetch(tx_desc);
1198
1199 /* update budget accounting */
1200 budget--;
1201 } while (likely(budget));
1202
1203 i += tx_ring->count;
1204 tx_ring->next_to_clean = i;
1205 u64_stats_update_begin(&tx_ring->syncp);
1206 tx_ring->stats.bytes += total_bytes;
1207 tx_ring->stats.packets += total_packets;
1208 u64_stats_update_end(&tx_ring->syncp);
1209 q_vector->tx.total_bytes += total_bytes;
1210 q_vector->tx.total_packets += total_packets;
1211 adapter->tx_ipsec += total_ipsec;
1212
1213 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1214 /* schedule immediate reset if we believe we hung */
1215 struct ixgbe_hw *hw = &adapter->hw;
1216 e_err(drv, "Detected Tx Unit Hang %s\n"
1217 " Tx Queue <%d>\n"
1218 " TDH, TDT <%x>, <%x>\n"
1219 " next_to_use <%x>\n"
1220 " next_to_clean <%x>\n"
1221 "tx_buffer_info[next_to_clean]\n"
1222 " time_stamp <%lx>\n"
1223 " jiffies <%lx>\n",
1224 ring_is_xdp(tx_ring) ? "(XDP)" : "",
1225 tx_ring->queue_index,
1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1228 tx_ring->next_to_use, i,
1229 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1230
1231 if (!ring_is_xdp(tx_ring))
1232 netif_stop_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
1234
1235 e_info(probe,
1236 "tx hang %d detected on queue %d, resetting adapter\n",
1237 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1238
1239 /* schedule immediate reset if we believe we hung */
1240 ixgbe_tx_timeout_reset(adapter);
1241
1242 /* the adapter is about to reset, no point in enabling stuff */
1243 return true;
1244 }
1245
1246 if (ring_is_xdp(tx_ring))
1247 return !!budget;
1248
1249 netdev_tx_completed_queue(txring_txq(tx_ring),
1250 total_packets, total_bytes);
1251
1252 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1253 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1254 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1255 /* Make sure that anybody stopping the queue after this
1256 * sees the new next_to_clean.
1257 */
1258 smp_mb();
1259 if (__netif_subqueue_stopped(tx_ring->netdev,
1260 tx_ring->queue_index)
1261 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1262 netif_wake_subqueue(tx_ring->netdev,
1263 tx_ring->queue_index);
1264 ++tx_ring->tx_stats.restart_queue;
1265 }
1266 }
1267
1268 return !!budget;
1269 }
1270
1271 #ifdef CONFIG_IXGBE_DCA
ixgbe_update_tx_dca(struct ixgbe_adapter * adapter,struct ixgbe_ring * tx_ring,int cpu)1272 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1273 struct ixgbe_ring *tx_ring,
1274 int cpu)
1275 {
1276 struct ixgbe_hw *hw = &adapter->hw;
1277 u32 txctrl = 0;
1278 u16 reg_offset;
1279
1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1282
1283 switch (hw->mac.type) {
1284 case ixgbe_mac_82598EB:
1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1286 break;
1287 case ixgbe_mac_82599EB:
1288 case ixgbe_mac_X540:
1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1290 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1291 break;
1292 default:
1293 /* for unknown hardware do not write register */
1294 return;
1295 }
1296
1297 /*
1298 * We can enable relaxed ordering for reads, but not writes when
1299 * DCA is enabled. This is due to a known issue in some chipsets
1300 * which will cause the DCA tag to be cleared.
1301 */
1302 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1303 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1304 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1305
1306 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1307 }
1308
ixgbe_update_rx_dca(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring,int cpu)1309 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1310 struct ixgbe_ring *rx_ring,
1311 int cpu)
1312 {
1313 struct ixgbe_hw *hw = &adapter->hw;
1314 u32 rxctrl = 0;
1315 u8 reg_idx = rx_ring->reg_idx;
1316
1317 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1318 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1319
1320 switch (hw->mac.type) {
1321 case ixgbe_mac_82599EB:
1322 case ixgbe_mac_X540:
1323 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1324 break;
1325 default:
1326 break;
1327 }
1328
1329 /*
1330 * We can enable relaxed ordering for reads, but not writes when
1331 * DCA is enabled. This is due to a known issue in some chipsets
1332 * which will cause the DCA tag to be cleared.
1333 */
1334 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1335 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1336 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1337
1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1339 }
1340
ixgbe_update_dca(struct ixgbe_q_vector * q_vector)1341 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1342 {
1343 struct ixgbe_adapter *adapter = q_vector->adapter;
1344 struct ixgbe_ring *ring;
1345 int cpu = get_cpu();
1346
1347 if (q_vector->cpu == cpu)
1348 goto out_no_update;
1349
1350 ixgbe_for_each_ring(ring, q_vector->tx)
1351 ixgbe_update_tx_dca(adapter, ring, cpu);
1352
1353 ixgbe_for_each_ring(ring, q_vector->rx)
1354 ixgbe_update_rx_dca(adapter, ring, cpu);
1355
1356 q_vector->cpu = cpu;
1357 out_no_update:
1358 put_cpu();
1359 }
1360
ixgbe_setup_dca(struct ixgbe_adapter * adapter)1361 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1362 {
1363 int i;
1364
1365 /* always use CB2 mode, difference is masked in the CB driver */
1366 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1368 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1369 else
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1371 IXGBE_DCA_CTRL_DCA_DISABLE);
1372
1373 for (i = 0; i < adapter->num_q_vectors; i++) {
1374 adapter->q_vector[i]->cpu = -1;
1375 ixgbe_update_dca(adapter->q_vector[i]);
1376 }
1377 }
1378
__ixgbe_notify_dca(struct device * dev,void * data)1379 static int __ixgbe_notify_dca(struct device *dev, void *data)
1380 {
1381 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1382 unsigned long event = *(unsigned long *)data;
1383
1384 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1385 return 0;
1386
1387 switch (event) {
1388 case DCA_PROVIDER_ADD:
1389 /* if we're already enabled, don't do it again */
1390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1391 break;
1392 if (dca_add_requester(dev) == 0) {
1393 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1395 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1396 break;
1397 }
1398 fallthrough; /* DCA is disabled. */
1399 case DCA_PROVIDER_REMOVE:
1400 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1401 dca_remove_requester(dev);
1402 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1404 IXGBE_DCA_CTRL_DCA_DISABLE);
1405 }
1406 break;
1407 }
1408
1409 return 0;
1410 }
1411
1412 #endif /* CONFIG_IXGBE_DCA */
1413
1414 #define IXGBE_RSS_L4_TYPES_MASK \
1415 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1416 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1419
ixgbe_rx_hash(struct ixgbe_ring * ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1420 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1421 union ixgbe_adv_rx_desc *rx_desc,
1422 struct sk_buff *skb)
1423 {
1424 u16 rss_type;
1425
1426 if (!(ring->netdev->features & NETIF_F_RXHASH))
1427 return;
1428
1429 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1430 IXGBE_RXDADV_RSSTYPE_MASK;
1431
1432 if (!rss_type)
1433 return;
1434
1435 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1436 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1437 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1438 }
1439
1440 #ifdef IXGBE_FCOE
1441 /**
1442 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1443 * @ring: structure containing ring specific data
1444 * @rx_desc: advanced rx descriptor
1445 *
1446 * Returns : true if it is FCoE pkt
1447 */
ixgbe_rx_is_fcoe(struct ixgbe_ring * ring,union ixgbe_adv_rx_desc * rx_desc)1448 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1449 union ixgbe_adv_rx_desc *rx_desc)
1450 {
1451 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1452
1453 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1454 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1455 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1456 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1457 }
1458
1459 #endif /* IXGBE_FCOE */
1460 /**
1461 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1462 * @ring: structure containing ring specific data
1463 * @rx_desc: current Rx descriptor being processed
1464 * @skb: skb currently being received and modified
1465 **/
ixgbe_rx_checksum(struct ixgbe_ring * ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1466 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1467 union ixgbe_adv_rx_desc *rx_desc,
1468 struct sk_buff *skb)
1469 {
1470 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1471 bool encap_pkt = false;
1472
1473 skb_checksum_none_assert(skb);
1474
1475 /* Rx csum disabled */
1476 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1477 return;
1478
1479 /* check for VXLAN and Geneve packets */
1480 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
1481 encap_pkt = true;
1482 skb->encapsulation = 1;
1483 }
1484
1485 /* if IP and error */
1486 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1487 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1488 ring->rx_stats.csum_err++;
1489 return;
1490 }
1491
1492 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1493 return;
1494
1495 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1496 /*
1497 * 82599 errata, UDP frames with a 0 checksum can be marked as
1498 * checksum errors.
1499 */
1500 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1501 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1502 return;
1503
1504 ring->rx_stats.csum_err++;
1505 return;
1506 }
1507
1508 /* It must be a TCP or UDP packet with a valid checksum */
1509 skb->ip_summed = CHECKSUM_UNNECESSARY;
1510 if (encap_pkt) {
1511 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1512 return;
1513
1514 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1515 skb->ip_summed = CHECKSUM_NONE;
1516 return;
1517 }
1518 /* If we checked the outer header let the stack know */
1519 skb->csum_level = 1;
1520 }
1521 }
1522
ixgbe_rx_offset(struct ixgbe_ring * rx_ring)1523 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring)
1524 {
1525 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0;
1526 }
1527
ixgbe_alloc_mapped_page(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * bi)1528 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1529 struct ixgbe_rx_buffer *bi)
1530 {
1531 struct page *page = bi->page;
1532 dma_addr_t dma;
1533
1534 /* since we are recycling buffers we should seldom need to alloc */
1535 if (likely(page))
1536 return true;
1537
1538 /* alloc new page for storage */
1539 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1540 if (unlikely(!page)) {
1541 rx_ring->rx_stats.alloc_rx_page_failed++;
1542 return false;
1543 }
1544
1545 /* map page for use */
1546 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1547 ixgbe_rx_pg_size(rx_ring),
1548 DMA_FROM_DEVICE,
1549 IXGBE_RX_DMA_ATTR);
1550
1551 /*
1552 * if mapping failed free memory back to system since
1553 * there isn't much point in holding memory we can't use
1554 */
1555 if (dma_mapping_error(rx_ring->dev, dma)) {
1556 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1557
1558 rx_ring->rx_stats.alloc_rx_page_failed++;
1559 return false;
1560 }
1561
1562 bi->dma = dma;
1563 bi->page = page;
1564 bi->page_offset = ixgbe_rx_offset(rx_ring);
1565 page_ref_add(page, USHRT_MAX - 1);
1566 bi->pagecnt_bias = USHRT_MAX;
1567 rx_ring->rx_stats.alloc_rx_page++;
1568
1569 return true;
1570 }
1571
1572 /**
1573 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1574 * @rx_ring: ring to place buffers on
1575 * @cleaned_count: number of buffers to replace
1576 **/
ixgbe_alloc_rx_buffers(struct ixgbe_ring * rx_ring,u16 cleaned_count)1577 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1578 {
1579 union ixgbe_adv_rx_desc *rx_desc;
1580 struct ixgbe_rx_buffer *bi;
1581 u16 i = rx_ring->next_to_use;
1582 u16 bufsz;
1583
1584 /* nothing to do */
1585 if (!cleaned_count)
1586 return;
1587
1588 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1589 bi = &rx_ring->rx_buffer_info[i];
1590 i -= rx_ring->count;
1591
1592 bufsz = ixgbe_rx_bufsz(rx_ring);
1593
1594 do {
1595 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1596 break;
1597
1598 /* sync the buffer for use by the device */
1599 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1600 bi->page_offset, bufsz,
1601 DMA_FROM_DEVICE);
1602
1603 /*
1604 * Refresh the desc even if buffer_addrs didn't change
1605 * because each write-back erases this info.
1606 */
1607 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1608
1609 rx_desc++;
1610 bi++;
1611 i++;
1612 if (unlikely(!i)) {
1613 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1614 bi = rx_ring->rx_buffer_info;
1615 i -= rx_ring->count;
1616 }
1617
1618 /* clear the length for the next_to_use descriptor */
1619 rx_desc->wb.upper.length = 0;
1620
1621 cleaned_count--;
1622 } while (cleaned_count);
1623
1624 i += rx_ring->count;
1625
1626 if (rx_ring->next_to_use != i) {
1627 rx_ring->next_to_use = i;
1628
1629 /* update next to alloc since we have filled the ring */
1630 rx_ring->next_to_alloc = i;
1631
1632 /* Force memory writes to complete before letting h/w
1633 * know there are new descriptors to fetch. (Only
1634 * applicable for weak-ordered memory model archs,
1635 * such as IA-64).
1636 */
1637 wmb();
1638 writel(i, rx_ring->tail);
1639 }
1640 }
1641
ixgbe_set_rsc_gso_size(struct ixgbe_ring * ring,struct sk_buff * skb)1642 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1643 struct sk_buff *skb)
1644 {
1645 u16 hdr_len = skb_headlen(skb);
1646
1647 /* set gso_size to avoid messing up TCP MSS */
1648 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1649 IXGBE_CB(skb)->append_cnt);
1650 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1651 }
1652
ixgbe_update_rsc_stats(struct ixgbe_ring * rx_ring,struct sk_buff * skb)1653 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1654 struct sk_buff *skb)
1655 {
1656 /* if append_cnt is 0 then frame is not RSC */
1657 if (!IXGBE_CB(skb)->append_cnt)
1658 return;
1659
1660 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1661 rx_ring->rx_stats.rsc_flush++;
1662
1663 ixgbe_set_rsc_gso_size(rx_ring, skb);
1664
1665 /* gso_size is computed using append_cnt so always clear it last */
1666 IXGBE_CB(skb)->append_cnt = 0;
1667 }
1668
1669 /**
1670 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1671 * @rx_ring: rx descriptor ring packet is being transacted on
1672 * @rx_desc: pointer to the EOP Rx descriptor
1673 * @skb: pointer to current skb being populated
1674 *
1675 * This function checks the ring, descriptor, and packet information in
1676 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1677 * other fields within the skb.
1678 **/
ixgbe_process_skb_fields(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1679 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1680 union ixgbe_adv_rx_desc *rx_desc,
1681 struct sk_buff *skb)
1682 {
1683 struct net_device *dev = rx_ring->netdev;
1684 u32 flags = rx_ring->q_vector->adapter->flags;
1685
1686 ixgbe_update_rsc_stats(rx_ring, skb);
1687
1688 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1689
1690 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1691
1692 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1693 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1694
1695 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1696 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1697 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1699 }
1700
1701 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP))
1702 ixgbe_ipsec_rx(rx_ring, rx_desc, skb);
1703
1704 /* record Rx queue, or update MACVLAN statistics */
1705 if (netif_is_ixgbe(dev))
1706 skb_record_rx_queue(skb, rx_ring->queue_index);
1707 else
1708 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true,
1709 false);
1710
1711 skb->protocol = eth_type_trans(skb, dev);
1712 }
1713
ixgbe_rx_skb(struct ixgbe_q_vector * q_vector,struct sk_buff * skb)1714 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1715 struct sk_buff *skb)
1716 {
1717 napi_gro_receive(&q_vector->napi, skb);
1718 }
1719
1720 /**
1721 * ixgbe_is_non_eop - process handling of non-EOP buffers
1722 * @rx_ring: Rx ring being processed
1723 * @rx_desc: Rx descriptor for current buffer
1724 * @skb: Current socket buffer containing buffer in progress
1725 *
1726 * This function updates next to clean. If the buffer is an EOP buffer
1727 * this function exits returning false, otherwise it will place the
1728 * sk_buff in the next buffer to be chained and return true indicating
1729 * that this is in fact a non-EOP buffer.
1730 **/
ixgbe_is_non_eop(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1731 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1732 union ixgbe_adv_rx_desc *rx_desc,
1733 struct sk_buff *skb)
1734 {
1735 u32 ntc = rx_ring->next_to_clean + 1;
1736
1737 /* fetch, update, and store next to clean */
1738 ntc = (ntc < rx_ring->count) ? ntc : 0;
1739 rx_ring->next_to_clean = ntc;
1740
1741 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1742
1743 /* update RSC append count if present */
1744 if (ring_is_rsc_enabled(rx_ring)) {
1745 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1746 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1747
1748 if (unlikely(rsc_enabled)) {
1749 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1750
1751 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1752 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1753
1754 /* update ntc based on RSC value */
1755 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1756 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1757 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1758 }
1759 }
1760
1761 /* if we are the last buffer then there is nothing else to do */
1762 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1763 return false;
1764
1765 /* place skb in next buffer to be received */
1766 rx_ring->rx_buffer_info[ntc].skb = skb;
1767 rx_ring->rx_stats.non_eop_descs++;
1768
1769 return true;
1770 }
1771
1772 /**
1773 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1774 * @rx_ring: rx descriptor ring packet is being transacted on
1775 * @skb: pointer to current skb being adjusted
1776 *
1777 * This function is an ixgbe specific version of __pskb_pull_tail. The
1778 * main difference between this version and the original function is that
1779 * this function can make several assumptions about the state of things
1780 * that allow for significant optimizations versus the standard function.
1781 * As a result we can do things like drop a frag and maintain an accurate
1782 * truesize for the skb.
1783 */
ixgbe_pull_tail(struct ixgbe_ring * rx_ring,struct sk_buff * skb)1784 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1785 struct sk_buff *skb)
1786 {
1787 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1788 unsigned char *va;
1789 unsigned int pull_len;
1790
1791 /*
1792 * it is valid to use page_address instead of kmap since we are
1793 * working with pages allocated out of the lomem pool per
1794 * alloc_page(GFP_ATOMIC)
1795 */
1796 va = skb_frag_address(frag);
1797
1798 /*
1799 * we need the header to contain the greater of either ETH_HLEN or
1800 * 60 bytes if the skb->len is less than 60 for skb_pad.
1801 */
1802 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE);
1803
1804 /* align pull length to size of long to optimize memcpy performance */
1805 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1806
1807 /* update all of the pointers */
1808 skb_frag_size_sub(frag, pull_len);
1809 skb_frag_off_add(frag, pull_len);
1810 skb->data_len -= pull_len;
1811 skb->tail += pull_len;
1812 }
1813
1814 /**
1815 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1816 * @rx_ring: rx descriptor ring packet is being transacted on
1817 * @skb: pointer to current skb being updated
1818 *
1819 * This function provides a basic DMA sync up for the first fragment of an
1820 * skb. The reason for doing this is that the first fragment cannot be
1821 * unmapped until we have reached the end of packet descriptor for a buffer
1822 * chain.
1823 */
ixgbe_dma_sync_frag(struct ixgbe_ring * rx_ring,struct sk_buff * skb)1824 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1825 struct sk_buff *skb)
1826 {
1827 if (ring_uses_build_skb(rx_ring)) {
1828 unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1;
1829 unsigned long offset = (unsigned long)(skb->data) & mask;
1830
1831 dma_sync_single_range_for_cpu(rx_ring->dev,
1832 IXGBE_CB(skb)->dma,
1833 offset,
1834 skb_headlen(skb),
1835 DMA_FROM_DEVICE);
1836 } else {
1837 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1838
1839 dma_sync_single_range_for_cpu(rx_ring->dev,
1840 IXGBE_CB(skb)->dma,
1841 skb_frag_off(frag),
1842 skb_frag_size(frag),
1843 DMA_FROM_DEVICE);
1844 }
1845
1846 /* If the page was released, just unmap it. */
1847 if (unlikely(IXGBE_CB(skb)->page_released)) {
1848 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
1849 ixgbe_rx_pg_size(rx_ring),
1850 DMA_FROM_DEVICE,
1851 IXGBE_RX_DMA_ATTR);
1852 }
1853 }
1854
1855 /**
1856 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1857 * @rx_ring: rx descriptor ring packet is being transacted on
1858 * @rx_desc: pointer to the EOP Rx descriptor
1859 * @skb: pointer to current skb being fixed
1860 *
1861 * Check if the skb is valid in the XDP case it will be an error pointer.
1862 * Return true in this case to abort processing and advance to next
1863 * descriptor.
1864 *
1865 * Check for corrupted packet headers caused by senders on the local L2
1866 * embedded NIC switch not setting up their Tx Descriptors right. These
1867 * should be very rare.
1868 *
1869 * Also address the case where we are pulling data in on pages only
1870 * and as such no data is present in the skb header.
1871 *
1872 * In addition if skb is not at least 60 bytes we need to pad it so that
1873 * it is large enough to qualify as a valid Ethernet frame.
1874 *
1875 * Returns true if an error was encountered and skb was freed.
1876 **/
ixgbe_cleanup_headers(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1877 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1878 union ixgbe_adv_rx_desc *rx_desc,
1879 struct sk_buff *skb)
1880 {
1881 struct net_device *netdev = rx_ring->netdev;
1882
1883 /* XDP packets use error pointer so abort at this point */
1884 if (IS_ERR(skb))
1885 return true;
1886
1887 /* Verify netdev is present, and that packet does not have any
1888 * errors that would be unacceptable to the netdev.
1889 */
1890 if (!netdev ||
1891 (unlikely(ixgbe_test_staterr(rx_desc,
1892 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1893 !(netdev->features & NETIF_F_RXALL)))) {
1894 dev_kfree_skb_any(skb);
1895 return true;
1896 }
1897
1898 /* place header in linear portion of buffer */
1899 if (!skb_headlen(skb))
1900 ixgbe_pull_tail(rx_ring, skb);
1901
1902 #ifdef IXGBE_FCOE
1903 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1904 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1905 return false;
1906
1907 #endif
1908 /* if eth_skb_pad returns an error the skb was freed */
1909 if (eth_skb_pad(skb))
1910 return true;
1911
1912 return false;
1913 }
1914
1915 /**
1916 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1917 * @rx_ring: rx descriptor ring to store buffers on
1918 * @old_buff: donor buffer to have page reused
1919 *
1920 * Synchronizes page for reuse by the adapter
1921 **/
ixgbe_reuse_rx_page(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * old_buff)1922 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1923 struct ixgbe_rx_buffer *old_buff)
1924 {
1925 struct ixgbe_rx_buffer *new_buff;
1926 u16 nta = rx_ring->next_to_alloc;
1927
1928 new_buff = &rx_ring->rx_buffer_info[nta];
1929
1930 /* update, and store next to alloc */
1931 nta++;
1932 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1933
1934 /* Transfer page from old buffer to new buffer.
1935 * Move each member individually to avoid possible store
1936 * forwarding stalls and unnecessary copy of skb.
1937 */
1938 new_buff->dma = old_buff->dma;
1939 new_buff->page = old_buff->page;
1940 new_buff->page_offset = old_buff->page_offset;
1941 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1942 }
1943
ixgbe_page_is_reserved(struct page * page)1944 static inline bool ixgbe_page_is_reserved(struct page *page)
1945 {
1946 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1947 }
1948
ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer * rx_buffer,int rx_buffer_pgcnt)1949 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer,
1950 int rx_buffer_pgcnt)
1951 {
1952 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1953 struct page *page = rx_buffer->page;
1954
1955 /* avoid re-using remote pages */
1956 if (unlikely(ixgbe_page_is_reserved(page)))
1957 return false;
1958
1959 #if (PAGE_SIZE < 8192)
1960 /* if we are only owner of page we can reuse it */
1961 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
1962 return false;
1963 #else
1964 /* The last offset is a bit aggressive in that we assume the
1965 * worst case of FCoE being enabled and using a 3K buffer.
1966 * However this should have minimal impact as the 1K extra is
1967 * still less than one buffer in size.
1968 */
1969 #define IXGBE_LAST_OFFSET \
1970 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K)
1971 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET)
1972 return false;
1973 #endif
1974
1975 /* If we have drained the page fragment pool we need to update
1976 * the pagecnt_bias and page count so that we fully restock the
1977 * number of references the driver holds.
1978 */
1979 if (unlikely(pagecnt_bias == 1)) {
1980 page_ref_add(page, USHRT_MAX - 1);
1981 rx_buffer->pagecnt_bias = USHRT_MAX;
1982 }
1983
1984 return true;
1985 }
1986
1987 /**
1988 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1989 * @rx_ring: rx descriptor ring to transact packets on
1990 * @rx_buffer: buffer containing page to add
1991 * @skb: sk_buff to place the data into
1992 * @size: size of data in rx_buffer
1993 *
1994 * This function will add the data contained in rx_buffer->page to the skb.
1995 * This is done either through a direct copy if the data in the buffer is
1996 * less than the skb header size, otherwise it will just attach the page as
1997 * a frag to the skb.
1998 *
1999 * The function will then update the page offset if necessary and return
2000 * true if the buffer can be reused by the adapter.
2001 **/
ixgbe_add_rx_frag(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,struct sk_buff * skb,unsigned int size)2002 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
2003 struct ixgbe_rx_buffer *rx_buffer,
2004 struct sk_buff *skb,
2005 unsigned int size)
2006 {
2007 #if (PAGE_SIZE < 8192)
2008 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2009 #else
2010 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
2011 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) :
2012 SKB_DATA_ALIGN(size);
2013 #endif
2014 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
2015 rx_buffer->page_offset, size, truesize);
2016 #if (PAGE_SIZE < 8192)
2017 rx_buffer->page_offset ^= truesize;
2018 #else
2019 rx_buffer->page_offset += truesize;
2020 #endif
2021 }
2022
ixgbe_get_rx_buffer(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff ** skb,const unsigned int size,int * rx_buffer_pgcnt)2023 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring,
2024 union ixgbe_adv_rx_desc *rx_desc,
2025 struct sk_buff **skb,
2026 const unsigned int size,
2027 int *rx_buffer_pgcnt)
2028 {
2029 struct ixgbe_rx_buffer *rx_buffer;
2030
2031 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2032 *rx_buffer_pgcnt =
2033 #if (PAGE_SIZE < 8192)
2034 page_count(rx_buffer->page);
2035 #else
2036 0;
2037 #endif
2038 prefetchw(rx_buffer->page);
2039 *skb = rx_buffer->skb;
2040
2041 /* Delay unmapping of the first packet. It carries the header
2042 * information, HW may still access the header after the writeback.
2043 * Only unmap it when EOP is reached
2044 */
2045 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) {
2046 if (!*skb)
2047 goto skip_sync;
2048 } else {
2049 if (*skb)
2050 ixgbe_dma_sync_frag(rx_ring, *skb);
2051 }
2052
2053 /* we are reusing so sync this buffer for CPU use */
2054 dma_sync_single_range_for_cpu(rx_ring->dev,
2055 rx_buffer->dma,
2056 rx_buffer->page_offset,
2057 size,
2058 DMA_FROM_DEVICE);
2059 skip_sync:
2060 rx_buffer->pagecnt_bias--;
2061
2062 return rx_buffer;
2063 }
2064
ixgbe_put_rx_buffer(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,struct sk_buff * skb,int rx_buffer_pgcnt)2065 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring,
2066 struct ixgbe_rx_buffer *rx_buffer,
2067 struct sk_buff *skb,
2068 int rx_buffer_pgcnt)
2069 {
2070 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
2071 /* hand second half of page back to the ring */
2072 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2073 } else {
2074 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) {
2075 /* the page has been released from the ring */
2076 IXGBE_CB(skb)->page_released = true;
2077 } else {
2078 /* we are not reusing the buffer so unmap it */
2079 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2080 ixgbe_rx_pg_size(rx_ring),
2081 DMA_FROM_DEVICE,
2082 IXGBE_RX_DMA_ATTR);
2083 }
2084 __page_frag_cache_drain(rx_buffer->page,
2085 rx_buffer->pagecnt_bias);
2086 }
2087
2088 /* clear contents of rx_buffer */
2089 rx_buffer->page = NULL;
2090 rx_buffer->skb = NULL;
2091 }
2092
ixgbe_construct_skb(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,struct xdp_buff * xdp,union ixgbe_adv_rx_desc * rx_desc)2093 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring,
2094 struct ixgbe_rx_buffer *rx_buffer,
2095 struct xdp_buff *xdp,
2096 union ixgbe_adv_rx_desc *rx_desc)
2097 {
2098 unsigned int size = xdp->data_end - xdp->data;
2099 #if (PAGE_SIZE < 8192)
2100 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2101 #else
2102 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
2103 xdp->data_hard_start);
2104 #endif
2105 struct sk_buff *skb;
2106
2107 /* prefetch first cache line of first page */
2108 net_prefetch(xdp->data);
2109
2110 /* Note, we get here by enabling legacy-rx via:
2111 *
2112 * ethtool --set-priv-flags <dev> legacy-rx on
2113 *
2114 * In this mode, we currently get 0 extra XDP headroom as
2115 * opposed to having legacy-rx off, where we process XDP
2116 * packets going to stack via ixgbe_build_skb(). The latter
2117 * provides us currently with 192 bytes of headroom.
2118 *
2119 * For ixgbe_construct_skb() mode it means that the
2120 * xdp->data_meta will always point to xdp->data, since
2121 * the helper cannot expand the head. Should this ever
2122 * change in future for legacy-rx mode on, then lets also
2123 * add xdp->data_meta handling here.
2124 */
2125
2126 /* allocate a skb to store the frags */
2127 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE);
2128 if (unlikely(!skb))
2129 return NULL;
2130
2131 if (size > IXGBE_RX_HDR_SIZE) {
2132 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2133 IXGBE_CB(skb)->dma = rx_buffer->dma;
2134
2135 skb_add_rx_frag(skb, 0, rx_buffer->page,
2136 xdp->data - page_address(rx_buffer->page),
2137 size, truesize);
2138 #if (PAGE_SIZE < 8192)
2139 rx_buffer->page_offset ^= truesize;
2140 #else
2141 rx_buffer->page_offset += truesize;
2142 #endif
2143 } else {
2144 memcpy(__skb_put(skb, size),
2145 xdp->data, ALIGN(size, sizeof(long)));
2146 rx_buffer->pagecnt_bias++;
2147 }
2148
2149 return skb;
2150 }
2151
ixgbe_build_skb(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,struct xdp_buff * xdp,union ixgbe_adv_rx_desc * rx_desc)2152 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring,
2153 struct ixgbe_rx_buffer *rx_buffer,
2154 struct xdp_buff *xdp,
2155 union ixgbe_adv_rx_desc *rx_desc)
2156 {
2157 unsigned int metasize = xdp->data - xdp->data_meta;
2158 #if (PAGE_SIZE < 8192)
2159 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2160 #else
2161 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2162 SKB_DATA_ALIGN(xdp->data_end -
2163 xdp->data_hard_start);
2164 #endif
2165 struct sk_buff *skb;
2166
2167 /* Prefetch first cache line of first page. If xdp->data_meta
2168 * is unused, this points extactly as xdp->data, otherwise we
2169 * likely have a consumer accessing first few bytes of meta
2170 * data, and then actual data.
2171 */
2172 net_prefetch(xdp->data_meta);
2173
2174 /* build an skb to around the page buffer */
2175 skb = build_skb(xdp->data_hard_start, truesize);
2176 if (unlikely(!skb))
2177 return NULL;
2178
2179 /* update pointers within the skb to store the data */
2180 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2181 __skb_put(skb, xdp->data_end - xdp->data);
2182 if (metasize)
2183 skb_metadata_set(skb, metasize);
2184
2185 /* record DMA address if this is the start of a chain of buffers */
2186 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2187 IXGBE_CB(skb)->dma = rx_buffer->dma;
2188
2189 /* update buffer offset */
2190 #if (PAGE_SIZE < 8192)
2191 rx_buffer->page_offset ^= truesize;
2192 #else
2193 rx_buffer->page_offset += truesize;
2194 #endif
2195
2196 return skb;
2197 }
2198
ixgbe_run_xdp(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring,struct xdp_buff * xdp)2199 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter,
2200 struct ixgbe_ring *rx_ring,
2201 struct xdp_buff *xdp)
2202 {
2203 int err, result = IXGBE_XDP_PASS;
2204 struct bpf_prog *xdp_prog;
2205 struct xdp_frame *xdpf;
2206 u32 act;
2207
2208 rcu_read_lock();
2209 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2210
2211 if (!xdp_prog)
2212 goto xdp_out;
2213
2214 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2215
2216 act = bpf_prog_run_xdp(xdp_prog, xdp);
2217 switch (act) {
2218 case XDP_PASS:
2219 break;
2220 case XDP_TX:
2221 xdpf = xdp_convert_buff_to_frame(xdp);
2222 if (unlikely(!xdpf))
2223 goto out_failure;
2224 result = ixgbe_xmit_xdp_ring(adapter, xdpf);
2225 if (result == IXGBE_XDP_CONSUMED)
2226 goto out_failure;
2227 break;
2228 case XDP_REDIRECT:
2229 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
2230 if (err)
2231 goto out_failure;
2232 result = IXGBE_XDP_REDIR;
2233 break;
2234 default:
2235 bpf_warn_invalid_xdp_action(act);
2236 fallthrough;
2237 case XDP_ABORTED:
2238 out_failure:
2239 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2240 fallthrough; /* handle aborts by dropping packet */
2241 case XDP_DROP:
2242 result = IXGBE_XDP_CONSUMED;
2243 break;
2244 }
2245 xdp_out:
2246 rcu_read_unlock();
2247 return ERR_PTR(-result);
2248 }
2249
ixgbe_rx_frame_truesize(struct ixgbe_ring * rx_ring,unsigned int size)2250 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring,
2251 unsigned int size)
2252 {
2253 unsigned int truesize;
2254
2255 #if (PAGE_SIZE < 8192)
2256 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
2257 #else
2258 truesize = ring_uses_build_skb(rx_ring) ?
2259 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) +
2260 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
2261 SKB_DATA_ALIGN(size);
2262 #endif
2263 return truesize;
2264 }
2265
ixgbe_rx_buffer_flip(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,unsigned int size)2266 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring,
2267 struct ixgbe_rx_buffer *rx_buffer,
2268 unsigned int size)
2269 {
2270 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size);
2271 #if (PAGE_SIZE < 8192)
2272 rx_buffer->page_offset ^= truesize;
2273 #else
2274 rx_buffer->page_offset += truesize;
2275 #endif
2276 }
2277
2278 /**
2279 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2280 * @q_vector: structure containing interrupt and ring information
2281 * @rx_ring: rx descriptor ring to transact packets on
2282 * @budget: Total limit on number of packets to process
2283 *
2284 * This function provides a "bounce buffer" approach to Rx interrupt
2285 * processing. The advantage to this is that on systems that have
2286 * expensive overhead for IOMMU access this provides a means of avoiding
2287 * it by maintaining the mapping of the page to the syste.
2288 *
2289 * Returns amount of work completed
2290 **/
ixgbe_clean_rx_irq(struct ixgbe_q_vector * q_vector,struct ixgbe_ring * rx_ring,const int budget)2291 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2292 struct ixgbe_ring *rx_ring,
2293 const int budget)
2294 {
2295 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2296 struct ixgbe_adapter *adapter = q_vector->adapter;
2297 #ifdef IXGBE_FCOE
2298 int ddp_bytes;
2299 unsigned int mss = 0;
2300 #endif /* IXGBE_FCOE */
2301 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2302 unsigned int xdp_xmit = 0;
2303 struct xdp_buff xdp;
2304
2305 xdp.rxq = &rx_ring->xdp_rxq;
2306
2307 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
2308 #if (PAGE_SIZE < 8192)
2309 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0);
2310 #endif
2311
2312 while (likely(total_rx_packets < budget)) {
2313 union ixgbe_adv_rx_desc *rx_desc;
2314 struct ixgbe_rx_buffer *rx_buffer;
2315 struct sk_buff *skb;
2316 int rx_buffer_pgcnt;
2317 unsigned int size;
2318
2319 /* return some buffers to hardware, one at a time is too slow */
2320 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2321 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2322 cleaned_count = 0;
2323 }
2324
2325 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2326 size = le16_to_cpu(rx_desc->wb.upper.length);
2327 if (!size)
2328 break;
2329
2330 /* This memory barrier is needed to keep us from reading
2331 * any other fields out of the rx_desc until we know the
2332 * descriptor has been written back
2333 */
2334 dma_rmb();
2335
2336 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt);
2337
2338 /* retrieve a buffer from the ring */
2339 if (!skb) {
2340 xdp.data = page_address(rx_buffer->page) +
2341 rx_buffer->page_offset;
2342 xdp.data_meta = xdp.data;
2343 xdp.data_hard_start = xdp.data -
2344 ixgbe_rx_offset(rx_ring);
2345 xdp.data_end = xdp.data + size;
2346 #if (PAGE_SIZE > 4096)
2347 /* At larger PAGE_SIZE, frame_sz depend on len size */
2348 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size);
2349 #endif
2350 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp);
2351 }
2352
2353 if (IS_ERR(skb)) {
2354 unsigned int xdp_res = -PTR_ERR(skb);
2355
2356 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) {
2357 xdp_xmit |= xdp_res;
2358 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size);
2359 } else {
2360 rx_buffer->pagecnt_bias++;
2361 }
2362 total_rx_packets++;
2363 total_rx_bytes += size;
2364 } else if (skb) {
2365 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size);
2366 } else if (ring_uses_build_skb(rx_ring)) {
2367 skb = ixgbe_build_skb(rx_ring, rx_buffer,
2368 &xdp, rx_desc);
2369 } else {
2370 skb = ixgbe_construct_skb(rx_ring, rx_buffer,
2371 &xdp, rx_desc);
2372 }
2373
2374 /* exit if we failed to retrieve a buffer */
2375 if (!skb) {
2376 rx_ring->rx_stats.alloc_rx_buff_failed++;
2377 rx_buffer->pagecnt_bias++;
2378 break;
2379 }
2380
2381 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt);
2382 cleaned_count++;
2383
2384 /* place incomplete frames back on ring for completion */
2385 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2386 continue;
2387
2388 /* verify the packet layout is correct */
2389 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2390 continue;
2391
2392 /* probably a little skewed due to removing CRC */
2393 total_rx_bytes += skb->len;
2394
2395 /* populate checksum, timestamp, VLAN, and protocol */
2396 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2397
2398 #ifdef IXGBE_FCOE
2399 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2400 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2401 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2402 /* include DDPed FCoE data */
2403 if (ddp_bytes > 0) {
2404 if (!mss) {
2405 mss = rx_ring->netdev->mtu -
2406 sizeof(struct fcoe_hdr) -
2407 sizeof(struct fc_frame_header) -
2408 sizeof(struct fcoe_crc_eof);
2409 if (mss > 512)
2410 mss &= ~511;
2411 }
2412 total_rx_bytes += ddp_bytes;
2413 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2414 mss);
2415 }
2416 if (!ddp_bytes) {
2417 dev_kfree_skb_any(skb);
2418 continue;
2419 }
2420 }
2421
2422 #endif /* IXGBE_FCOE */
2423 ixgbe_rx_skb(q_vector, skb);
2424
2425 /* update budget accounting */
2426 total_rx_packets++;
2427 }
2428
2429 if (xdp_xmit & IXGBE_XDP_REDIR)
2430 xdp_do_flush_map();
2431
2432 if (xdp_xmit & IXGBE_XDP_TX) {
2433 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
2434
2435 /* Force memory writes to complete before letting h/w
2436 * know there are new descriptors to fetch.
2437 */
2438 wmb();
2439 writel(ring->next_to_use, ring->tail);
2440 }
2441
2442 u64_stats_update_begin(&rx_ring->syncp);
2443 rx_ring->stats.packets += total_rx_packets;
2444 rx_ring->stats.bytes += total_rx_bytes;
2445 u64_stats_update_end(&rx_ring->syncp);
2446 q_vector->rx.total_packets += total_rx_packets;
2447 q_vector->rx.total_bytes += total_rx_bytes;
2448
2449 return total_rx_packets;
2450 }
2451
2452 /**
2453 * ixgbe_configure_msix - Configure MSI-X hardware
2454 * @adapter: board private structure
2455 *
2456 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2457 * interrupts.
2458 **/
ixgbe_configure_msix(struct ixgbe_adapter * adapter)2459 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2460 {
2461 struct ixgbe_q_vector *q_vector;
2462 int v_idx;
2463 u32 mask;
2464
2465 /* Populate MSIX to EITR Select */
2466 if (adapter->num_vfs > 32) {
2467 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
2468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2469 }
2470
2471 /*
2472 * Populate the IVAR table and set the ITR values to the
2473 * corresponding register.
2474 */
2475 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2476 struct ixgbe_ring *ring;
2477 q_vector = adapter->q_vector[v_idx];
2478
2479 ixgbe_for_each_ring(ring, q_vector->rx)
2480 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2481
2482 ixgbe_for_each_ring(ring, q_vector->tx)
2483 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2484
2485 ixgbe_write_eitr(q_vector);
2486 }
2487
2488 switch (adapter->hw.mac.type) {
2489 case ixgbe_mac_82598EB:
2490 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2491 v_idx);
2492 break;
2493 case ixgbe_mac_82599EB:
2494 case ixgbe_mac_X540:
2495 case ixgbe_mac_X550:
2496 case ixgbe_mac_X550EM_x:
2497 case ixgbe_mac_x550em_a:
2498 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2499 break;
2500 default:
2501 break;
2502 }
2503 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2504
2505 /* set up to autoclear timer, and the vectors */
2506 mask = IXGBE_EIMS_ENABLE_MASK;
2507 mask &= ~(IXGBE_EIMS_OTHER |
2508 IXGBE_EIMS_MAILBOX |
2509 IXGBE_EIMS_LSC);
2510
2511 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2512 }
2513
2514 /**
2515 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2516 * @q_vector: structure containing interrupt and ring information
2517 * @ring_container: structure containing ring performance data
2518 *
2519 * Stores a new ITR value based on packets and byte
2520 * counts during the last interrupt. The advantage of per interrupt
2521 * computation is faster updates and more accurate ITR for the current
2522 * traffic pattern. Constants in this function were computed
2523 * based on theoretical maximum wire speed and thresholds were set based
2524 * on testing data as well as attempting to minimize response time
2525 * while increasing bulk throughput.
2526 **/
ixgbe_update_itr(struct ixgbe_q_vector * q_vector,struct ixgbe_ring_container * ring_container)2527 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2528 struct ixgbe_ring_container *ring_container)
2529 {
2530 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS |
2531 IXGBE_ITR_ADAPTIVE_LATENCY;
2532 unsigned int avg_wire_size, packets, bytes;
2533 unsigned long next_update = jiffies;
2534
2535 /* If we don't have any rings just leave ourselves set for maximum
2536 * possible latency so we take ourselves out of the equation.
2537 */
2538 if (!ring_container->ring)
2539 return;
2540
2541 /* If we didn't update within up to 1 - 2 jiffies we can assume
2542 * that either packets are coming in so slow there hasn't been
2543 * any work, or that there is so much work that NAPI is dealing
2544 * with interrupt moderation and we don't need to do anything.
2545 */
2546 if (time_after(next_update, ring_container->next_update))
2547 goto clear_counts;
2548
2549 packets = ring_container->total_packets;
2550
2551 /* We have no packets to actually measure against. This means
2552 * either one of the other queues on this vector is active or
2553 * we are a Tx queue doing TSO with too high of an interrupt rate.
2554 *
2555 * When this occurs just tick up our delay by the minimum value
2556 * and hope that this extra delay will prevent us from being called
2557 * without any work on our queue.
2558 */
2559 if (!packets) {
2560 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2561 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2562 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2563 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY;
2564 goto clear_counts;
2565 }
2566
2567 bytes = ring_container->total_bytes;
2568
2569 /* If packets are less than 4 or bytes are less than 9000 assume
2570 * insufficient data to use bulk rate limiting approach. We are
2571 * likely latency driven.
2572 */
2573 if (packets < 4 && bytes < 9000) {
2574 itr = IXGBE_ITR_ADAPTIVE_LATENCY;
2575 goto adjust_by_size;
2576 }
2577
2578 /* Between 4 and 48 we can assume that our current interrupt delay
2579 * is only slightly too low. As such we should increase it by a small
2580 * fixed amount.
2581 */
2582 if (packets < 48) {
2583 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2584 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2585 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2586 goto clear_counts;
2587 }
2588
2589 /* Between 48 and 96 is our "goldilocks" zone where we are working
2590 * out "just right". Just report that our current ITR is good for us.
2591 */
2592 if (packets < 96) {
2593 itr = q_vector->itr >> 2;
2594 goto clear_counts;
2595 }
2596
2597 /* If packet count is 96 or greater we are likely looking at a slight
2598 * overrun of the delay we want. Try halving our delay to see if that
2599 * will cut the number of packets in half per interrupt.
2600 */
2601 if (packets < 256) {
2602 itr = q_vector->itr >> 3;
2603 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS)
2604 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS;
2605 goto clear_counts;
2606 }
2607
2608 /* The paths below assume we are dealing with a bulk ITR since number
2609 * of packets is 256 or greater. We are just going to have to compute
2610 * a value and try to bring the count under control, though for smaller
2611 * packet sizes there isn't much we can do as NAPI polling will likely
2612 * be kicking in sooner rather than later.
2613 */
2614 itr = IXGBE_ITR_ADAPTIVE_BULK;
2615
2616 adjust_by_size:
2617 /* If packet counts are 256 or greater we can assume we have a gross
2618 * overestimation of what the rate should be. Instead of trying to fine
2619 * tune it just use the formula below to try and dial in an exact value
2620 * give the current packet size of the frame.
2621 */
2622 avg_wire_size = bytes / packets;
2623
2624 /* The following is a crude approximation of:
2625 * wmem_default / (size + overhead) = desired_pkts_per_int
2626 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
2627 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
2628 *
2629 * Assuming wmem_default is 212992 and overhead is 640 bytes per
2630 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
2631 * formula down to
2632 *
2633 * (170 * (size + 24)) / (size + 640) = ITR
2634 *
2635 * We first do some math on the packet size and then finally bitshift
2636 * by 8 after rounding up. We also have to account for PCIe link speed
2637 * difference as ITR scales based on this.
2638 */
2639 if (avg_wire_size <= 60) {
2640 /* Start at 50k ints/sec */
2641 avg_wire_size = 5120;
2642 } else if (avg_wire_size <= 316) {
2643 /* 50K ints/sec to 16K ints/sec */
2644 avg_wire_size *= 40;
2645 avg_wire_size += 2720;
2646 } else if (avg_wire_size <= 1084) {
2647 /* 16K ints/sec to 9.2K ints/sec */
2648 avg_wire_size *= 15;
2649 avg_wire_size += 11452;
2650 } else if (avg_wire_size < 1968) {
2651 /* 9.2K ints/sec to 8K ints/sec */
2652 avg_wire_size *= 5;
2653 avg_wire_size += 22420;
2654 } else {
2655 /* plateau at a limit of 8K ints/sec */
2656 avg_wire_size = 32256;
2657 }
2658
2659 /* If we are in low latency mode half our delay which doubles the rate
2660 * to somewhere between 100K to 16K ints/sec
2661 */
2662 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY)
2663 avg_wire_size >>= 1;
2664
2665 /* Resultant value is 256 times larger than it needs to be. This
2666 * gives us room to adjust the value as needed to either increase
2667 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
2668 *
2669 * Use addition as we have already recorded the new latency flag
2670 * for the ITR value.
2671 */
2672 switch (q_vector->adapter->link_speed) {
2673 case IXGBE_LINK_SPEED_10GB_FULL:
2674 case IXGBE_LINK_SPEED_100_FULL:
2675 default:
2676 itr += DIV_ROUND_UP(avg_wire_size,
2677 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) *
2678 IXGBE_ITR_ADAPTIVE_MIN_INC;
2679 break;
2680 case IXGBE_LINK_SPEED_2_5GB_FULL:
2681 case IXGBE_LINK_SPEED_1GB_FULL:
2682 case IXGBE_LINK_SPEED_10_FULL:
2683 if (avg_wire_size > 8064)
2684 avg_wire_size = 8064;
2685 itr += DIV_ROUND_UP(avg_wire_size,
2686 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) *
2687 IXGBE_ITR_ADAPTIVE_MIN_INC;
2688 break;
2689 }
2690
2691 clear_counts:
2692 /* write back value */
2693 ring_container->itr = itr;
2694
2695 /* next update should occur within next jiffy */
2696 ring_container->next_update = next_update + 1;
2697
2698 ring_container->total_bytes = 0;
2699 ring_container->total_packets = 0;
2700 }
2701
2702 /**
2703 * ixgbe_write_eitr - write EITR register in hardware specific way
2704 * @q_vector: structure containing interrupt and ring information
2705 *
2706 * This function is made to be called by ethtool and by the driver
2707 * when it needs to update EITR registers at runtime. Hardware
2708 * specific quirks/differences are taken care of here.
2709 */
ixgbe_write_eitr(struct ixgbe_q_vector * q_vector)2710 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2711 {
2712 struct ixgbe_adapter *adapter = q_vector->adapter;
2713 struct ixgbe_hw *hw = &adapter->hw;
2714 int v_idx = q_vector->v_idx;
2715 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2716
2717 switch (adapter->hw.mac.type) {
2718 case ixgbe_mac_82598EB:
2719 /* must write high and low 16 bits to reset counter */
2720 itr_reg |= (itr_reg << 16);
2721 break;
2722 case ixgbe_mac_82599EB:
2723 case ixgbe_mac_X540:
2724 case ixgbe_mac_X550:
2725 case ixgbe_mac_X550EM_x:
2726 case ixgbe_mac_x550em_a:
2727 /*
2728 * set the WDIS bit to not clear the timer bits and cause an
2729 * immediate assertion of the interrupt
2730 */
2731 itr_reg |= IXGBE_EITR_CNT_WDIS;
2732 break;
2733 default:
2734 break;
2735 }
2736 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2737 }
2738
ixgbe_set_itr(struct ixgbe_q_vector * q_vector)2739 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2740 {
2741 u32 new_itr;
2742
2743 ixgbe_update_itr(q_vector, &q_vector->tx);
2744 ixgbe_update_itr(q_vector, &q_vector->rx);
2745
2746 /* use the smallest value of new ITR delay calculations */
2747 new_itr = min(q_vector->rx.itr, q_vector->tx.itr);
2748
2749 /* Clear latency flag if set, shift into correct position */
2750 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY;
2751 new_itr <<= 2;
2752
2753 if (new_itr != q_vector->itr) {
2754 /* save the algorithm value here */
2755 q_vector->itr = new_itr;
2756
2757 ixgbe_write_eitr(q_vector);
2758 }
2759 }
2760
2761 /**
2762 * ixgbe_check_overtemp_subtask - check for over temperature
2763 * @adapter: pointer to adapter
2764 **/
ixgbe_check_overtemp_subtask(struct ixgbe_adapter * adapter)2765 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2766 {
2767 struct ixgbe_hw *hw = &adapter->hw;
2768 u32 eicr = adapter->interrupt_event;
2769 s32 rc;
2770
2771 if (test_bit(__IXGBE_DOWN, &adapter->state))
2772 return;
2773
2774 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2775 return;
2776
2777 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2778
2779 switch (hw->device_id) {
2780 case IXGBE_DEV_ID_82599_T3_LOM:
2781 /*
2782 * Since the warning interrupt is for both ports
2783 * we don't have to check if:
2784 * - This interrupt wasn't for our port.
2785 * - We may have missed the interrupt so always have to
2786 * check if we got a LSC
2787 */
2788 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2789 !(eicr & IXGBE_EICR_LSC))
2790 return;
2791
2792 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2793 u32 speed;
2794 bool link_up = false;
2795
2796 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2797
2798 if (link_up)
2799 return;
2800 }
2801
2802 /* Check if this is not due to overtemp */
2803 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2804 return;
2805
2806 break;
2807 case IXGBE_DEV_ID_X550EM_A_1G_T:
2808 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2809 rc = hw->phy.ops.check_overtemp(hw);
2810 if (rc != IXGBE_ERR_OVERTEMP)
2811 return;
2812 break;
2813 default:
2814 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2815 return;
2816 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2817 return;
2818 break;
2819 }
2820 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2821
2822 adapter->interrupt_event = 0;
2823 }
2824
ixgbe_check_fan_failure(struct ixgbe_adapter * adapter,u32 eicr)2825 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2826 {
2827 struct ixgbe_hw *hw = &adapter->hw;
2828
2829 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2830 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2831 e_crit(probe, "Fan has stopped, replace the adapter\n");
2832 /* write to clear the interrupt */
2833 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2834 }
2835 }
2836
ixgbe_check_overtemp_event(struct ixgbe_adapter * adapter,u32 eicr)2837 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2838 {
2839 struct ixgbe_hw *hw = &adapter->hw;
2840
2841 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2842 return;
2843
2844 switch (adapter->hw.mac.type) {
2845 case ixgbe_mac_82599EB:
2846 /*
2847 * Need to check link state so complete overtemp check
2848 * on service task
2849 */
2850 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2851 (eicr & IXGBE_EICR_LSC)) &&
2852 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2853 adapter->interrupt_event = eicr;
2854 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2855 ixgbe_service_event_schedule(adapter);
2856 return;
2857 }
2858 return;
2859 case ixgbe_mac_x550em_a:
2860 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) {
2861 adapter->interrupt_event = eicr;
2862 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2863 ixgbe_service_event_schedule(adapter);
2864 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
2865 IXGBE_EICR_GPI_SDP0_X550EM_a);
2866 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR,
2867 IXGBE_EICR_GPI_SDP0_X550EM_a);
2868 }
2869 return;
2870 case ixgbe_mac_X550:
2871 case ixgbe_mac_X540:
2872 if (!(eicr & IXGBE_EICR_TS))
2873 return;
2874 break;
2875 default:
2876 return;
2877 }
2878
2879 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2880 }
2881
ixgbe_is_sfp(struct ixgbe_hw * hw)2882 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2883 {
2884 switch (hw->mac.type) {
2885 case ixgbe_mac_82598EB:
2886 if (hw->phy.type == ixgbe_phy_nl)
2887 return true;
2888 return false;
2889 case ixgbe_mac_82599EB:
2890 case ixgbe_mac_X550EM_x:
2891 case ixgbe_mac_x550em_a:
2892 switch (hw->mac.ops.get_media_type(hw)) {
2893 case ixgbe_media_type_fiber:
2894 case ixgbe_media_type_fiber_qsfp:
2895 return true;
2896 default:
2897 return false;
2898 }
2899 default:
2900 return false;
2901 }
2902 }
2903
ixgbe_check_sfp_event(struct ixgbe_adapter * adapter,u32 eicr)2904 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2905 {
2906 struct ixgbe_hw *hw = &adapter->hw;
2907 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2908
2909 if (!ixgbe_is_sfp(hw))
2910 return;
2911
2912 /* Later MAC's use different SDP */
2913 if (hw->mac.type >= ixgbe_mac_X540)
2914 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2915
2916 if (eicr & eicr_mask) {
2917 /* Clear the interrupt */
2918 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2919 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2920 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2921 adapter->sfp_poll_time = 0;
2922 ixgbe_service_event_schedule(adapter);
2923 }
2924 }
2925
2926 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2927 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2928 /* Clear the interrupt */
2929 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2930 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2931 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2932 ixgbe_service_event_schedule(adapter);
2933 }
2934 }
2935 }
2936
ixgbe_check_lsc(struct ixgbe_adapter * adapter)2937 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2938 {
2939 struct ixgbe_hw *hw = &adapter->hw;
2940
2941 adapter->lsc_int++;
2942 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2943 adapter->link_check_timeout = jiffies;
2944 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2945 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2946 IXGBE_WRITE_FLUSH(hw);
2947 ixgbe_service_event_schedule(adapter);
2948 }
2949 }
2950
ixgbe_irq_enable_queues(struct ixgbe_adapter * adapter,u64 qmask)2951 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2952 u64 qmask)
2953 {
2954 u32 mask;
2955 struct ixgbe_hw *hw = &adapter->hw;
2956
2957 switch (hw->mac.type) {
2958 case ixgbe_mac_82598EB:
2959 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2960 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2961 break;
2962 case ixgbe_mac_82599EB:
2963 case ixgbe_mac_X540:
2964 case ixgbe_mac_X550:
2965 case ixgbe_mac_X550EM_x:
2966 case ixgbe_mac_x550em_a:
2967 mask = (qmask & 0xFFFFFFFF);
2968 if (mask)
2969 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2970 mask = (qmask >> 32);
2971 if (mask)
2972 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2973 break;
2974 default:
2975 break;
2976 }
2977 /* skip the flush */
2978 }
2979
2980 /**
2981 * ixgbe_irq_enable - Enable default interrupt generation settings
2982 * @adapter: board private structure
2983 * @queues: enable irqs for queues
2984 * @flush: flush register write
2985 **/
ixgbe_irq_enable(struct ixgbe_adapter * adapter,bool queues,bool flush)2986 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2987 bool flush)
2988 {
2989 struct ixgbe_hw *hw = &adapter->hw;
2990 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2991
2992 /* don't reenable LSC while waiting for link */
2993 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2994 mask &= ~IXGBE_EIMS_LSC;
2995
2996 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2997 switch (adapter->hw.mac.type) {
2998 case ixgbe_mac_82599EB:
2999 mask |= IXGBE_EIMS_GPI_SDP0(hw);
3000 break;
3001 case ixgbe_mac_X540:
3002 case ixgbe_mac_X550:
3003 case ixgbe_mac_X550EM_x:
3004 case ixgbe_mac_x550em_a:
3005 mask |= IXGBE_EIMS_TS;
3006 break;
3007 default:
3008 break;
3009 }
3010 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3011 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3012 switch (adapter->hw.mac.type) {
3013 case ixgbe_mac_82599EB:
3014 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3015 mask |= IXGBE_EIMS_GPI_SDP2(hw);
3016 fallthrough;
3017 case ixgbe_mac_X540:
3018 case ixgbe_mac_X550:
3019 case ixgbe_mac_X550EM_x:
3020 case ixgbe_mac_x550em_a:
3021 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
3022 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
3023 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
3024 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
3025 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
3026 mask |= IXGBE_EICR_GPI_SDP0_X540;
3027 mask |= IXGBE_EIMS_ECC;
3028 mask |= IXGBE_EIMS_MAILBOX;
3029 break;
3030 default:
3031 break;
3032 }
3033
3034 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
3035 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
3036 mask |= IXGBE_EIMS_FLOW_DIR;
3037
3038 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
3039 if (queues)
3040 ixgbe_irq_enable_queues(adapter, ~0);
3041 if (flush)
3042 IXGBE_WRITE_FLUSH(&adapter->hw);
3043 }
3044
ixgbe_msix_other(int irq,void * data)3045 static irqreturn_t ixgbe_msix_other(int irq, void *data)
3046 {
3047 struct ixgbe_adapter *adapter = data;
3048 struct ixgbe_hw *hw = &adapter->hw;
3049 u32 eicr;
3050
3051 /*
3052 * Workaround for Silicon errata. Use clear-by-write instead
3053 * of clear-by-read. Reading with EICS will return the
3054 * interrupt causes without clearing, which later be done
3055 * with the write to EICR.
3056 */
3057 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
3058
3059 /* The lower 16bits of the EICR register are for the queue interrupts
3060 * which should be masked here in order to not accidentally clear them if
3061 * the bits are high when ixgbe_msix_other is called. There is a race
3062 * condition otherwise which results in possible performance loss
3063 * especially if the ixgbe_msix_other interrupt is triggering
3064 * consistently (as it would when PPS is turned on for the X540 device)
3065 */
3066 eicr &= 0xFFFF0000;
3067
3068 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3069
3070 if (eicr & IXGBE_EICR_LSC)
3071 ixgbe_check_lsc(adapter);
3072
3073 if (eicr & IXGBE_EICR_MAILBOX)
3074 ixgbe_msg_task(adapter);
3075
3076 switch (hw->mac.type) {
3077 case ixgbe_mac_82599EB:
3078 case ixgbe_mac_X540:
3079 case ixgbe_mac_X550:
3080 case ixgbe_mac_X550EM_x:
3081 case ixgbe_mac_x550em_a:
3082 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
3083 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
3084 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
3085 ixgbe_service_event_schedule(adapter);
3086 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3087 IXGBE_EICR_GPI_SDP0_X540);
3088 }
3089 if (eicr & IXGBE_EICR_ECC) {
3090 e_info(link, "Received ECC Err, initiating reset\n");
3091 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3092 ixgbe_service_event_schedule(adapter);
3093 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3094 }
3095 /* Handle Flow Director Full threshold interrupt */
3096 if (eicr & IXGBE_EICR_FLOW_DIR) {
3097 int reinit_count = 0;
3098 int i;
3099 for (i = 0; i < adapter->num_tx_queues; i++) {
3100 struct ixgbe_ring *ring = adapter->tx_ring[i];
3101 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
3102 &ring->state))
3103 reinit_count++;
3104 }
3105 if (reinit_count) {
3106 /* no more flow director interrupts until after init */
3107 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
3108 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
3109 ixgbe_service_event_schedule(adapter);
3110 }
3111 }
3112 ixgbe_check_sfp_event(adapter, eicr);
3113 ixgbe_check_overtemp_event(adapter, eicr);
3114 break;
3115 default:
3116 break;
3117 }
3118
3119 ixgbe_check_fan_failure(adapter, eicr);
3120
3121 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3122 ixgbe_ptp_check_pps_event(adapter);
3123
3124 /* re-enable the original interrupt state, no lsc, no queues */
3125 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3126 ixgbe_irq_enable(adapter, false, false);
3127
3128 return IRQ_HANDLED;
3129 }
3130
ixgbe_msix_clean_rings(int irq,void * data)3131 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
3132 {
3133 struct ixgbe_q_vector *q_vector = data;
3134
3135 /* EIAM disabled interrupts (on this vector) for us */
3136
3137 if (q_vector->rx.ring || q_vector->tx.ring)
3138 napi_schedule_irqoff(&q_vector->napi);
3139
3140 return IRQ_HANDLED;
3141 }
3142
3143 /**
3144 * ixgbe_poll - NAPI Rx polling callback
3145 * @napi: structure for representing this polling device
3146 * @budget: how many packets driver is allowed to clean
3147 *
3148 * This function is used for legacy and MSI, NAPI mode
3149 **/
ixgbe_poll(struct napi_struct * napi,int budget)3150 int ixgbe_poll(struct napi_struct *napi, int budget)
3151 {
3152 struct ixgbe_q_vector *q_vector =
3153 container_of(napi, struct ixgbe_q_vector, napi);
3154 struct ixgbe_adapter *adapter = q_vector->adapter;
3155 struct ixgbe_ring *ring;
3156 int per_ring_budget, work_done = 0;
3157 bool clean_complete = true;
3158
3159 #ifdef CONFIG_IXGBE_DCA
3160 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3161 ixgbe_update_dca(q_vector);
3162 #endif
3163
3164 ixgbe_for_each_ring(ring, q_vector->tx) {
3165 bool wd = ring->xsk_pool ?
3166 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) :
3167 ixgbe_clean_tx_irq(q_vector, ring, budget);
3168
3169 if (!wd)
3170 clean_complete = false;
3171 }
3172
3173 /* Exit if we are called by netpoll */
3174 if (budget <= 0)
3175 return budget;
3176
3177 /* attempt to distribute budget to each queue fairly, but don't allow
3178 * the budget to go below 1 because we'll exit polling */
3179 if (q_vector->rx.count > 1)
3180 per_ring_budget = max(budget/q_vector->rx.count, 1);
3181 else
3182 per_ring_budget = budget;
3183
3184 ixgbe_for_each_ring(ring, q_vector->rx) {
3185 int cleaned = ring->xsk_pool ?
3186 ixgbe_clean_rx_irq_zc(q_vector, ring,
3187 per_ring_budget) :
3188 ixgbe_clean_rx_irq(q_vector, ring,
3189 per_ring_budget);
3190
3191 work_done += cleaned;
3192 if (cleaned >= per_ring_budget)
3193 clean_complete = false;
3194 }
3195
3196 /* If all work not completed, return budget and keep polling */
3197 if (!clean_complete)
3198 return budget;
3199
3200 /* all work done, exit the polling mode */
3201 if (likely(napi_complete_done(napi, work_done))) {
3202 if (adapter->rx_itr_setting & 1)
3203 ixgbe_set_itr(q_vector);
3204 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3205 ixgbe_irq_enable_queues(adapter,
3206 BIT_ULL(q_vector->v_idx));
3207 }
3208
3209 return min(work_done, budget - 1);
3210 }
3211
3212 /**
3213 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
3214 * @adapter: board private structure
3215 *
3216 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
3217 * interrupts from the kernel.
3218 **/
ixgbe_request_msix_irqs(struct ixgbe_adapter * adapter)3219 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
3220 {
3221 struct net_device *netdev = adapter->netdev;
3222 unsigned int ri = 0, ti = 0;
3223 int vector, err;
3224
3225 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3226 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3227 struct msix_entry *entry = &adapter->msix_entries[vector];
3228
3229 if (q_vector->tx.ring && q_vector->rx.ring) {
3230 snprintf(q_vector->name, sizeof(q_vector->name),
3231 "%s-TxRx-%u", netdev->name, ri++);
3232 ti++;
3233 } else if (q_vector->rx.ring) {
3234 snprintf(q_vector->name, sizeof(q_vector->name),
3235 "%s-rx-%u", netdev->name, ri++);
3236 } else if (q_vector->tx.ring) {
3237 snprintf(q_vector->name, sizeof(q_vector->name),
3238 "%s-tx-%u", netdev->name, ti++);
3239 } else {
3240 /* skip this unused q_vector */
3241 continue;
3242 }
3243 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
3244 q_vector->name, q_vector);
3245 if (err) {
3246 e_err(probe, "request_irq failed for MSIX interrupt "
3247 "Error: %d\n", err);
3248 goto free_queue_irqs;
3249 }
3250 /* If Flow Director is enabled, set interrupt affinity */
3251 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3252 /* assign the mask for this irq */
3253 irq_set_affinity_hint(entry->vector,
3254 &q_vector->affinity_mask);
3255 }
3256 }
3257
3258 err = request_irq(adapter->msix_entries[vector].vector,
3259 ixgbe_msix_other, 0, netdev->name, adapter);
3260 if (err) {
3261 e_err(probe, "request_irq for msix_other failed: %d\n", err);
3262 goto free_queue_irqs;
3263 }
3264
3265 return 0;
3266
3267 free_queue_irqs:
3268 while (vector) {
3269 vector--;
3270 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
3271 NULL);
3272 free_irq(adapter->msix_entries[vector].vector,
3273 adapter->q_vector[vector]);
3274 }
3275 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3276 pci_disable_msix(adapter->pdev);
3277 kfree(adapter->msix_entries);
3278 adapter->msix_entries = NULL;
3279 return err;
3280 }
3281
3282 /**
3283 * ixgbe_intr - legacy mode Interrupt Handler
3284 * @irq: interrupt number
3285 * @data: pointer to a network interface device structure
3286 **/
ixgbe_intr(int irq,void * data)3287 static irqreturn_t ixgbe_intr(int irq, void *data)
3288 {
3289 struct ixgbe_adapter *adapter = data;
3290 struct ixgbe_hw *hw = &adapter->hw;
3291 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3292 u32 eicr;
3293
3294 /*
3295 * Workaround for silicon errata #26 on 82598. Mask the interrupt
3296 * before the read of EICR.
3297 */
3298 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
3299
3300 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
3301 * therefore no explicit interrupt disable is necessary */
3302 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3303 if (!eicr) {
3304 /*
3305 * shared interrupt alert!
3306 * make sure interrupts are enabled because the read will
3307 * have disabled interrupts due to EIAM
3308 * finish the workaround of silicon errata on 82598. Unmask
3309 * the interrupt that we masked before the EICR read.
3310 */
3311 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3312 ixgbe_irq_enable(adapter, true, true);
3313 return IRQ_NONE; /* Not our interrupt */
3314 }
3315
3316 if (eicr & IXGBE_EICR_LSC)
3317 ixgbe_check_lsc(adapter);
3318
3319 switch (hw->mac.type) {
3320 case ixgbe_mac_82599EB:
3321 ixgbe_check_sfp_event(adapter, eicr);
3322 fallthrough;
3323 case ixgbe_mac_X540:
3324 case ixgbe_mac_X550:
3325 case ixgbe_mac_X550EM_x:
3326 case ixgbe_mac_x550em_a:
3327 if (eicr & IXGBE_EICR_ECC) {
3328 e_info(link, "Received ECC Err, initiating reset\n");
3329 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3330 ixgbe_service_event_schedule(adapter);
3331 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3332 }
3333 ixgbe_check_overtemp_event(adapter, eicr);
3334 break;
3335 default:
3336 break;
3337 }
3338
3339 ixgbe_check_fan_failure(adapter, eicr);
3340 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3341 ixgbe_ptp_check_pps_event(adapter);
3342
3343 /* would disable interrupts here but EIAM disabled it */
3344 napi_schedule_irqoff(&q_vector->napi);
3345
3346 /*
3347 * re-enable link(maybe) and non-queue interrupts, no flush.
3348 * ixgbe_poll will re-enable the queue interrupts
3349 */
3350 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3351 ixgbe_irq_enable(adapter, false, false);
3352
3353 return IRQ_HANDLED;
3354 }
3355
3356 /**
3357 * ixgbe_request_irq - initialize interrupts
3358 * @adapter: board private structure
3359 *
3360 * Attempts to configure interrupts using the best available
3361 * capabilities of the hardware and kernel.
3362 **/
ixgbe_request_irq(struct ixgbe_adapter * adapter)3363 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
3364 {
3365 struct net_device *netdev = adapter->netdev;
3366 int err;
3367
3368 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3369 err = ixgbe_request_msix_irqs(adapter);
3370 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
3371 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
3372 netdev->name, adapter);
3373 else
3374 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
3375 netdev->name, adapter);
3376
3377 if (err)
3378 e_err(probe, "request_irq failed, Error %d\n", err);
3379
3380 return err;
3381 }
3382
ixgbe_free_irq(struct ixgbe_adapter * adapter)3383 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3384 {
3385 int vector;
3386
3387 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3388 free_irq(adapter->pdev->irq, adapter);
3389 return;
3390 }
3391
3392 if (!adapter->msix_entries)
3393 return;
3394
3395 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3396 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3397 struct msix_entry *entry = &adapter->msix_entries[vector];
3398
3399 /* free only the irqs that were actually requested */
3400 if (!q_vector->rx.ring && !q_vector->tx.ring)
3401 continue;
3402
3403 /* clear the affinity_mask in the IRQ descriptor */
3404 irq_set_affinity_hint(entry->vector, NULL);
3405
3406 free_irq(entry->vector, q_vector);
3407 }
3408
3409 free_irq(adapter->msix_entries[vector].vector, adapter);
3410 }
3411
3412 /**
3413 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3414 * @adapter: board private structure
3415 **/
ixgbe_irq_disable(struct ixgbe_adapter * adapter)3416 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3417 {
3418 switch (adapter->hw.mac.type) {
3419 case ixgbe_mac_82598EB:
3420 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3421 break;
3422 case ixgbe_mac_82599EB:
3423 case ixgbe_mac_X540:
3424 case ixgbe_mac_X550:
3425 case ixgbe_mac_X550EM_x:
3426 case ixgbe_mac_x550em_a:
3427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3428 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3429 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3430 break;
3431 default:
3432 break;
3433 }
3434 IXGBE_WRITE_FLUSH(&adapter->hw);
3435 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3436 int vector;
3437
3438 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3439 synchronize_irq(adapter->msix_entries[vector].vector);
3440
3441 synchronize_irq(adapter->msix_entries[vector++].vector);
3442 } else {
3443 synchronize_irq(adapter->pdev->irq);
3444 }
3445 }
3446
3447 /**
3448 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3449 * @adapter: board private structure
3450 *
3451 **/
ixgbe_configure_msi_and_legacy(struct ixgbe_adapter * adapter)3452 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3453 {
3454 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3455
3456 ixgbe_write_eitr(q_vector);
3457
3458 ixgbe_set_ivar(adapter, 0, 0, 0);
3459 ixgbe_set_ivar(adapter, 1, 0, 0);
3460
3461 e_info(hw, "Legacy interrupt IVAR setup done\n");
3462 }
3463
3464 /**
3465 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3466 * @adapter: board private structure
3467 * @ring: structure containing ring specific data
3468 *
3469 * Configure the Tx descriptor ring after a reset.
3470 **/
ixgbe_configure_tx_ring(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)3471 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3472 struct ixgbe_ring *ring)
3473 {
3474 struct ixgbe_hw *hw = &adapter->hw;
3475 u64 tdba = ring->dma;
3476 int wait_loop = 10;
3477 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3478 u8 reg_idx = ring->reg_idx;
3479
3480 ring->xsk_pool = NULL;
3481 if (ring_is_xdp(ring))
3482 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring);
3483
3484 /* disable queue to avoid issues while updating state */
3485 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3486 IXGBE_WRITE_FLUSH(hw);
3487
3488 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3489 (tdba & DMA_BIT_MASK(32)));
3490 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3491 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3492 ring->count * sizeof(union ixgbe_adv_tx_desc));
3493 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3494 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3495 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3496
3497 /*
3498 * set WTHRESH to encourage burst writeback, it should not be set
3499 * higher than 1 when:
3500 * - ITR is 0 as it could cause false TX hangs
3501 * - ITR is set to > 100k int/sec and BQL is enabled
3502 *
3503 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3504 * to or less than the number of on chip descriptors, which is
3505 * currently 40.
3506 */
3507 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3508 txdctl |= 1u << 16; /* WTHRESH = 1 */
3509 else
3510 txdctl |= 8u << 16; /* WTHRESH = 8 */
3511
3512 /*
3513 * Setting PTHRESH to 32 both improves performance
3514 * and avoids a TX hang with DFP enabled
3515 */
3516 txdctl |= (1u << 8) | /* HTHRESH = 1 */
3517 32; /* PTHRESH = 32 */
3518
3519 /* reinitialize flowdirector state */
3520 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3521 ring->atr_sample_rate = adapter->atr_sample_rate;
3522 ring->atr_count = 0;
3523 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3524 } else {
3525 ring->atr_sample_rate = 0;
3526 }
3527
3528 /* initialize XPS */
3529 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3530 struct ixgbe_q_vector *q_vector = ring->q_vector;
3531
3532 if (q_vector)
3533 netif_set_xps_queue(ring->netdev,
3534 &q_vector->affinity_mask,
3535 ring->queue_index);
3536 }
3537
3538 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3539
3540 /* reinitialize tx_buffer_info */
3541 memset(ring->tx_buffer_info, 0,
3542 sizeof(struct ixgbe_tx_buffer) * ring->count);
3543
3544 /* enable queue */
3545 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3546
3547 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3548 if (hw->mac.type == ixgbe_mac_82598EB &&
3549 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3550 return;
3551
3552 /* poll to verify queue is enabled */
3553 do {
3554 usleep_range(1000, 2000);
3555 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3556 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3557 if (!wait_loop)
3558 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
3559 }
3560
ixgbe_setup_mtqc(struct ixgbe_adapter * adapter)3561 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3562 {
3563 struct ixgbe_hw *hw = &adapter->hw;
3564 u32 rttdcs, mtqc;
3565 u8 tcs = adapter->hw_tcs;
3566
3567 if (hw->mac.type == ixgbe_mac_82598EB)
3568 return;
3569
3570 /* disable the arbiter while setting MTQC */
3571 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3572 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3573 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3574
3575 /* set transmit pool layout */
3576 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3577 mtqc = IXGBE_MTQC_VT_ENA;
3578 if (tcs > 4)
3579 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3580 else if (tcs > 1)
3581 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3582 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3583 IXGBE_82599_VMDQ_4Q_MASK)
3584 mtqc |= IXGBE_MTQC_32VF;
3585 else
3586 mtqc |= IXGBE_MTQC_64VF;
3587 } else {
3588 if (tcs > 4) {
3589 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3590 } else if (tcs > 1) {
3591 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3592 } else {
3593 u8 max_txq = adapter->num_tx_queues +
3594 adapter->num_xdp_queues;
3595 if (max_txq > 63)
3596 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3597 else
3598 mtqc = IXGBE_MTQC_64Q_1PB;
3599 }
3600 }
3601
3602 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3603
3604 /* Enable Security TX Buffer IFG for multiple pb */
3605 if (tcs) {
3606 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3607 sectx |= IXGBE_SECTX_DCB;
3608 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3609 }
3610
3611 /* re-enable the arbiter */
3612 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3613 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3614 }
3615
3616 /**
3617 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3618 * @adapter: board private structure
3619 *
3620 * Configure the Tx unit of the MAC after a reset.
3621 **/
ixgbe_configure_tx(struct ixgbe_adapter * adapter)3622 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3623 {
3624 struct ixgbe_hw *hw = &adapter->hw;
3625 u32 dmatxctl;
3626 u32 i;
3627
3628 ixgbe_setup_mtqc(adapter);
3629
3630 if (hw->mac.type != ixgbe_mac_82598EB) {
3631 /* DMATXCTL.EN must be before Tx queues are enabled */
3632 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3633 dmatxctl |= IXGBE_DMATXCTL_TE;
3634 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3635 }
3636
3637 /* Setup the HW Tx Head and Tail descriptor pointers */
3638 for (i = 0; i < adapter->num_tx_queues; i++)
3639 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3640 for (i = 0; i < adapter->num_xdp_queues; i++)
3641 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]);
3642 }
3643
ixgbe_enable_rx_drop(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)3644 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3645 struct ixgbe_ring *ring)
3646 {
3647 struct ixgbe_hw *hw = &adapter->hw;
3648 u8 reg_idx = ring->reg_idx;
3649 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3650
3651 srrctl |= IXGBE_SRRCTL_DROP_EN;
3652
3653 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3654 }
3655
ixgbe_disable_rx_drop(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)3656 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3657 struct ixgbe_ring *ring)
3658 {
3659 struct ixgbe_hw *hw = &adapter->hw;
3660 u8 reg_idx = ring->reg_idx;
3661 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3662
3663 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3664
3665 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3666 }
3667
3668 #ifdef CONFIG_IXGBE_DCB
ixgbe_set_rx_drop_en(struct ixgbe_adapter * adapter)3669 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3670 #else
3671 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3672 #endif
3673 {
3674 int i;
3675 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3676
3677 if (adapter->ixgbe_ieee_pfc)
3678 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3679
3680 /*
3681 * We should set the drop enable bit if:
3682 * SR-IOV is enabled
3683 * or
3684 * Number of Rx queues > 1 and flow control is disabled
3685 *
3686 * This allows us to avoid head of line blocking for security
3687 * and performance reasons.
3688 */
3689 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3690 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3691 for (i = 0; i < adapter->num_rx_queues; i++)
3692 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3693 } else {
3694 for (i = 0; i < adapter->num_rx_queues; i++)
3695 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3696 }
3697 }
3698
3699 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3700
ixgbe_configure_srrctl(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring)3701 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3702 struct ixgbe_ring *rx_ring)
3703 {
3704 struct ixgbe_hw *hw = &adapter->hw;
3705 u32 srrctl;
3706 u8 reg_idx = rx_ring->reg_idx;
3707
3708 if (hw->mac.type == ixgbe_mac_82598EB) {
3709 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3710
3711 /*
3712 * if VMDq is not active we must program one srrctl register
3713 * per RSS queue since we have enabled RDRXCTL.MVMEN
3714 */
3715 reg_idx &= mask;
3716 }
3717
3718 /* configure header buffer length, needed for RSC */
3719 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3720
3721 /* configure the packet buffer length */
3722 if (rx_ring->xsk_pool) {
3723 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool);
3724
3725 /* If the MAC support setting RXDCTL.RLPML, the
3726 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and
3727 * RXDCTL.RLPML is set to the actual UMEM buffer
3728 * size. If not, then we are stuck with a 1k buffer
3729 * size resolution. In this case frames larger than
3730 * the UMEM buffer size viewed in a 1k resolution will
3731 * be dropped.
3732 */
3733 if (hw->mac.type != ixgbe_mac_82599EB)
3734 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3735 else
3736 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3737 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) {
3738 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3739 } else {
3740 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3741 }
3742
3743 /* configure descriptor type */
3744 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3745
3746 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3747 }
3748
3749 /**
3750 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3751 * @adapter: device handle
3752 *
3753 * - 82598/82599/X540: 128
3754 * - X550(non-SRIOV mode): 512
3755 * - X550(SRIOV mode): 64
3756 */
ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter * adapter)3757 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3758 {
3759 if (adapter->hw.mac.type < ixgbe_mac_X550)
3760 return 128;
3761 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3762 return 64;
3763 else
3764 return 512;
3765 }
3766
3767 /**
3768 * ixgbe_store_key - Write the RSS key to HW
3769 * @adapter: device handle
3770 *
3771 * Write the RSS key stored in adapter.rss_key to HW.
3772 */
ixgbe_store_key(struct ixgbe_adapter * adapter)3773 void ixgbe_store_key(struct ixgbe_adapter *adapter)
3774 {
3775 struct ixgbe_hw *hw = &adapter->hw;
3776 int i;
3777
3778 for (i = 0; i < 10; i++)
3779 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3780 }
3781
3782 /**
3783 * ixgbe_init_rss_key - Initialize adapter RSS key
3784 * @adapter: device handle
3785 *
3786 * Allocates and initializes the RSS key if it is not allocated.
3787 **/
ixgbe_init_rss_key(struct ixgbe_adapter * adapter)3788 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter)
3789 {
3790 u32 *rss_key;
3791
3792 if (!adapter->rss_key) {
3793 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL);
3794 if (unlikely(!rss_key))
3795 return -ENOMEM;
3796
3797 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE);
3798 adapter->rss_key = rss_key;
3799 }
3800
3801 return 0;
3802 }
3803
3804 /**
3805 * ixgbe_store_reta - Write the RETA table to HW
3806 * @adapter: device handle
3807 *
3808 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3809 */
ixgbe_store_reta(struct ixgbe_adapter * adapter)3810 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3811 {
3812 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3813 struct ixgbe_hw *hw = &adapter->hw;
3814 u32 reta = 0;
3815 u32 indices_multi;
3816 u8 *indir_tbl = adapter->rss_indir_tbl;
3817
3818 /* Fill out the redirection table as follows:
3819 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3820 * indices.
3821 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3822 * - X550: 8 bit wide entries containing 6 bit RSS index
3823 */
3824 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3825 indices_multi = 0x11;
3826 else
3827 indices_multi = 0x1;
3828
3829 /* Write redirection table to HW */
3830 for (i = 0; i < reta_entries; i++) {
3831 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3832 if ((i & 3) == 3) {
3833 if (i < 128)
3834 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3835 else
3836 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3837 reta);
3838 reta = 0;
3839 }
3840 }
3841 }
3842
3843 /**
3844 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3845 * @adapter: device handle
3846 *
3847 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3848 */
ixgbe_store_vfreta(struct ixgbe_adapter * adapter)3849 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3850 {
3851 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3852 struct ixgbe_hw *hw = &adapter->hw;
3853 u32 vfreta = 0;
3854
3855 /* Write redirection table to HW */
3856 for (i = 0; i < reta_entries; i++) {
3857 u16 pool = adapter->num_rx_pools;
3858
3859 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3860 if ((i & 3) != 3)
3861 continue;
3862
3863 while (pool--)
3864 IXGBE_WRITE_REG(hw,
3865 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)),
3866 vfreta);
3867 vfreta = 0;
3868 }
3869 }
3870
ixgbe_setup_reta(struct ixgbe_adapter * adapter)3871 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3872 {
3873 u32 i, j;
3874 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3875 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3876
3877 /* Program table for at least 4 queues w/ SR-IOV so that VFs can
3878 * make full use of any rings they may have. We will use the
3879 * PSRTYPE register to control how many rings we use within the PF.
3880 */
3881 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3882 rss_i = 4;
3883
3884 /* Fill out hash function seeds */
3885 ixgbe_store_key(adapter);
3886
3887 /* Fill out redirection table */
3888 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3889
3890 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3891 if (j == rss_i)
3892 j = 0;
3893
3894 adapter->rss_indir_tbl[i] = j;
3895 }
3896
3897 ixgbe_store_reta(adapter);
3898 }
3899
ixgbe_setup_vfreta(struct ixgbe_adapter * adapter)3900 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3901 {
3902 struct ixgbe_hw *hw = &adapter->hw;
3903 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3904 int i, j;
3905
3906 /* Fill out hash function seeds */
3907 for (i = 0; i < 10; i++) {
3908 u16 pool = adapter->num_rx_pools;
3909
3910 while (pool--)
3911 IXGBE_WRITE_REG(hw,
3912 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)),
3913 *(adapter->rss_key + i));
3914 }
3915
3916 /* Fill out the redirection table */
3917 for (i = 0, j = 0; i < 64; i++, j++) {
3918 if (j == rss_i)
3919 j = 0;
3920
3921 adapter->rss_indir_tbl[i] = j;
3922 }
3923
3924 ixgbe_store_vfreta(adapter);
3925 }
3926
ixgbe_setup_mrqc(struct ixgbe_adapter * adapter)3927 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3928 {
3929 struct ixgbe_hw *hw = &adapter->hw;
3930 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3931 u32 rxcsum;
3932
3933 /* Disable indicating checksum in descriptor, enables RSS hash */
3934 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3935 rxcsum |= IXGBE_RXCSUM_PCSD;
3936 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3937
3938 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3939 if (adapter->ring_feature[RING_F_RSS].mask)
3940 mrqc = IXGBE_MRQC_RSSEN;
3941 } else {
3942 u8 tcs = adapter->hw_tcs;
3943
3944 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3945 if (tcs > 4)
3946 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3947 else if (tcs > 1)
3948 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3949 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3950 IXGBE_82599_VMDQ_4Q_MASK)
3951 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3952 else
3953 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3954
3955 /* Enable L3/L4 for Tx Switched packets only for X550,
3956 * older devices do not support this feature
3957 */
3958 if (hw->mac.type >= ixgbe_mac_X550)
3959 mrqc |= IXGBE_MRQC_L3L4TXSWEN;
3960 } else {
3961 if (tcs > 4)
3962 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3963 else if (tcs > 1)
3964 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3965 else
3966 mrqc = IXGBE_MRQC_RSSEN;
3967 }
3968 }
3969
3970 /* Perform hash on these packet types */
3971 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3972 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3973 IXGBE_MRQC_RSS_FIELD_IPV6 |
3974 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3975
3976 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3977 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3978 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3979 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3980
3981 if ((hw->mac.type >= ixgbe_mac_X550) &&
3982 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3983 u16 pool = adapter->num_rx_pools;
3984
3985 /* Enable VF RSS mode */
3986 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3987 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3988
3989 /* Setup RSS through the VF registers */
3990 ixgbe_setup_vfreta(adapter);
3991 vfmrqc = IXGBE_MRQC_RSSEN;
3992 vfmrqc |= rss_field;
3993
3994 while (pool--)
3995 IXGBE_WRITE_REG(hw,
3996 IXGBE_PFVFMRQC(VMDQ_P(pool)),
3997 vfmrqc);
3998 } else {
3999 ixgbe_setup_reta(adapter);
4000 mrqc |= rss_field;
4001 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4002 }
4003 }
4004
4005 /**
4006 * ixgbe_configure_rscctl - enable RSC for the indicated ring
4007 * @adapter: address of board private structure
4008 * @ring: structure containing ring specific data
4009 **/
ixgbe_configure_rscctl(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)4010 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
4011 struct ixgbe_ring *ring)
4012 {
4013 struct ixgbe_hw *hw = &adapter->hw;
4014 u32 rscctrl;
4015 u8 reg_idx = ring->reg_idx;
4016
4017 if (!ring_is_rsc_enabled(ring))
4018 return;
4019
4020 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
4021 rscctrl |= IXGBE_RSCCTL_RSCEN;
4022 /*
4023 * we must limit the number of descriptors so that the
4024 * total size of max desc * buf_len is not greater
4025 * than 65536
4026 */
4027 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
4028 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
4029 }
4030
4031 #define IXGBE_MAX_RX_DESC_POLL 10
ixgbe_rx_desc_queue_enable(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)4032 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
4033 struct ixgbe_ring *ring)
4034 {
4035 struct ixgbe_hw *hw = &adapter->hw;
4036 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
4037 u32 rxdctl;
4038 u8 reg_idx = ring->reg_idx;
4039
4040 if (ixgbe_removed(hw->hw_addr))
4041 return;
4042 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
4043 if (hw->mac.type == ixgbe_mac_82598EB &&
4044 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
4045 return;
4046
4047 do {
4048 usleep_range(1000, 2000);
4049 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4050 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4051
4052 if (!wait_loop) {
4053 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
4054 "the polling period\n", reg_idx);
4055 }
4056 }
4057
ixgbe_configure_rx_ring(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)4058 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
4059 struct ixgbe_ring *ring)
4060 {
4061 struct ixgbe_hw *hw = &adapter->hw;
4062 union ixgbe_adv_rx_desc *rx_desc;
4063 u64 rdba = ring->dma;
4064 u32 rxdctl;
4065 u8 reg_idx = ring->reg_idx;
4066
4067 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4068 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring);
4069 if (ring->xsk_pool) {
4070 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4071 MEM_TYPE_XSK_BUFF_POOL,
4072 NULL));
4073 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
4074 } else {
4075 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4076 MEM_TYPE_PAGE_SHARED, NULL));
4077 }
4078
4079 /* disable queue to avoid use of these values while updating state */
4080 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4081 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4082
4083 /* write value back with RXDCTL.ENABLE bit cleared */
4084 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4085 IXGBE_WRITE_FLUSH(hw);
4086
4087 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
4088 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
4089 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
4090 ring->count * sizeof(union ixgbe_adv_rx_desc));
4091 /* Force flushing of IXGBE_RDLEN to prevent MDD */
4092 IXGBE_WRITE_FLUSH(hw);
4093
4094 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
4095 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
4096 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
4097
4098 ixgbe_configure_srrctl(adapter, ring);
4099 ixgbe_configure_rscctl(adapter, ring);
4100
4101 if (hw->mac.type == ixgbe_mac_82598EB) {
4102 /*
4103 * enable cache line friendly hardware writes:
4104 * PTHRESH=32 descriptors (half the internal cache),
4105 * this also removes ugly rx_no_buffer_count increment
4106 * HTHRESH=4 descriptors (to minimize latency on fetch)
4107 * WTHRESH=8 burst writeback up to two cache lines
4108 */
4109 rxdctl &= ~0x3FFFFF;
4110 rxdctl |= 0x080420;
4111 #if (PAGE_SIZE < 8192)
4112 /* RXDCTL.RLPML does not work on 82599 */
4113 } else if (hw->mac.type != ixgbe_mac_82599EB) {
4114 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4115 IXGBE_RXDCTL_RLPML_EN);
4116
4117 /* Limit the maximum frame size so we don't overrun the skb.
4118 * This can happen in SRIOV mode when the MTU of the VF is
4119 * higher than the MTU of the PF.
4120 */
4121 if (ring_uses_build_skb(ring) &&
4122 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
4123 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB |
4124 IXGBE_RXDCTL_RLPML_EN;
4125 #endif
4126 }
4127
4128 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) {
4129 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool);
4130
4131 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4132 IXGBE_RXDCTL_RLPML_EN);
4133 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN;
4134
4135 ring->rx_buf_len = xsk_buf_len;
4136 }
4137
4138 /* initialize rx_buffer_info */
4139 memset(ring->rx_buffer_info, 0,
4140 sizeof(struct ixgbe_rx_buffer) * ring->count);
4141
4142 /* initialize Rx descriptor 0 */
4143 rx_desc = IXGBE_RX_DESC(ring, 0);
4144 rx_desc->wb.upper.length = 0;
4145
4146 /* enable receive descriptor ring */
4147 rxdctl |= IXGBE_RXDCTL_ENABLE;
4148 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4149
4150 ixgbe_rx_desc_queue_enable(adapter, ring);
4151 if (ring->xsk_pool)
4152 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring));
4153 else
4154 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
4155 }
4156
ixgbe_setup_psrtype(struct ixgbe_adapter * adapter)4157 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
4158 {
4159 struct ixgbe_hw *hw = &adapter->hw;
4160 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
4161 u16 pool = adapter->num_rx_pools;
4162
4163 /* PSRTYPE must be initialized in non 82598 adapters */
4164 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4165 IXGBE_PSRTYPE_UDPHDR |
4166 IXGBE_PSRTYPE_IPV4HDR |
4167 IXGBE_PSRTYPE_L2HDR |
4168 IXGBE_PSRTYPE_IPV6HDR;
4169
4170 if (hw->mac.type == ixgbe_mac_82598EB)
4171 return;
4172
4173 if (rss_i > 3)
4174 psrtype |= 2u << 29;
4175 else if (rss_i > 1)
4176 psrtype |= 1u << 29;
4177
4178 while (pool--)
4179 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4180 }
4181
ixgbe_configure_virtualization(struct ixgbe_adapter * adapter)4182 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
4183 {
4184 struct ixgbe_hw *hw = &adapter->hw;
4185 u16 pool = adapter->num_rx_pools;
4186 u32 reg_offset, vf_shift, vmolr;
4187 u32 gcr_ext, vmdctl;
4188 int i;
4189
4190 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
4191 return;
4192
4193 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4194 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
4195 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
4196 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
4197 vmdctl |= IXGBE_VT_CTL_REPLEN;
4198 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
4199
4200 /* accept untagged packets until a vlan tag is
4201 * specifically set for the VMDQ queue/pool
4202 */
4203 vmolr = IXGBE_VMOLR_AUPE;
4204 while (pool--)
4205 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr);
4206
4207 vf_shift = VMDQ_P(0) % 32;
4208 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
4209
4210 /* Enable only the PF's pool for Tx/Rx */
4211 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
4212 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
4213 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
4214 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
4215 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
4216 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4217
4218 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
4219 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
4220
4221 /* clear VLAN promisc flag so VFTA will be updated if necessary */
4222 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4223
4224 /*
4225 * Set up VF register offsets for selected VT Mode,
4226 * i.e. 32 or 64 VFs for SR-IOV
4227 */
4228 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4229 case IXGBE_82599_VMDQ_8Q_MASK:
4230 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
4231 break;
4232 case IXGBE_82599_VMDQ_4Q_MASK:
4233 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
4234 break;
4235 default:
4236 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
4237 break;
4238 }
4239
4240 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4241
4242 for (i = 0; i < adapter->num_vfs; i++) {
4243 /* configure spoof checking */
4244 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
4245 adapter->vfinfo[i].spoofchk_enabled);
4246
4247 /* Enable/Disable RSS query feature */
4248 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
4249 adapter->vfinfo[i].rss_query_enabled);
4250 }
4251 }
4252
ixgbe_set_rx_buffer_len(struct ixgbe_adapter * adapter)4253 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
4254 {
4255 struct ixgbe_hw *hw = &adapter->hw;
4256 struct net_device *netdev = adapter->netdev;
4257 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4258 struct ixgbe_ring *rx_ring;
4259 int i;
4260 u32 mhadd, hlreg0;
4261
4262 #ifdef IXGBE_FCOE
4263 /* adjust max frame to be able to do baby jumbo for FCoE */
4264 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4265 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
4266 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4267
4268 #endif /* IXGBE_FCOE */
4269
4270 /* adjust max frame to be at least the size of a standard frame */
4271 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4272 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
4273
4274 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4275 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
4276 mhadd &= ~IXGBE_MHADD_MFS_MASK;
4277 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
4278
4279 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4280 }
4281
4282 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4283 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
4284 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4285 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4286
4287 /*
4288 * Setup the HW Rx Head and Tail Descriptor Pointers and
4289 * the Base and Length of the Rx Descriptor Ring
4290 */
4291 for (i = 0; i < adapter->num_rx_queues; i++) {
4292 rx_ring = adapter->rx_ring[i];
4293
4294 clear_ring_rsc_enabled(rx_ring);
4295 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4296 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4297
4298 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4299 set_ring_rsc_enabled(rx_ring);
4300
4301 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state))
4302 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4303
4304 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
4305 continue;
4306
4307 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4308
4309 #if (PAGE_SIZE < 8192)
4310 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4311 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4312
4313 if (IXGBE_2K_TOO_SMALL_WITH_PADDING ||
4314 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4315 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4316 #endif
4317 }
4318 }
4319
ixgbe_setup_rdrxctl(struct ixgbe_adapter * adapter)4320 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
4321 {
4322 struct ixgbe_hw *hw = &adapter->hw;
4323 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4324
4325 switch (hw->mac.type) {
4326 case ixgbe_mac_82598EB:
4327 /*
4328 * For VMDq support of different descriptor types or
4329 * buffer sizes through the use of multiple SRRCTL
4330 * registers, RDRXCTL.MVMEN must be set to 1
4331 *
4332 * also, the manual doesn't mention it clearly but DCA hints
4333 * will only use queue 0's tags unless this bit is set. Side
4334 * effects of setting this bit are only that SRRCTL must be
4335 * fully programmed [0..15]
4336 */
4337 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
4338 break;
4339 case ixgbe_mac_X550:
4340 case ixgbe_mac_X550EM_x:
4341 case ixgbe_mac_x550em_a:
4342 if (adapter->num_vfs)
4343 rdrxctl |= IXGBE_RDRXCTL_PSP;
4344 fallthrough;
4345 case ixgbe_mac_82599EB:
4346 case ixgbe_mac_X540:
4347 /* Disable RSC for ACK packets */
4348 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
4349 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
4350 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4351 /* hardware requires some bits to be set by default */
4352 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
4353 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4354 break;
4355 default:
4356 /* We should do nothing since we don't know this hardware */
4357 return;
4358 }
4359
4360 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4361 }
4362
4363 /**
4364 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
4365 * @adapter: board private structure
4366 *
4367 * Configure the Rx unit of the MAC after a reset.
4368 **/
ixgbe_configure_rx(struct ixgbe_adapter * adapter)4369 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
4370 {
4371 struct ixgbe_hw *hw = &adapter->hw;
4372 int i;
4373 u32 rxctrl, rfctl;
4374
4375 /* disable receives while setting up the descriptors */
4376 hw->mac.ops.disable_rx(hw);
4377
4378 ixgbe_setup_psrtype(adapter);
4379 ixgbe_setup_rdrxctl(adapter);
4380
4381 /* RSC Setup */
4382 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4383 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4384 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
4385 rfctl |= IXGBE_RFCTL_RSC_DIS;
4386
4387 /* disable NFS filtering */
4388 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
4389 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4390
4391 /* Program registers for the distribution of queues */
4392 ixgbe_setup_mrqc(adapter);
4393
4394 /* set_rx_buffer_len must be called before ring initialization */
4395 ixgbe_set_rx_buffer_len(adapter);
4396
4397 /*
4398 * Setup the HW Rx Head and Tail Descriptor Pointers and
4399 * the Base and Length of the Rx Descriptor Ring
4400 */
4401 for (i = 0; i < adapter->num_rx_queues; i++)
4402 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
4403
4404 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4405 /* disable drop enable for 82598 parts */
4406 if (hw->mac.type == ixgbe_mac_82598EB)
4407 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4408
4409 /* enable all receives */
4410 rxctrl |= IXGBE_RXCTRL_RXEN;
4411 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4412 }
4413
ixgbe_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)4414 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
4415 __be16 proto, u16 vid)
4416 {
4417 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4418 struct ixgbe_hw *hw = &adapter->hw;
4419
4420 /* add VID to filter table */
4421 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4422 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
4423
4424 set_bit(vid, adapter->active_vlans);
4425
4426 return 0;
4427 }
4428
ixgbe_find_vlvf_entry(struct ixgbe_hw * hw,u32 vlan)4429 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
4430 {
4431 u32 vlvf;
4432 int idx;
4433
4434 /* short cut the special case */
4435 if (vlan == 0)
4436 return 0;
4437
4438 /* Search for the vlan id in the VLVF entries */
4439 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
4440 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
4441 if ((vlvf & VLAN_VID_MASK) == vlan)
4442 break;
4443 }
4444
4445 return idx;
4446 }
4447
ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter * adapter,u32 vid)4448 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
4449 {
4450 struct ixgbe_hw *hw = &adapter->hw;
4451 u32 bits, word;
4452 int idx;
4453
4454 idx = ixgbe_find_vlvf_entry(hw, vid);
4455 if (!idx)
4456 return;
4457
4458 /* See if any other pools are set for this VLAN filter
4459 * entry other than the PF.
4460 */
4461 word = idx * 2 + (VMDQ_P(0) / 32);
4462 bits = ~BIT(VMDQ_P(0) % 32);
4463 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4464
4465 /* Disable the filter so this falls into the default pool. */
4466 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4467 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4468 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4469 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4470 }
4471 }
4472
ixgbe_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)4473 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4474 __be16 proto, u16 vid)
4475 {
4476 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4477 struct ixgbe_hw *hw = &adapter->hw;
4478
4479 /* remove VID from filter table */
4480 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4481 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4482
4483 clear_bit(vid, adapter->active_vlans);
4484
4485 return 0;
4486 }
4487
4488 /**
4489 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4490 * @adapter: driver data
4491 */
ixgbe_vlan_strip_disable(struct ixgbe_adapter * adapter)4492 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4493 {
4494 struct ixgbe_hw *hw = &adapter->hw;
4495 u32 vlnctrl;
4496 int i, j;
4497
4498 switch (hw->mac.type) {
4499 case ixgbe_mac_82598EB:
4500 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4501 vlnctrl &= ~IXGBE_VLNCTRL_VME;
4502 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4503 break;
4504 case ixgbe_mac_82599EB:
4505 case ixgbe_mac_X540:
4506 case ixgbe_mac_X550:
4507 case ixgbe_mac_X550EM_x:
4508 case ixgbe_mac_x550em_a:
4509 for (i = 0; i < adapter->num_rx_queues; i++) {
4510 struct ixgbe_ring *ring = adapter->rx_ring[i];
4511
4512 if (!netif_is_ixgbe(ring->netdev))
4513 continue;
4514
4515 j = ring->reg_idx;
4516 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4517 vlnctrl &= ~IXGBE_RXDCTL_VME;
4518 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4519 }
4520 break;
4521 default:
4522 break;
4523 }
4524 }
4525
4526 /**
4527 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
4528 * @adapter: driver data
4529 */
ixgbe_vlan_strip_enable(struct ixgbe_adapter * adapter)4530 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
4531 {
4532 struct ixgbe_hw *hw = &adapter->hw;
4533 u32 vlnctrl;
4534 int i, j;
4535
4536 switch (hw->mac.type) {
4537 case ixgbe_mac_82598EB:
4538 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4539 vlnctrl |= IXGBE_VLNCTRL_VME;
4540 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4541 break;
4542 case ixgbe_mac_82599EB:
4543 case ixgbe_mac_X540:
4544 case ixgbe_mac_X550:
4545 case ixgbe_mac_X550EM_x:
4546 case ixgbe_mac_x550em_a:
4547 for (i = 0; i < adapter->num_rx_queues; i++) {
4548 struct ixgbe_ring *ring = adapter->rx_ring[i];
4549
4550 if (!netif_is_ixgbe(ring->netdev))
4551 continue;
4552
4553 j = ring->reg_idx;
4554 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4555 vlnctrl |= IXGBE_RXDCTL_VME;
4556 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4557 }
4558 break;
4559 default:
4560 break;
4561 }
4562 }
4563
ixgbe_vlan_promisc_enable(struct ixgbe_adapter * adapter)4564 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4565 {
4566 struct ixgbe_hw *hw = &adapter->hw;
4567 u32 vlnctrl, i;
4568
4569 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4570
4571 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4572 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4573 vlnctrl |= IXGBE_VLNCTRL_VFE;
4574 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4575 } else {
4576 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
4577 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4578 return;
4579 }
4580
4581 /* Nothing to do for 82598 */
4582 if (hw->mac.type == ixgbe_mac_82598EB)
4583 return;
4584
4585 /* We are already in VLAN promisc, nothing to do */
4586 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4587 return;
4588
4589 /* Set flag so we don't redo unnecessary work */
4590 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4591
4592 /* Add PF to all active pools */
4593 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4594 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4595 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4596
4597 vlvfb |= BIT(VMDQ_P(0) % 32);
4598 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4599 }
4600
4601 /* Set all bits in the VLAN filter table array */
4602 for (i = hw->mac.vft_size; i--;)
4603 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4604 }
4605
4606 #define VFTA_BLOCK_SIZE 8
ixgbe_scrub_vfta(struct ixgbe_adapter * adapter,u32 vfta_offset)4607 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4608 {
4609 struct ixgbe_hw *hw = &adapter->hw;
4610 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4611 u32 vid_start = vfta_offset * 32;
4612 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4613 u32 i, vid, word, bits;
4614
4615 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4616 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4617
4618 /* pull VLAN ID from VLVF */
4619 vid = vlvf & VLAN_VID_MASK;
4620
4621 /* only concern outselves with a certain range */
4622 if (vid < vid_start || vid >= vid_end)
4623 continue;
4624
4625 if (vlvf) {
4626 /* record VLAN ID in VFTA */
4627 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4628
4629 /* if PF is part of this then continue */
4630 if (test_bit(vid, adapter->active_vlans))
4631 continue;
4632 }
4633
4634 /* remove PF from the pool */
4635 word = i * 2 + VMDQ_P(0) / 32;
4636 bits = ~BIT(VMDQ_P(0) % 32);
4637 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4638 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4639 }
4640
4641 /* extract values from active_vlans and write back to VFTA */
4642 for (i = VFTA_BLOCK_SIZE; i--;) {
4643 vid = (vfta_offset + i) * 32;
4644 word = vid / BITS_PER_LONG;
4645 bits = vid % BITS_PER_LONG;
4646
4647 vfta[i] |= adapter->active_vlans[word] >> bits;
4648
4649 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4650 }
4651 }
4652
ixgbe_vlan_promisc_disable(struct ixgbe_adapter * adapter)4653 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4654 {
4655 struct ixgbe_hw *hw = &adapter->hw;
4656 u32 vlnctrl, i;
4657
4658 /* Set VLAN filtering to enabled */
4659 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4660 vlnctrl |= IXGBE_VLNCTRL_VFE;
4661 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4662
4663 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4664 hw->mac.type == ixgbe_mac_82598EB)
4665 return;
4666
4667 /* We are not in VLAN promisc, nothing to do */
4668 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4669 return;
4670
4671 /* Set flag so we don't redo unnecessary work */
4672 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4673
4674 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4675 ixgbe_scrub_vfta(adapter, i);
4676 }
4677
ixgbe_restore_vlan(struct ixgbe_adapter * adapter)4678 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4679 {
4680 u16 vid = 1;
4681
4682 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4683
4684 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
4685 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4686 }
4687
4688 /**
4689 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4690 * @netdev: network interface device structure
4691 *
4692 * Writes multicast address list to the MTA hash table.
4693 * Returns: -ENOMEM on failure
4694 * 0 on no addresses written
4695 * X on writing X addresses to MTA
4696 **/
ixgbe_write_mc_addr_list(struct net_device * netdev)4697 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4698 {
4699 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4700 struct ixgbe_hw *hw = &adapter->hw;
4701
4702 if (!netif_running(netdev))
4703 return 0;
4704
4705 if (hw->mac.ops.update_mc_addr_list)
4706 hw->mac.ops.update_mc_addr_list(hw, netdev);
4707 else
4708 return -ENOMEM;
4709
4710 #ifdef CONFIG_PCI_IOV
4711 ixgbe_restore_vf_multicasts(adapter);
4712 #endif
4713
4714 return netdev_mc_count(netdev);
4715 }
4716
4717 #ifdef CONFIG_PCI_IOV
ixgbe_full_sync_mac_table(struct ixgbe_adapter * adapter)4718 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4719 {
4720 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4721 struct ixgbe_hw *hw = &adapter->hw;
4722 int i;
4723
4724 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4725 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4726
4727 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4728 hw->mac.ops.set_rar(hw, i,
4729 mac_table->addr,
4730 mac_table->pool,
4731 IXGBE_RAH_AV);
4732 else
4733 hw->mac.ops.clear_rar(hw, i);
4734 }
4735 }
4736
4737 #endif
ixgbe_sync_mac_table(struct ixgbe_adapter * adapter)4738 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4739 {
4740 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4741 struct ixgbe_hw *hw = &adapter->hw;
4742 int i;
4743
4744 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4745 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4746 continue;
4747
4748 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4749
4750 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4751 hw->mac.ops.set_rar(hw, i,
4752 mac_table->addr,
4753 mac_table->pool,
4754 IXGBE_RAH_AV);
4755 else
4756 hw->mac.ops.clear_rar(hw, i);
4757 }
4758 }
4759
ixgbe_flush_sw_mac_table(struct ixgbe_adapter * adapter)4760 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4761 {
4762 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4763 struct ixgbe_hw *hw = &adapter->hw;
4764 int i;
4765
4766 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4767 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4768 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4769 }
4770
4771 ixgbe_sync_mac_table(adapter);
4772 }
4773
ixgbe_available_rars(struct ixgbe_adapter * adapter,u16 pool)4774 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4775 {
4776 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4777 struct ixgbe_hw *hw = &adapter->hw;
4778 int i, count = 0;
4779
4780 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4781 /* do not count default RAR as available */
4782 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4783 continue;
4784
4785 /* only count unused and addresses that belong to us */
4786 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4787 if (mac_table->pool != pool)
4788 continue;
4789 }
4790
4791 count++;
4792 }
4793
4794 return count;
4795 }
4796
4797 /* this function destroys the first RAR entry */
ixgbe_mac_set_default_filter(struct ixgbe_adapter * adapter)4798 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4799 {
4800 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4801 struct ixgbe_hw *hw = &adapter->hw;
4802
4803 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4804 mac_table->pool = VMDQ_P(0);
4805
4806 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4807
4808 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4809 IXGBE_RAH_AV);
4810 }
4811
ixgbe_add_mac_filter(struct ixgbe_adapter * adapter,const u8 * addr,u16 pool)4812 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4813 const u8 *addr, u16 pool)
4814 {
4815 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4816 struct ixgbe_hw *hw = &adapter->hw;
4817 int i;
4818
4819 if (is_zero_ether_addr(addr))
4820 return -EINVAL;
4821
4822 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4823 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4824 continue;
4825
4826 ether_addr_copy(mac_table->addr, addr);
4827 mac_table->pool = pool;
4828
4829 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4830 IXGBE_MAC_STATE_IN_USE;
4831
4832 ixgbe_sync_mac_table(adapter);
4833
4834 return i;
4835 }
4836
4837 return -ENOMEM;
4838 }
4839
ixgbe_del_mac_filter(struct ixgbe_adapter * adapter,const u8 * addr,u16 pool)4840 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4841 const u8 *addr, u16 pool)
4842 {
4843 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4844 struct ixgbe_hw *hw = &adapter->hw;
4845 int i;
4846
4847 if (is_zero_ether_addr(addr))
4848 return -EINVAL;
4849
4850 /* search table for addr, if found clear IN_USE flag and sync */
4851 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4852 /* we can only delete an entry if it is in use */
4853 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4854 continue;
4855 /* we only care about entries that belong to the given pool */
4856 if (mac_table->pool != pool)
4857 continue;
4858 /* we only care about a specific MAC address */
4859 if (!ether_addr_equal(addr, mac_table->addr))
4860 continue;
4861
4862 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4863 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4864
4865 ixgbe_sync_mac_table(adapter);
4866
4867 return 0;
4868 }
4869
4870 return -ENOMEM;
4871 }
4872
ixgbe_uc_sync(struct net_device * netdev,const unsigned char * addr)4873 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4874 {
4875 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4876 int ret;
4877
4878 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4879
4880 return min_t(int, ret, 0);
4881 }
4882
ixgbe_uc_unsync(struct net_device * netdev,const unsigned char * addr)4883 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4884 {
4885 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4886
4887 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4888
4889 return 0;
4890 }
4891
4892 /**
4893 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4894 * @netdev: network interface device structure
4895 *
4896 * The set_rx_method entry point is called whenever the unicast/multicast
4897 * address list or the network interface flags are updated. This routine is
4898 * responsible for configuring the hardware for proper unicast, multicast and
4899 * promiscuous mode.
4900 **/
ixgbe_set_rx_mode(struct net_device * netdev)4901 void ixgbe_set_rx_mode(struct net_device *netdev)
4902 {
4903 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4904 struct ixgbe_hw *hw = &adapter->hw;
4905 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4906 netdev_features_t features = netdev->features;
4907 int count;
4908
4909 /* Check for Promiscuous and All Multicast modes */
4910 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4911
4912 /* set all bits that we expect to always be set */
4913 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4914 fctrl |= IXGBE_FCTRL_BAM;
4915 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4916 fctrl |= IXGBE_FCTRL_PMCF;
4917
4918 /* clear the bits we are changing the status of */
4919 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4920 if (netdev->flags & IFF_PROMISC) {
4921 hw->addr_ctrl.user_set_promisc = true;
4922 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4923 vmolr |= IXGBE_VMOLR_MPE;
4924 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4925 } else {
4926 if (netdev->flags & IFF_ALLMULTI) {
4927 fctrl |= IXGBE_FCTRL_MPE;
4928 vmolr |= IXGBE_VMOLR_MPE;
4929 }
4930 hw->addr_ctrl.user_set_promisc = false;
4931 }
4932
4933 /*
4934 * Write addresses to available RAR registers, if there is not
4935 * sufficient space to store all the addresses then enable
4936 * unicast promiscuous mode
4937 */
4938 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4939 fctrl |= IXGBE_FCTRL_UPE;
4940 vmolr |= IXGBE_VMOLR_ROPE;
4941 }
4942
4943 /* Write addresses to the MTA, if the attempt fails
4944 * then we should just turn on promiscuous mode so
4945 * that we can at least receive multicast traffic
4946 */
4947 count = ixgbe_write_mc_addr_list(netdev);
4948 if (count < 0) {
4949 fctrl |= IXGBE_FCTRL_MPE;
4950 vmolr |= IXGBE_VMOLR_MPE;
4951 } else if (count) {
4952 vmolr |= IXGBE_VMOLR_ROMPE;
4953 }
4954
4955 if (hw->mac.type != ixgbe_mac_82598EB) {
4956 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4957 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4958 IXGBE_VMOLR_ROPE);
4959 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4960 }
4961
4962 /* This is useful for sniffing bad packets. */
4963 if (features & NETIF_F_RXALL) {
4964 /* UPE and MPE will be handled by normal PROMISC logic
4965 * in e1000e_set_rx_mode */
4966 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4967 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4968 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4969
4970 fctrl &= ~(IXGBE_FCTRL_DPF);
4971 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4972 }
4973
4974 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4975
4976 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4977 ixgbe_vlan_strip_enable(adapter);
4978 else
4979 ixgbe_vlan_strip_disable(adapter);
4980
4981 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4982 ixgbe_vlan_promisc_disable(adapter);
4983 else
4984 ixgbe_vlan_promisc_enable(adapter);
4985 }
4986
ixgbe_napi_enable_all(struct ixgbe_adapter * adapter)4987 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4988 {
4989 int q_idx;
4990
4991 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4992 napi_enable(&adapter->q_vector[q_idx]->napi);
4993 }
4994
ixgbe_napi_disable_all(struct ixgbe_adapter * adapter)4995 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4996 {
4997 int q_idx;
4998
4999 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
5000 napi_disable(&adapter->q_vector[q_idx]->napi);
5001 }
5002
ixgbe_udp_tunnel_sync(struct net_device * dev,unsigned int table)5003 static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table)
5004 {
5005 struct ixgbe_adapter *adapter = netdev_priv(dev);
5006 struct ixgbe_hw *hw = &adapter->hw;
5007 struct udp_tunnel_info ti;
5008
5009 udp_tunnel_nic_get_port(dev, table, 0, &ti);
5010 if (ti.type == UDP_TUNNEL_TYPE_VXLAN)
5011 adapter->vxlan_port = ti.port;
5012 else
5013 adapter->geneve_port = ti.port;
5014
5015 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL,
5016 ntohs(adapter->vxlan_port) |
5017 ntohs(adapter->geneve_port) <<
5018 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT);
5019 return 0;
5020 }
5021
5022 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = {
5023 .sync_table = ixgbe_udp_tunnel_sync,
5024 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5025 .tables = {
5026 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
5027 },
5028 };
5029
5030 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = {
5031 .sync_table = ixgbe_udp_tunnel_sync,
5032 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5033 .tables = {
5034 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
5035 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
5036 },
5037 };
5038
5039 #ifdef CONFIG_IXGBE_DCB
5040 /**
5041 * ixgbe_configure_dcb - Configure DCB hardware
5042 * @adapter: ixgbe adapter struct
5043 *
5044 * This is called by the driver on open to configure the DCB hardware.
5045 * This is also called by the gennetlink interface when reconfiguring
5046 * the DCB state.
5047 */
ixgbe_configure_dcb(struct ixgbe_adapter * adapter)5048 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
5049 {
5050 struct ixgbe_hw *hw = &adapter->hw;
5051 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
5052
5053 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
5054 if (hw->mac.type == ixgbe_mac_82598EB)
5055 netif_set_gso_max_size(adapter->netdev, 65536);
5056 return;
5057 }
5058
5059 if (hw->mac.type == ixgbe_mac_82598EB)
5060 netif_set_gso_max_size(adapter->netdev, 32768);
5061
5062 #ifdef IXGBE_FCOE
5063 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
5064 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
5065 #endif
5066
5067 /* reconfigure the hardware */
5068 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
5069 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5070 DCB_TX_CONFIG);
5071 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5072 DCB_RX_CONFIG);
5073 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
5074 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
5075 ixgbe_dcb_hw_ets(&adapter->hw,
5076 adapter->ixgbe_ieee_ets,
5077 max_frame);
5078 ixgbe_dcb_hw_pfc_config(&adapter->hw,
5079 adapter->ixgbe_ieee_pfc->pfc_en,
5080 adapter->ixgbe_ieee_ets->prio_tc);
5081 }
5082
5083 /* Enable RSS Hash per TC */
5084 if (hw->mac.type != ixgbe_mac_82598EB) {
5085 u32 msb = 0;
5086 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
5087
5088 while (rss_i) {
5089 msb++;
5090 rss_i >>= 1;
5091 }
5092
5093 /* write msb to all 8 TCs in one write */
5094 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
5095 }
5096 }
5097 #endif
5098
5099 /* Additional bittime to account for IXGBE framing */
5100 #define IXGBE_ETH_FRAMING 20
5101
5102 /**
5103 * ixgbe_hpbthresh - calculate high water mark for flow control
5104 *
5105 * @adapter: board private structure to calculate for
5106 * @pb: packet buffer to calculate
5107 */
ixgbe_hpbthresh(struct ixgbe_adapter * adapter,int pb)5108 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
5109 {
5110 struct ixgbe_hw *hw = &adapter->hw;
5111 struct net_device *dev = adapter->netdev;
5112 int link, tc, kb, marker;
5113 u32 dv_id, rx_pba;
5114
5115 /* Calculate max LAN frame size */
5116 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
5117
5118 #ifdef IXGBE_FCOE
5119 /* FCoE traffic class uses FCOE jumbo frames */
5120 if ((dev->features & NETIF_F_FCOE_MTU) &&
5121 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5122 (pb == ixgbe_fcoe_get_tc(adapter)))
5123 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5124 #endif
5125
5126 /* Calculate delay value for device */
5127 switch (hw->mac.type) {
5128 case ixgbe_mac_X540:
5129 case ixgbe_mac_X550:
5130 case ixgbe_mac_X550EM_x:
5131 case ixgbe_mac_x550em_a:
5132 dv_id = IXGBE_DV_X540(link, tc);
5133 break;
5134 default:
5135 dv_id = IXGBE_DV(link, tc);
5136 break;
5137 }
5138
5139 /* Loopback switch introduces additional latency */
5140 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5141 dv_id += IXGBE_B2BT(tc);
5142
5143 /* Delay value is calculated in bit times convert to KB */
5144 kb = IXGBE_BT2KB(dv_id);
5145 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
5146
5147 marker = rx_pba - kb;
5148
5149 /* It is possible that the packet buffer is not large enough
5150 * to provide required headroom. In this case throw an error
5151 * to user and a do the best we can.
5152 */
5153 if (marker < 0) {
5154 e_warn(drv, "Packet Buffer(%i) can not provide enough"
5155 "headroom to support flow control."
5156 "Decrease MTU or number of traffic classes\n", pb);
5157 marker = tc + 1;
5158 }
5159
5160 return marker;
5161 }
5162
5163 /**
5164 * ixgbe_lpbthresh - calculate low water mark for for flow control
5165 *
5166 * @adapter: board private structure to calculate for
5167 * @pb: packet buffer to calculate
5168 */
ixgbe_lpbthresh(struct ixgbe_adapter * adapter,int pb)5169 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
5170 {
5171 struct ixgbe_hw *hw = &adapter->hw;
5172 struct net_device *dev = adapter->netdev;
5173 int tc;
5174 u32 dv_id;
5175
5176 /* Calculate max LAN frame size */
5177 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5178
5179 #ifdef IXGBE_FCOE
5180 /* FCoE traffic class uses FCOE jumbo frames */
5181 if ((dev->features & NETIF_F_FCOE_MTU) &&
5182 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5183 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
5184 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5185 #endif
5186
5187 /* Calculate delay value for device */
5188 switch (hw->mac.type) {
5189 case ixgbe_mac_X540:
5190 case ixgbe_mac_X550:
5191 case ixgbe_mac_X550EM_x:
5192 case ixgbe_mac_x550em_a:
5193 dv_id = IXGBE_LOW_DV_X540(tc);
5194 break;
5195 default:
5196 dv_id = IXGBE_LOW_DV(tc);
5197 break;
5198 }
5199
5200 /* Delay value is calculated in bit times convert to KB */
5201 return IXGBE_BT2KB(dv_id);
5202 }
5203
5204 /*
5205 * ixgbe_pbthresh_setup - calculate and setup high low water marks
5206 */
ixgbe_pbthresh_setup(struct ixgbe_adapter * adapter)5207 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
5208 {
5209 struct ixgbe_hw *hw = &adapter->hw;
5210 int num_tc = adapter->hw_tcs;
5211 int i;
5212
5213 if (!num_tc)
5214 num_tc = 1;
5215
5216 for (i = 0; i < num_tc; i++) {
5217 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
5218 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
5219
5220 /* Low water marks must not be larger than high water marks */
5221 if (hw->fc.low_water[i] > hw->fc.high_water[i])
5222 hw->fc.low_water[i] = 0;
5223 }
5224
5225 for (; i < MAX_TRAFFIC_CLASS; i++)
5226 hw->fc.high_water[i] = 0;
5227 }
5228
ixgbe_configure_pb(struct ixgbe_adapter * adapter)5229 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
5230 {
5231 struct ixgbe_hw *hw = &adapter->hw;
5232 int hdrm;
5233 u8 tc = adapter->hw_tcs;
5234
5235 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5236 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5237 hdrm = 32 << adapter->fdir_pballoc;
5238 else
5239 hdrm = 0;
5240
5241 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
5242 ixgbe_pbthresh_setup(adapter);
5243 }
5244
ixgbe_fdir_filter_restore(struct ixgbe_adapter * adapter)5245 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
5246 {
5247 struct ixgbe_hw *hw = &adapter->hw;
5248 struct hlist_node *node2;
5249 struct ixgbe_fdir_filter *filter;
5250 u8 queue;
5251
5252 spin_lock(&adapter->fdir_perfect_lock);
5253
5254 if (!hlist_empty(&adapter->fdir_filter_list))
5255 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
5256
5257 hlist_for_each_entry_safe(filter, node2,
5258 &adapter->fdir_filter_list, fdir_node) {
5259 if (filter->action == IXGBE_FDIR_DROP_QUEUE) {
5260 queue = IXGBE_FDIR_DROP_QUEUE;
5261 } else {
5262 u32 ring = ethtool_get_flow_spec_ring(filter->action);
5263 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action);
5264
5265 if (!vf && (ring >= adapter->num_rx_queues)) {
5266 e_err(drv, "FDIR restore failed without VF, ring: %u\n",
5267 ring);
5268 continue;
5269 } else if (vf &&
5270 ((vf > adapter->num_vfs) ||
5271 ring >= adapter->num_rx_queues_per_pool)) {
5272 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n",
5273 vf, ring);
5274 continue;
5275 }
5276
5277 /* Map the ring onto the absolute queue index */
5278 if (!vf)
5279 queue = adapter->rx_ring[ring]->reg_idx;
5280 else
5281 queue = ((vf - 1) *
5282 adapter->num_rx_queues_per_pool) + ring;
5283 }
5284
5285 ixgbe_fdir_write_perfect_filter_82599(hw,
5286 &filter->filter, filter->sw_idx, queue);
5287 }
5288
5289 spin_unlock(&adapter->fdir_perfect_lock);
5290 }
5291
5292 /**
5293 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
5294 * @rx_ring: ring to free buffers from
5295 **/
ixgbe_clean_rx_ring(struct ixgbe_ring * rx_ring)5296 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
5297 {
5298 u16 i = rx_ring->next_to_clean;
5299 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
5300
5301 if (rx_ring->xsk_pool) {
5302 ixgbe_xsk_clean_rx_ring(rx_ring);
5303 goto skip_free;
5304 }
5305
5306 /* Free all the Rx ring sk_buffs */
5307 while (i != rx_ring->next_to_alloc) {
5308 if (rx_buffer->skb) {
5309 struct sk_buff *skb = rx_buffer->skb;
5310 if (IXGBE_CB(skb)->page_released)
5311 dma_unmap_page_attrs(rx_ring->dev,
5312 IXGBE_CB(skb)->dma,
5313 ixgbe_rx_pg_size(rx_ring),
5314 DMA_FROM_DEVICE,
5315 IXGBE_RX_DMA_ATTR);
5316 dev_kfree_skb(skb);
5317 }
5318
5319 /* Invalidate cache lines that may have been written to by
5320 * device so that we avoid corrupting memory.
5321 */
5322 dma_sync_single_range_for_cpu(rx_ring->dev,
5323 rx_buffer->dma,
5324 rx_buffer->page_offset,
5325 ixgbe_rx_bufsz(rx_ring),
5326 DMA_FROM_DEVICE);
5327
5328 /* free resources associated with mapping */
5329 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
5330 ixgbe_rx_pg_size(rx_ring),
5331 DMA_FROM_DEVICE,
5332 IXGBE_RX_DMA_ATTR);
5333 __page_frag_cache_drain(rx_buffer->page,
5334 rx_buffer->pagecnt_bias);
5335
5336 i++;
5337 rx_buffer++;
5338 if (i == rx_ring->count) {
5339 i = 0;
5340 rx_buffer = rx_ring->rx_buffer_info;
5341 }
5342 }
5343
5344 skip_free:
5345 rx_ring->next_to_alloc = 0;
5346 rx_ring->next_to_clean = 0;
5347 rx_ring->next_to_use = 0;
5348 }
5349
ixgbe_fwd_ring_up(struct ixgbe_adapter * adapter,struct ixgbe_fwd_adapter * accel)5350 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter,
5351 struct ixgbe_fwd_adapter *accel)
5352 {
5353 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
5354 int num_tc = netdev_get_num_tc(adapter->netdev);
5355 struct net_device *vdev = accel->netdev;
5356 int i, baseq, err;
5357
5358 baseq = accel->pool * adapter->num_rx_queues_per_pool;
5359 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n",
5360 accel->pool, adapter->num_rx_pools,
5361 baseq, baseq + adapter->num_rx_queues_per_pool);
5362
5363 accel->rx_base_queue = baseq;
5364 accel->tx_base_queue = baseq;
5365
5366 /* record configuration for macvlan interface in vdev */
5367 for (i = 0; i < num_tc; i++)
5368 netdev_bind_sb_channel_queue(adapter->netdev, vdev,
5369 i, rss_i, baseq + (rss_i * i));
5370
5371 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5372 adapter->rx_ring[baseq + i]->netdev = vdev;
5373
5374 /* Guarantee all rings are updated before we update the
5375 * MAC address filter.
5376 */
5377 wmb();
5378
5379 /* ixgbe_add_mac_filter will return an index if it succeeds, so we
5380 * need to only treat it as an error value if it is negative.
5381 */
5382 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr,
5383 VMDQ_P(accel->pool));
5384 if (err >= 0)
5385 return 0;
5386
5387 /* if we cannot add the MAC rule then disable the offload */
5388 macvlan_release_l2fw_offload(vdev);
5389
5390 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5391 adapter->rx_ring[baseq + i]->netdev = NULL;
5392
5393 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n");
5394
5395 /* unbind the queues and drop the subordinate channel config */
5396 netdev_unbind_sb_channel(adapter->netdev, vdev);
5397 netdev_set_sb_channel(vdev, 0);
5398
5399 clear_bit(accel->pool, adapter->fwd_bitmask);
5400 kfree(accel);
5401
5402 return err;
5403 }
5404
ixgbe_macvlan_up(struct net_device * vdev,struct netdev_nested_priv * priv)5405 static int ixgbe_macvlan_up(struct net_device *vdev,
5406 struct netdev_nested_priv *priv)
5407 {
5408 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
5409 struct ixgbe_fwd_adapter *accel;
5410
5411 if (!netif_is_macvlan(vdev))
5412 return 0;
5413
5414 accel = macvlan_accel_priv(vdev);
5415 if (!accel)
5416 return 0;
5417
5418 ixgbe_fwd_ring_up(adapter, accel);
5419
5420 return 0;
5421 }
5422
ixgbe_configure_dfwd(struct ixgbe_adapter * adapter)5423 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5424 {
5425 struct netdev_nested_priv priv = {
5426 .data = (void *)adapter,
5427 };
5428
5429 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5430 ixgbe_macvlan_up, &priv);
5431 }
5432
ixgbe_configure(struct ixgbe_adapter * adapter)5433 static void ixgbe_configure(struct ixgbe_adapter *adapter)
5434 {
5435 struct ixgbe_hw *hw = &adapter->hw;
5436
5437 ixgbe_configure_pb(adapter);
5438 #ifdef CONFIG_IXGBE_DCB
5439 ixgbe_configure_dcb(adapter);
5440 #endif
5441 /*
5442 * We must restore virtualization before VLANs or else
5443 * the VLVF registers will not be populated
5444 */
5445 ixgbe_configure_virtualization(adapter);
5446
5447 ixgbe_set_rx_mode(adapter->netdev);
5448 ixgbe_restore_vlan(adapter);
5449 ixgbe_ipsec_restore(adapter);
5450
5451 switch (hw->mac.type) {
5452 case ixgbe_mac_82599EB:
5453 case ixgbe_mac_X540:
5454 hw->mac.ops.disable_rx_buff(hw);
5455 break;
5456 default:
5457 break;
5458 }
5459
5460 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5461 ixgbe_init_fdir_signature_82599(&adapter->hw,
5462 adapter->fdir_pballoc);
5463 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5464 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5465 adapter->fdir_pballoc);
5466 ixgbe_fdir_filter_restore(adapter);
5467 }
5468
5469 switch (hw->mac.type) {
5470 case ixgbe_mac_82599EB:
5471 case ixgbe_mac_X540:
5472 hw->mac.ops.enable_rx_buff(hw);
5473 break;
5474 default:
5475 break;
5476 }
5477
5478 #ifdef CONFIG_IXGBE_DCA
5479 /* configure DCA */
5480 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5481 ixgbe_setup_dca(adapter);
5482 #endif /* CONFIG_IXGBE_DCA */
5483
5484 #ifdef IXGBE_FCOE
5485 /* configure FCoE L2 filters, redirection table, and Rx control */
5486 ixgbe_configure_fcoe(adapter);
5487
5488 #endif /* IXGBE_FCOE */
5489 ixgbe_configure_tx(adapter);
5490 ixgbe_configure_rx(adapter);
5491 ixgbe_configure_dfwd(adapter);
5492 }
5493
5494 /**
5495 * ixgbe_sfp_link_config - set up SFP+ link
5496 * @adapter: pointer to private adapter struct
5497 **/
ixgbe_sfp_link_config(struct ixgbe_adapter * adapter)5498 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5499 {
5500 /*
5501 * We are assuming the worst case scenario here, and that
5502 * is that an SFP was inserted/removed after the reset
5503 * but before SFP detection was enabled. As such the best
5504 * solution is to just start searching as soon as we start
5505 */
5506 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5507 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5508
5509 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5510 adapter->sfp_poll_time = 0;
5511 }
5512
5513 /**
5514 * ixgbe_non_sfp_link_config - set up non-SFP+ link
5515 * @hw: pointer to private hardware struct
5516 *
5517 * Returns 0 on success, negative on failure
5518 **/
ixgbe_non_sfp_link_config(struct ixgbe_hw * hw)5519 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
5520 {
5521 u32 speed;
5522 bool autoneg, link_up = false;
5523 int ret = IXGBE_ERR_LINK_SETUP;
5524
5525 if (hw->mac.ops.check_link)
5526 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
5527
5528 if (ret)
5529 return ret;
5530
5531 speed = hw->phy.autoneg_advertised;
5532 if (!speed && hw->mac.ops.get_link_capabilities) {
5533 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5534 &autoneg);
5535 /* remove NBASE-T speeds from default autonegotiation
5536 * to accommodate broken network switches in the field
5537 * which cannot cope with advertised NBASE-T speeds
5538 */
5539 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL |
5540 IXGBE_LINK_SPEED_2_5GB_FULL);
5541 }
5542
5543 if (ret)
5544 return ret;
5545
5546 if (hw->mac.ops.setup_link)
5547 ret = hw->mac.ops.setup_link(hw, speed, link_up);
5548
5549 return ret;
5550 }
5551
ixgbe_setup_gpie(struct ixgbe_adapter * adapter)5552 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
5553 {
5554 struct ixgbe_hw *hw = &adapter->hw;
5555 u32 gpie = 0;
5556
5557 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5558 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5559 IXGBE_GPIE_OCD;
5560 gpie |= IXGBE_GPIE_EIAME;
5561 /*
5562 * use EIAM to auto-mask when MSI-X interrupt is asserted
5563 * this saves a register write for every interrupt
5564 */
5565 switch (hw->mac.type) {
5566 case ixgbe_mac_82598EB:
5567 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5568 break;
5569 case ixgbe_mac_82599EB:
5570 case ixgbe_mac_X540:
5571 case ixgbe_mac_X550:
5572 case ixgbe_mac_X550EM_x:
5573 case ixgbe_mac_x550em_a:
5574 default:
5575 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5576 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5577 break;
5578 }
5579 } else {
5580 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5581 * specifically only auto mask tx and rx interrupts */
5582 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5583 }
5584
5585 /* XXX: to interrupt immediately for EICS writes, enable this */
5586 /* gpie |= IXGBE_GPIE_EIMEN; */
5587
5588 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5589 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
5590
5591 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5592 case IXGBE_82599_VMDQ_8Q_MASK:
5593 gpie |= IXGBE_GPIE_VTMODE_16;
5594 break;
5595 case IXGBE_82599_VMDQ_4Q_MASK:
5596 gpie |= IXGBE_GPIE_VTMODE_32;
5597 break;
5598 default:
5599 gpie |= IXGBE_GPIE_VTMODE_64;
5600 break;
5601 }
5602 }
5603
5604 /* Enable Thermal over heat sensor interrupt */
5605 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5606 switch (adapter->hw.mac.type) {
5607 case ixgbe_mac_82599EB:
5608 gpie |= IXGBE_SDP0_GPIEN_8259X;
5609 break;
5610 default:
5611 break;
5612 }
5613 }
5614
5615 /* Enable fan failure interrupt */
5616 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
5617 gpie |= IXGBE_SDP1_GPIEN(hw);
5618
5619 switch (hw->mac.type) {
5620 case ixgbe_mac_82599EB:
5621 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5622 break;
5623 case ixgbe_mac_X550EM_x:
5624 case ixgbe_mac_x550em_a:
5625 gpie |= IXGBE_SDP0_GPIEN_X540;
5626 break;
5627 default:
5628 break;
5629 }
5630
5631 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5632 }
5633
ixgbe_up_complete(struct ixgbe_adapter * adapter)5634 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5635 {
5636 struct ixgbe_hw *hw = &adapter->hw;
5637 int err;
5638 u32 ctrl_ext;
5639
5640 ixgbe_get_hw_control(adapter);
5641 ixgbe_setup_gpie(adapter);
5642
5643 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5644 ixgbe_configure_msix(adapter);
5645 else
5646 ixgbe_configure_msi_and_legacy(adapter);
5647
5648 /* enable the optics for 82599 SFP+ fiber */
5649 if (hw->mac.ops.enable_tx_laser)
5650 hw->mac.ops.enable_tx_laser(hw);
5651
5652 if (hw->phy.ops.set_phy_power)
5653 hw->phy.ops.set_phy_power(hw, true);
5654
5655 smp_mb__before_atomic();
5656 clear_bit(__IXGBE_DOWN, &adapter->state);
5657 ixgbe_napi_enable_all(adapter);
5658
5659 if (ixgbe_is_sfp(hw)) {
5660 ixgbe_sfp_link_config(adapter);
5661 } else {
5662 err = ixgbe_non_sfp_link_config(hw);
5663 if (err)
5664 e_err(probe, "link_config FAILED %d\n", err);
5665 }
5666
5667 /* clear any pending interrupts, may auto mask */
5668 IXGBE_READ_REG(hw, IXGBE_EICR);
5669 ixgbe_irq_enable(adapter, true, true);
5670
5671 /*
5672 * If this adapter has a fan, check to see if we had a failure
5673 * before we enabled the interrupt.
5674 */
5675 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5676 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5677 if (esdp & IXGBE_ESDP_SDP1)
5678 e_crit(drv, "Fan has stopped, replace the adapter\n");
5679 }
5680
5681 /* bring the link up in the watchdog, this could race with our first
5682 * link up interrupt but shouldn't be a problem */
5683 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5684 adapter->link_check_timeout = jiffies;
5685 mod_timer(&adapter->service_timer, jiffies);
5686
5687 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5688 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5689 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5690 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5691
5692 /* update setting rx tx for all active vfs */
5693 ixgbe_set_all_vfs(adapter);
5694 }
5695
ixgbe_reinit_locked(struct ixgbe_adapter * adapter)5696 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5697 {
5698 /* put off any impending NetWatchDogTimeout */
5699 netif_trans_update(adapter->netdev);
5700
5701 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5702 usleep_range(1000, 2000);
5703 if (adapter->hw.phy.type == ixgbe_phy_fw)
5704 ixgbe_watchdog_link_is_down(adapter);
5705 ixgbe_down(adapter);
5706 /*
5707 * If SR-IOV enabled then wait a bit before bringing the adapter
5708 * back up to give the VFs time to respond to the reset. The
5709 * two second wait is based upon the watchdog timer cycle in
5710 * the VF driver.
5711 */
5712 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5713 msleep(2000);
5714 ixgbe_up(adapter);
5715 clear_bit(__IXGBE_RESETTING, &adapter->state);
5716 }
5717
ixgbe_up(struct ixgbe_adapter * adapter)5718 void ixgbe_up(struct ixgbe_adapter *adapter)
5719 {
5720 /* hardware has been reset, we need to reload some things */
5721 ixgbe_configure(adapter);
5722
5723 ixgbe_up_complete(adapter);
5724 }
5725
ixgbe_get_completion_timeout(struct ixgbe_adapter * adapter)5726 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter)
5727 {
5728 u16 devctl2;
5729
5730 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2);
5731
5732 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) {
5733 case IXGBE_PCIDEVCTRL2_17_34s:
5734 case IXGBE_PCIDEVCTRL2_4_8s:
5735 /* For now we cap the upper limit on delay to 2 seconds
5736 * as we end up going up to 34 seconds of delay in worst
5737 * case timeout value.
5738 */
5739 case IXGBE_PCIDEVCTRL2_1_2s:
5740 return 2000000ul; /* 2.0 s */
5741 case IXGBE_PCIDEVCTRL2_260_520ms:
5742 return 520000ul; /* 520 ms */
5743 case IXGBE_PCIDEVCTRL2_65_130ms:
5744 return 130000ul; /* 130 ms */
5745 case IXGBE_PCIDEVCTRL2_16_32ms:
5746 return 32000ul; /* 32 ms */
5747 case IXGBE_PCIDEVCTRL2_1_2ms:
5748 return 2000ul; /* 2 ms */
5749 case IXGBE_PCIDEVCTRL2_50_100us:
5750 return 100ul; /* 100 us */
5751 case IXGBE_PCIDEVCTRL2_16_32ms_def:
5752 return 32000ul; /* 32 ms */
5753 default:
5754 break;
5755 }
5756
5757 /* We shouldn't need to hit this path, but just in case default as
5758 * though completion timeout is not supported and support 32ms.
5759 */
5760 return 32000ul;
5761 }
5762
ixgbe_disable_rx(struct ixgbe_adapter * adapter)5763 void ixgbe_disable_rx(struct ixgbe_adapter *adapter)
5764 {
5765 unsigned long wait_delay, delay_interval;
5766 struct ixgbe_hw *hw = &adapter->hw;
5767 int i, wait_loop;
5768 u32 rxdctl;
5769
5770 /* disable receives */
5771 hw->mac.ops.disable_rx(hw);
5772
5773 if (ixgbe_removed(hw->hw_addr))
5774 return;
5775
5776 /* disable all enabled Rx queues */
5777 for (i = 0; i < adapter->num_rx_queues; i++) {
5778 struct ixgbe_ring *ring = adapter->rx_ring[i];
5779 u8 reg_idx = ring->reg_idx;
5780
5781 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5782 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5783 rxdctl |= IXGBE_RXDCTL_SWFLSH;
5784
5785 /* write value back with RXDCTL.ENABLE bit cleared */
5786 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
5787 }
5788
5789 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
5790 if (hw->mac.type == ixgbe_mac_82598EB &&
5791 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5792 return;
5793
5794 /* Determine our minimum delay interval. We will increase this value
5795 * with each subsequent test. This way if the device returns quickly
5796 * we should spend as little time as possible waiting, however as
5797 * the time increases we will wait for larger periods of time.
5798 *
5799 * The trick here is that we increase the interval using the
5800 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5801 * of that wait is that it totals up to 100x whatever interval we
5802 * choose. Since our minimum wait is 100us we can just divide the
5803 * total timeout by 100 to get our minimum delay interval.
5804 */
5805 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5806
5807 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5808 wait_delay = delay_interval;
5809
5810 while (wait_loop--) {
5811 usleep_range(wait_delay, wait_delay + 10);
5812 wait_delay += delay_interval * 2;
5813 rxdctl = 0;
5814
5815 /* OR together the reading of all the active RXDCTL registers,
5816 * and then test the result. We need the disable to complete
5817 * before we start freeing the memory and invalidating the
5818 * DMA mappings.
5819 */
5820 for (i = 0; i < adapter->num_rx_queues; i++) {
5821 struct ixgbe_ring *ring = adapter->rx_ring[i];
5822 u8 reg_idx = ring->reg_idx;
5823
5824 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5825 }
5826
5827 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
5828 return;
5829 }
5830
5831 e_err(drv,
5832 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5833 }
5834
ixgbe_disable_tx(struct ixgbe_adapter * adapter)5835 void ixgbe_disable_tx(struct ixgbe_adapter *adapter)
5836 {
5837 unsigned long wait_delay, delay_interval;
5838 struct ixgbe_hw *hw = &adapter->hw;
5839 int i, wait_loop;
5840 u32 txdctl;
5841
5842 if (ixgbe_removed(hw->hw_addr))
5843 return;
5844
5845 /* disable all enabled Tx queues */
5846 for (i = 0; i < adapter->num_tx_queues; i++) {
5847 struct ixgbe_ring *ring = adapter->tx_ring[i];
5848 u8 reg_idx = ring->reg_idx;
5849
5850 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5851 }
5852
5853 /* disable all enabled XDP Tx queues */
5854 for (i = 0; i < adapter->num_xdp_queues; i++) {
5855 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5856 u8 reg_idx = ring->reg_idx;
5857
5858 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5859 }
5860
5861 /* If the link is not up there shouldn't be much in the way of
5862 * pending transactions. Those that are left will be flushed out
5863 * when the reset logic goes through the flush sequence to clean out
5864 * the pending Tx transactions.
5865 */
5866 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5867 goto dma_engine_disable;
5868
5869 /* Determine our minimum delay interval. We will increase this value
5870 * with each subsequent test. This way if the device returns quickly
5871 * we should spend as little time as possible waiting, however as
5872 * the time increases we will wait for larger periods of time.
5873 *
5874 * The trick here is that we increase the interval using the
5875 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5876 * of that wait is that it totals up to 100x whatever interval we
5877 * choose. Since our minimum wait is 100us we can just divide the
5878 * total timeout by 100 to get our minimum delay interval.
5879 */
5880 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5881
5882 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5883 wait_delay = delay_interval;
5884
5885 while (wait_loop--) {
5886 usleep_range(wait_delay, wait_delay + 10);
5887 wait_delay += delay_interval * 2;
5888 txdctl = 0;
5889
5890 /* OR together the reading of all the active TXDCTL registers,
5891 * and then test the result. We need the disable to complete
5892 * before we start freeing the memory and invalidating the
5893 * DMA mappings.
5894 */
5895 for (i = 0; i < adapter->num_tx_queues; i++) {
5896 struct ixgbe_ring *ring = adapter->tx_ring[i];
5897 u8 reg_idx = ring->reg_idx;
5898
5899 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5900 }
5901 for (i = 0; i < adapter->num_xdp_queues; i++) {
5902 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5903 u8 reg_idx = ring->reg_idx;
5904
5905 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5906 }
5907
5908 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
5909 goto dma_engine_disable;
5910 }
5911
5912 e_err(drv,
5913 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5914
5915 dma_engine_disable:
5916 /* Disable the Tx DMA engine on 82599 and later MAC */
5917 switch (hw->mac.type) {
5918 case ixgbe_mac_82599EB:
5919 case ixgbe_mac_X540:
5920 case ixgbe_mac_X550:
5921 case ixgbe_mac_X550EM_x:
5922 case ixgbe_mac_x550em_a:
5923 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5924 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5925 ~IXGBE_DMATXCTL_TE));
5926 fallthrough;
5927 default:
5928 break;
5929 }
5930 }
5931
ixgbe_reset(struct ixgbe_adapter * adapter)5932 void ixgbe_reset(struct ixgbe_adapter *adapter)
5933 {
5934 struct ixgbe_hw *hw = &adapter->hw;
5935 struct net_device *netdev = adapter->netdev;
5936 int err;
5937
5938 if (ixgbe_removed(hw->hw_addr))
5939 return;
5940 /* lock SFP init bit to prevent race conditions with the watchdog */
5941 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5942 usleep_range(1000, 2000);
5943
5944 /* clear all SFP and link config related flags while holding SFP_INIT */
5945 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5946 IXGBE_FLAG2_SFP_NEEDS_RESET);
5947 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5948
5949 err = hw->mac.ops.init_hw(hw);
5950 switch (err) {
5951 case 0:
5952 case IXGBE_ERR_SFP_NOT_PRESENT:
5953 case IXGBE_ERR_SFP_NOT_SUPPORTED:
5954 break;
5955 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5956 e_dev_err("master disable timed out\n");
5957 break;
5958 case IXGBE_ERR_EEPROM_VERSION:
5959 /* We are running on a pre-production device, log a warning */
5960 e_dev_warn("This device is a pre-production adapter/LOM. "
5961 "Please be aware there may be issues associated with "
5962 "your hardware. If you are experiencing problems "
5963 "please contact your Intel or hardware "
5964 "representative who provided you with this "
5965 "hardware.\n");
5966 break;
5967 default:
5968 e_dev_err("Hardware Error: %d\n", err);
5969 }
5970
5971 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5972
5973 /* flush entries out of MAC table */
5974 ixgbe_flush_sw_mac_table(adapter);
5975 __dev_uc_unsync(netdev, NULL);
5976
5977 /* do not flush user set addresses */
5978 ixgbe_mac_set_default_filter(adapter);
5979
5980 /* update SAN MAC vmdq pool selection */
5981 if (hw->mac.san_mac_rar_index)
5982 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5983
5984 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5985 ixgbe_ptp_reset(adapter);
5986
5987 if (hw->phy.ops.set_phy_power) {
5988 if (!netif_running(adapter->netdev) && !adapter->wol)
5989 hw->phy.ops.set_phy_power(hw, false);
5990 else
5991 hw->phy.ops.set_phy_power(hw, true);
5992 }
5993 }
5994
5995 /**
5996 * ixgbe_clean_tx_ring - Free Tx Buffers
5997 * @tx_ring: ring to be cleaned
5998 **/
ixgbe_clean_tx_ring(struct ixgbe_ring * tx_ring)5999 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
6000 {
6001 u16 i = tx_ring->next_to_clean;
6002 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
6003
6004 if (tx_ring->xsk_pool) {
6005 ixgbe_xsk_clean_tx_ring(tx_ring);
6006 goto out;
6007 }
6008
6009 while (i != tx_ring->next_to_use) {
6010 union ixgbe_adv_tx_desc *eop_desc, *tx_desc;
6011
6012 /* Free all the Tx ring sk_buffs */
6013 if (ring_is_xdp(tx_ring))
6014 xdp_return_frame(tx_buffer->xdpf);
6015 else
6016 dev_kfree_skb_any(tx_buffer->skb);
6017
6018 /* unmap skb header data */
6019 dma_unmap_single(tx_ring->dev,
6020 dma_unmap_addr(tx_buffer, dma),
6021 dma_unmap_len(tx_buffer, len),
6022 DMA_TO_DEVICE);
6023
6024 /* check for eop_desc to determine the end of the packet */
6025 eop_desc = tx_buffer->next_to_watch;
6026 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6027
6028 /* unmap remaining buffers */
6029 while (tx_desc != eop_desc) {
6030 tx_buffer++;
6031 tx_desc++;
6032 i++;
6033 if (unlikely(i == tx_ring->count)) {
6034 i = 0;
6035 tx_buffer = tx_ring->tx_buffer_info;
6036 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6037 }
6038
6039 /* unmap any remaining paged data */
6040 if (dma_unmap_len(tx_buffer, len))
6041 dma_unmap_page(tx_ring->dev,
6042 dma_unmap_addr(tx_buffer, dma),
6043 dma_unmap_len(tx_buffer, len),
6044 DMA_TO_DEVICE);
6045 }
6046
6047 /* move us one more past the eop_desc for start of next pkt */
6048 tx_buffer++;
6049 i++;
6050 if (unlikely(i == tx_ring->count)) {
6051 i = 0;
6052 tx_buffer = tx_ring->tx_buffer_info;
6053 }
6054 }
6055
6056 /* reset BQL for queue */
6057 if (!ring_is_xdp(tx_ring))
6058 netdev_tx_reset_queue(txring_txq(tx_ring));
6059
6060 out:
6061 /* reset next_to_use and next_to_clean */
6062 tx_ring->next_to_use = 0;
6063 tx_ring->next_to_clean = 0;
6064 }
6065
6066 /**
6067 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
6068 * @adapter: board private structure
6069 **/
ixgbe_clean_all_rx_rings(struct ixgbe_adapter * adapter)6070 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
6071 {
6072 int i;
6073
6074 for (i = 0; i < adapter->num_rx_queues; i++)
6075 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
6076 }
6077
6078 /**
6079 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
6080 * @adapter: board private structure
6081 **/
ixgbe_clean_all_tx_rings(struct ixgbe_adapter * adapter)6082 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
6083 {
6084 int i;
6085
6086 for (i = 0; i < adapter->num_tx_queues; i++)
6087 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
6088 for (i = 0; i < adapter->num_xdp_queues; i++)
6089 ixgbe_clean_tx_ring(adapter->xdp_ring[i]);
6090 }
6091
ixgbe_fdir_filter_exit(struct ixgbe_adapter * adapter)6092 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
6093 {
6094 struct hlist_node *node2;
6095 struct ixgbe_fdir_filter *filter;
6096
6097 spin_lock(&adapter->fdir_perfect_lock);
6098
6099 hlist_for_each_entry_safe(filter, node2,
6100 &adapter->fdir_filter_list, fdir_node) {
6101 hlist_del(&filter->fdir_node);
6102 kfree(filter);
6103 }
6104 adapter->fdir_filter_count = 0;
6105
6106 spin_unlock(&adapter->fdir_perfect_lock);
6107 }
6108
ixgbe_down(struct ixgbe_adapter * adapter)6109 void ixgbe_down(struct ixgbe_adapter *adapter)
6110 {
6111 struct net_device *netdev = adapter->netdev;
6112 struct ixgbe_hw *hw = &adapter->hw;
6113 int i;
6114
6115 /* signal that we are down to the interrupt handler */
6116 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
6117 return; /* do nothing if already down */
6118
6119 /* Shut off incoming Tx traffic */
6120 netif_tx_stop_all_queues(netdev);
6121
6122 /* call carrier off first to avoid false dev_watchdog timeouts */
6123 netif_carrier_off(netdev);
6124 netif_tx_disable(netdev);
6125
6126 /* Disable Rx */
6127 ixgbe_disable_rx(adapter);
6128
6129 /* synchronize_rcu() needed for pending XDP buffers to drain */
6130 if (adapter->xdp_ring[0])
6131 synchronize_rcu();
6132
6133 ixgbe_irq_disable(adapter);
6134
6135 ixgbe_napi_disable_all(adapter);
6136
6137 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
6138 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6139 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6140
6141 del_timer_sync(&adapter->service_timer);
6142
6143 if (adapter->num_vfs) {
6144 /* Clear EITR Select mapping */
6145 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
6146
6147 /* Mark all the VFs as inactive */
6148 for (i = 0 ; i < adapter->num_vfs; i++)
6149 adapter->vfinfo[i].clear_to_send = false;
6150
6151 /* update setting rx tx for all active vfs */
6152 ixgbe_set_all_vfs(adapter);
6153 }
6154
6155 /* disable transmits in the hardware now that interrupts are off */
6156 ixgbe_disable_tx(adapter);
6157
6158 if (!pci_channel_offline(adapter->pdev))
6159 ixgbe_reset(adapter);
6160
6161 /* power down the optics for 82599 SFP+ fiber */
6162 if (hw->mac.ops.disable_tx_laser)
6163 hw->mac.ops.disable_tx_laser(hw);
6164
6165 ixgbe_clean_all_tx_rings(adapter);
6166 ixgbe_clean_all_rx_rings(adapter);
6167 }
6168
6169 /**
6170 * ixgbe_eee_capable - helper function to determine EEE support on X550
6171 * @adapter: board private structure
6172 */
ixgbe_set_eee_capable(struct ixgbe_adapter * adapter)6173 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter)
6174 {
6175 struct ixgbe_hw *hw = &adapter->hw;
6176
6177 switch (hw->device_id) {
6178 case IXGBE_DEV_ID_X550EM_A_1G_T:
6179 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6180 if (!hw->phy.eee_speeds_supported)
6181 break;
6182 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE;
6183 if (!hw->phy.eee_speeds_advertised)
6184 break;
6185 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
6186 break;
6187 default:
6188 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE;
6189 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
6190 break;
6191 }
6192 }
6193
6194 /**
6195 * ixgbe_tx_timeout - Respond to a Tx Hang
6196 * @netdev: network interface device structure
6197 * @txqueue: queue number that timed out
6198 **/
ixgbe_tx_timeout(struct net_device * netdev,unsigned int __always_unused txqueue)6199 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6200 {
6201 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6202
6203 /* Do the reset outside of interrupt context */
6204 ixgbe_tx_timeout_reset(adapter);
6205 }
6206
6207 #ifdef CONFIG_IXGBE_DCB
ixgbe_init_dcb(struct ixgbe_adapter * adapter)6208 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
6209 {
6210 struct ixgbe_hw *hw = &adapter->hw;
6211 struct tc_configuration *tc;
6212 int j;
6213
6214 switch (hw->mac.type) {
6215 case ixgbe_mac_82598EB:
6216 case ixgbe_mac_82599EB:
6217 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
6218 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
6219 break;
6220 case ixgbe_mac_X540:
6221 case ixgbe_mac_X550:
6222 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
6223 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
6224 break;
6225 case ixgbe_mac_X550EM_x:
6226 case ixgbe_mac_x550em_a:
6227 default:
6228 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
6229 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
6230 break;
6231 }
6232
6233 /* Configure DCB traffic classes */
6234 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
6235 tc = &adapter->dcb_cfg.tc_config[j];
6236 tc->path[DCB_TX_CONFIG].bwg_id = 0;
6237 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
6238 tc->path[DCB_RX_CONFIG].bwg_id = 0;
6239 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
6240 tc->dcb_pfc = pfc_disabled;
6241 }
6242
6243 /* Initialize default user to priority mapping, UPx->TC0 */
6244 tc = &adapter->dcb_cfg.tc_config[0];
6245 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
6246 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
6247
6248 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
6249 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
6250 adapter->dcb_cfg.pfc_mode_enable = false;
6251 adapter->dcb_set_bitmap = 0x00;
6252 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
6253 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
6254 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
6255 sizeof(adapter->temp_dcb_cfg));
6256 }
6257 #endif
6258
6259 /**
6260 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
6261 * @adapter: board private structure to initialize
6262 * @ii: pointer to ixgbe_info for device
6263 *
6264 * ixgbe_sw_init initializes the Adapter private data structure.
6265 * Fields are initialized based on PCI device information and
6266 * OS network device settings (MTU size).
6267 **/
ixgbe_sw_init(struct ixgbe_adapter * adapter,const struct ixgbe_info * ii)6268 static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
6269 const struct ixgbe_info *ii)
6270 {
6271 struct ixgbe_hw *hw = &adapter->hw;
6272 struct pci_dev *pdev = adapter->pdev;
6273 unsigned int rss, fdir;
6274 u32 fwsm;
6275 int i;
6276
6277 /* PCI config space info */
6278
6279 hw->vendor_id = pdev->vendor;
6280 hw->device_id = pdev->device;
6281 hw->revision_id = pdev->revision;
6282 hw->subsystem_vendor_id = pdev->subsystem_vendor;
6283 hw->subsystem_device_id = pdev->subsystem_device;
6284
6285 /* get_invariants needs the device IDs */
6286 ii->get_invariants(hw);
6287
6288 /* Set common capability flags and settings */
6289 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
6290 adapter->ring_feature[RING_F_RSS].limit = rss;
6291 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
6292 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
6293 adapter->atr_sample_rate = 20;
6294 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
6295 adapter->ring_feature[RING_F_FDIR].limit = fdir;
6296 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
6297 adapter->ring_feature[RING_F_VMDQ].limit = 1;
6298 #ifdef CONFIG_IXGBE_DCA
6299 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
6300 #endif
6301 #ifdef CONFIG_IXGBE_DCB
6302 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
6303 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6304 #endif
6305 #ifdef IXGBE_FCOE
6306 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
6307 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6308 #ifdef CONFIG_IXGBE_DCB
6309 /* Default traffic class to use for FCoE */
6310 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
6311 #endif /* CONFIG_IXGBE_DCB */
6312 #endif /* IXGBE_FCOE */
6313
6314 /* initialize static ixgbe jump table entries */
6315 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
6316 GFP_KERNEL);
6317 if (!adapter->jump_tables[0])
6318 return -ENOMEM;
6319 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
6320
6321 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
6322 adapter->jump_tables[i] = NULL;
6323
6324 adapter->mac_table = kcalloc(hw->mac.num_rar_entries,
6325 sizeof(struct ixgbe_mac_addr),
6326 GFP_KERNEL);
6327 if (!adapter->mac_table)
6328 return -ENOMEM;
6329
6330 if (ixgbe_init_rss_key(adapter))
6331 return -ENOMEM;
6332
6333 adapter->af_xdp_zc_qps = bitmap_zalloc(MAX_XDP_QUEUES, GFP_KERNEL);
6334 if (!adapter->af_xdp_zc_qps)
6335 return -ENOMEM;
6336
6337 /* Set MAC specific capability flags and exceptions */
6338 switch (hw->mac.type) {
6339 case ixgbe_mac_82598EB:
6340 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
6341
6342 if (hw->device_id == IXGBE_DEV_ID_82598AT)
6343 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
6344
6345 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
6346 adapter->ring_feature[RING_F_FDIR].limit = 0;
6347 adapter->atr_sample_rate = 0;
6348 adapter->fdir_pballoc = 0;
6349 #ifdef IXGBE_FCOE
6350 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6351 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6352 #ifdef CONFIG_IXGBE_DCB
6353 adapter->fcoe.up = 0;
6354 #endif /* IXGBE_DCB */
6355 #endif /* IXGBE_FCOE */
6356 break;
6357 case ixgbe_mac_82599EB:
6358 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
6359 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6360 break;
6361 case ixgbe_mac_X540:
6362 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
6363 if (fwsm & IXGBE_FWSM_TS_ENABLED)
6364 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6365 break;
6366 case ixgbe_mac_x550em_a:
6367 switch (hw->device_id) {
6368 case IXGBE_DEV_ID_X550EM_A_1G_T:
6369 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6370 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6371 break;
6372 default:
6373 break;
6374 }
6375 fallthrough;
6376 case ixgbe_mac_X550EM_x:
6377 #ifdef CONFIG_IXGBE_DCB
6378 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
6379 #endif
6380 #ifdef IXGBE_FCOE
6381 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6382 #ifdef CONFIG_IXGBE_DCB
6383 adapter->fcoe.up = 0;
6384 #endif /* IXGBE_DCB */
6385 #endif /* IXGBE_FCOE */
6386 fallthrough;
6387 case ixgbe_mac_X550:
6388 if (hw->mac.type == ixgbe_mac_X550)
6389 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6390 #ifdef CONFIG_IXGBE_DCA
6391 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
6392 #endif
6393 break;
6394 default:
6395 break;
6396 }
6397
6398 #ifdef IXGBE_FCOE
6399 /* FCoE support exists, always init the FCoE lock */
6400 spin_lock_init(&adapter->fcoe.lock);
6401
6402 #endif
6403 /* n-tuple support exists, always init our spinlock */
6404 spin_lock_init(&adapter->fdir_perfect_lock);
6405
6406 /* init spinlock to avoid concurrency of VF resources */
6407 spin_lock_init(&adapter->vfs_lock);
6408
6409 #ifdef CONFIG_IXGBE_DCB
6410 ixgbe_init_dcb(adapter);
6411 #endif
6412 ixgbe_init_ipsec_offload(adapter);
6413
6414 /* default flow control settings */
6415 hw->fc.requested_mode = ixgbe_fc_full;
6416 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
6417 ixgbe_pbthresh_setup(adapter);
6418 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
6419 hw->fc.send_xon = true;
6420 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
6421
6422 #ifdef CONFIG_PCI_IOV
6423 if (max_vfs > 0)
6424 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
6425
6426 /* assign number of SR-IOV VFs */
6427 if (hw->mac.type != ixgbe_mac_82598EB) {
6428 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
6429 max_vfs = 0;
6430 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
6431 }
6432 }
6433 #endif /* CONFIG_PCI_IOV */
6434
6435 /* enable itr by default in dynamic mode */
6436 adapter->rx_itr_setting = 1;
6437 adapter->tx_itr_setting = 1;
6438
6439 /* set default ring sizes */
6440 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
6441 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
6442
6443 /* set default work limits */
6444 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
6445
6446 /* initialize eeprom parameters */
6447 if (ixgbe_init_eeprom_params_generic(hw)) {
6448 e_dev_err("EEPROM initialization failed\n");
6449 return -EIO;
6450 }
6451
6452 /* PF holds first pool slot */
6453 set_bit(0, adapter->fwd_bitmask);
6454 set_bit(__IXGBE_DOWN, &adapter->state);
6455
6456 return 0;
6457 }
6458
6459 /**
6460 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
6461 * @tx_ring: tx descriptor ring (for a specific queue) to setup
6462 *
6463 * Return 0 on success, negative on failure
6464 **/
ixgbe_setup_tx_resources(struct ixgbe_ring * tx_ring)6465 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
6466 {
6467 struct device *dev = tx_ring->dev;
6468 int orig_node = dev_to_node(dev);
6469 int ring_node = NUMA_NO_NODE;
6470 int size;
6471
6472 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
6473
6474 if (tx_ring->q_vector)
6475 ring_node = tx_ring->q_vector->numa_node;
6476
6477 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node);
6478 if (!tx_ring->tx_buffer_info)
6479 tx_ring->tx_buffer_info = vmalloc(size);
6480 if (!tx_ring->tx_buffer_info)
6481 goto err;
6482
6483 /* round up to nearest 4K */
6484 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
6485 tx_ring->size = ALIGN(tx_ring->size, 4096);
6486
6487 set_dev_node(dev, ring_node);
6488 tx_ring->desc = dma_alloc_coherent(dev,
6489 tx_ring->size,
6490 &tx_ring->dma,
6491 GFP_KERNEL);
6492 set_dev_node(dev, orig_node);
6493 if (!tx_ring->desc)
6494 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
6495 &tx_ring->dma, GFP_KERNEL);
6496 if (!tx_ring->desc)
6497 goto err;
6498
6499 tx_ring->next_to_use = 0;
6500 tx_ring->next_to_clean = 0;
6501 return 0;
6502
6503 err:
6504 vfree(tx_ring->tx_buffer_info);
6505 tx_ring->tx_buffer_info = NULL;
6506 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
6507 return -ENOMEM;
6508 }
6509
6510 /**
6511 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
6512 * @adapter: board private structure
6513 *
6514 * If this function returns with an error, then it's possible one or
6515 * more of the rings is populated (while the rest are not). It is the
6516 * callers duty to clean those orphaned rings.
6517 *
6518 * Return 0 on success, negative on failure
6519 **/
ixgbe_setup_all_tx_resources(struct ixgbe_adapter * adapter)6520 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
6521 {
6522 int i, j = 0, err = 0;
6523
6524 for (i = 0; i < adapter->num_tx_queues; i++) {
6525 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
6526 if (!err)
6527 continue;
6528
6529 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
6530 goto err_setup_tx;
6531 }
6532 for (j = 0; j < adapter->num_xdp_queues; j++) {
6533 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]);
6534 if (!err)
6535 continue;
6536
6537 e_err(probe, "Allocation for Tx Queue %u failed\n", j);
6538 goto err_setup_tx;
6539 }
6540
6541 return 0;
6542 err_setup_tx:
6543 /* rewind the index freeing the rings as we go */
6544 while (j--)
6545 ixgbe_free_tx_resources(adapter->xdp_ring[j]);
6546 while (i--)
6547 ixgbe_free_tx_resources(adapter->tx_ring[i]);
6548 return err;
6549 }
6550
6551 /**
6552 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
6553 * @adapter: pointer to ixgbe_adapter
6554 * @rx_ring: rx descriptor ring (for a specific queue) to setup
6555 *
6556 * Returns 0 on success, negative on failure
6557 **/
ixgbe_setup_rx_resources(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring)6558 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
6559 struct ixgbe_ring *rx_ring)
6560 {
6561 struct device *dev = rx_ring->dev;
6562 int orig_node = dev_to_node(dev);
6563 int ring_node = NUMA_NO_NODE;
6564 int size;
6565
6566 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
6567
6568 if (rx_ring->q_vector)
6569 ring_node = rx_ring->q_vector->numa_node;
6570
6571 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node);
6572 if (!rx_ring->rx_buffer_info)
6573 rx_ring->rx_buffer_info = vmalloc(size);
6574 if (!rx_ring->rx_buffer_info)
6575 goto err;
6576
6577 /* Round up to nearest 4K */
6578 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
6579 rx_ring->size = ALIGN(rx_ring->size, 4096);
6580
6581 set_dev_node(dev, ring_node);
6582 rx_ring->desc = dma_alloc_coherent(dev,
6583 rx_ring->size,
6584 &rx_ring->dma,
6585 GFP_KERNEL);
6586 set_dev_node(dev, orig_node);
6587 if (!rx_ring->desc)
6588 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
6589 &rx_ring->dma, GFP_KERNEL);
6590 if (!rx_ring->desc)
6591 goto err;
6592
6593 rx_ring->next_to_clean = 0;
6594 rx_ring->next_to_use = 0;
6595
6596 /* XDP RX-queue info */
6597 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev,
6598 rx_ring->queue_index) < 0)
6599 goto err;
6600
6601 rx_ring->xdp_prog = adapter->xdp_prog;
6602
6603 return 0;
6604 err:
6605 vfree(rx_ring->rx_buffer_info);
6606 rx_ring->rx_buffer_info = NULL;
6607 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
6608 return -ENOMEM;
6609 }
6610
6611 /**
6612 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
6613 * @adapter: board private structure
6614 *
6615 * If this function returns with an error, then it's possible one or
6616 * more of the rings is populated (while the rest are not). It is the
6617 * callers duty to clean those orphaned rings.
6618 *
6619 * Return 0 on success, negative on failure
6620 **/
ixgbe_setup_all_rx_resources(struct ixgbe_adapter * adapter)6621 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
6622 {
6623 int i, err = 0;
6624
6625 for (i = 0; i < adapter->num_rx_queues; i++) {
6626 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
6627 if (!err)
6628 continue;
6629
6630 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
6631 goto err_setup_rx;
6632 }
6633
6634 #ifdef IXGBE_FCOE
6635 err = ixgbe_setup_fcoe_ddp_resources(adapter);
6636 if (!err)
6637 #endif
6638 return 0;
6639 err_setup_rx:
6640 /* rewind the index freeing the rings as we go */
6641 while (i--)
6642 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6643 return err;
6644 }
6645
6646 /**
6647 * ixgbe_free_tx_resources - Free Tx Resources per Queue
6648 * @tx_ring: Tx descriptor ring for a specific queue
6649 *
6650 * Free all transmit software resources
6651 **/
ixgbe_free_tx_resources(struct ixgbe_ring * tx_ring)6652 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
6653 {
6654 ixgbe_clean_tx_ring(tx_ring);
6655
6656 vfree(tx_ring->tx_buffer_info);
6657 tx_ring->tx_buffer_info = NULL;
6658
6659 /* if not set, then don't free */
6660 if (!tx_ring->desc)
6661 return;
6662
6663 dma_free_coherent(tx_ring->dev, tx_ring->size,
6664 tx_ring->desc, tx_ring->dma);
6665
6666 tx_ring->desc = NULL;
6667 }
6668
6669 /**
6670 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
6671 * @adapter: board private structure
6672 *
6673 * Free all transmit software resources
6674 **/
ixgbe_free_all_tx_resources(struct ixgbe_adapter * adapter)6675 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6676 {
6677 int i;
6678
6679 for (i = 0; i < adapter->num_tx_queues; i++)
6680 if (adapter->tx_ring[i]->desc)
6681 ixgbe_free_tx_resources(adapter->tx_ring[i]);
6682 for (i = 0; i < adapter->num_xdp_queues; i++)
6683 if (adapter->xdp_ring[i]->desc)
6684 ixgbe_free_tx_resources(adapter->xdp_ring[i]);
6685 }
6686
6687 /**
6688 * ixgbe_free_rx_resources - Free Rx Resources
6689 * @rx_ring: ring to clean the resources from
6690 *
6691 * Free all receive software resources
6692 **/
ixgbe_free_rx_resources(struct ixgbe_ring * rx_ring)6693 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
6694 {
6695 ixgbe_clean_rx_ring(rx_ring);
6696
6697 rx_ring->xdp_prog = NULL;
6698 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
6699 vfree(rx_ring->rx_buffer_info);
6700 rx_ring->rx_buffer_info = NULL;
6701
6702 /* if not set, then don't free */
6703 if (!rx_ring->desc)
6704 return;
6705
6706 dma_free_coherent(rx_ring->dev, rx_ring->size,
6707 rx_ring->desc, rx_ring->dma);
6708
6709 rx_ring->desc = NULL;
6710 }
6711
6712 /**
6713 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6714 * @adapter: board private structure
6715 *
6716 * Free all receive software resources
6717 **/
ixgbe_free_all_rx_resources(struct ixgbe_adapter * adapter)6718 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6719 {
6720 int i;
6721
6722 #ifdef IXGBE_FCOE
6723 ixgbe_free_fcoe_ddp_resources(adapter);
6724
6725 #endif
6726 for (i = 0; i < adapter->num_rx_queues; i++)
6727 if (adapter->rx_ring[i]->desc)
6728 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6729 }
6730
6731 /**
6732 * ixgbe_max_xdp_frame_size - returns the maximum allowed frame size for XDP
6733 * @adapter: device handle, pointer to adapter
6734 */
ixgbe_max_xdp_frame_size(struct ixgbe_adapter * adapter)6735 static int ixgbe_max_xdp_frame_size(struct ixgbe_adapter *adapter)
6736 {
6737 if (PAGE_SIZE >= 8192 || adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
6738 return IXGBE_RXBUFFER_2K;
6739 else
6740 return IXGBE_RXBUFFER_3K;
6741 }
6742
6743 /**
6744 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6745 * @netdev: network interface device structure
6746 * @new_mtu: new value for maximum frame size
6747 *
6748 * Returns 0 on success, negative on failure
6749 **/
ixgbe_change_mtu(struct net_device * netdev,int new_mtu)6750 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6751 {
6752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6753
6754 if (ixgbe_enabled_xdp_adapter(adapter)) {
6755 int new_frame_size = new_mtu + IXGBE_PKT_HDR_PAD;
6756
6757 if (new_frame_size > ixgbe_max_xdp_frame_size(adapter)) {
6758 e_warn(probe, "Requested MTU size is not supported with XDP\n");
6759 return -EINVAL;
6760 }
6761 }
6762
6763 /*
6764 * For 82599EB we cannot allow legacy VFs to enable their receive
6765 * paths when MTU greater than 1500 is configured. So display a
6766 * warning that legacy VFs will be disabled.
6767 */
6768 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6769 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
6770 (new_mtu > ETH_DATA_LEN))
6771 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
6772
6773 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6774 netdev->mtu, new_mtu);
6775
6776 /* must set new MTU before calling down or up */
6777 netdev->mtu = new_mtu;
6778
6779 if (netif_running(netdev))
6780 ixgbe_reinit_locked(adapter);
6781
6782 return 0;
6783 }
6784
6785 /**
6786 * ixgbe_open - Called when a network interface is made active
6787 * @netdev: network interface device structure
6788 *
6789 * Returns 0 on success, negative value on failure
6790 *
6791 * The open entry point is called when a network interface is made
6792 * active by the system (IFF_UP). At this point all resources needed
6793 * for transmit and receive operations are allocated, the interrupt
6794 * handler is registered with the OS, the watchdog timer is started,
6795 * and the stack is notified that the interface is ready.
6796 **/
ixgbe_open(struct net_device * netdev)6797 int ixgbe_open(struct net_device *netdev)
6798 {
6799 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6800 struct ixgbe_hw *hw = &adapter->hw;
6801 int err, queues;
6802
6803 /* disallow open during test */
6804 if (test_bit(__IXGBE_TESTING, &adapter->state))
6805 return -EBUSY;
6806
6807 netif_carrier_off(netdev);
6808
6809 /* allocate transmit descriptors */
6810 err = ixgbe_setup_all_tx_resources(adapter);
6811 if (err)
6812 goto err_setup_tx;
6813
6814 /* allocate receive descriptors */
6815 err = ixgbe_setup_all_rx_resources(adapter);
6816 if (err)
6817 goto err_setup_rx;
6818
6819 ixgbe_configure(adapter);
6820
6821 err = ixgbe_request_irq(adapter);
6822 if (err)
6823 goto err_req_irq;
6824
6825 /* Notify the stack of the actual queue counts. */
6826 queues = adapter->num_tx_queues;
6827 err = netif_set_real_num_tx_queues(netdev, queues);
6828 if (err)
6829 goto err_set_queues;
6830
6831 queues = adapter->num_rx_queues;
6832 err = netif_set_real_num_rx_queues(netdev, queues);
6833 if (err)
6834 goto err_set_queues;
6835
6836 ixgbe_ptp_init(adapter);
6837
6838 ixgbe_up_complete(adapter);
6839
6840 udp_tunnel_nic_reset_ntf(netdev);
6841
6842 return 0;
6843
6844 err_set_queues:
6845 ixgbe_free_irq(adapter);
6846 err_req_irq:
6847 ixgbe_free_all_rx_resources(adapter);
6848 if (hw->phy.ops.set_phy_power && !adapter->wol)
6849 hw->phy.ops.set_phy_power(&adapter->hw, false);
6850 err_setup_rx:
6851 ixgbe_free_all_tx_resources(adapter);
6852 err_setup_tx:
6853 ixgbe_reset(adapter);
6854
6855 return err;
6856 }
6857
ixgbe_close_suspend(struct ixgbe_adapter * adapter)6858 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6859 {
6860 ixgbe_ptp_suspend(adapter);
6861
6862 if (adapter->hw.phy.ops.enter_lplu) {
6863 adapter->hw.phy.reset_disable = true;
6864 ixgbe_down(adapter);
6865 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6866 adapter->hw.phy.reset_disable = false;
6867 } else {
6868 ixgbe_down(adapter);
6869 }
6870
6871 ixgbe_free_irq(adapter);
6872
6873 ixgbe_free_all_tx_resources(adapter);
6874 ixgbe_free_all_rx_resources(adapter);
6875 }
6876
6877 /**
6878 * ixgbe_close - Disables a network interface
6879 * @netdev: network interface device structure
6880 *
6881 * Returns 0, this is not allowed to fail
6882 *
6883 * The close entry point is called when an interface is de-activated
6884 * by the OS. The hardware is still under the drivers control, but
6885 * needs to be disabled. A global MAC reset is issued to stop the
6886 * hardware, and all transmit and receive resources are freed.
6887 **/
ixgbe_close(struct net_device * netdev)6888 int ixgbe_close(struct net_device *netdev)
6889 {
6890 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6891
6892 ixgbe_ptp_stop(adapter);
6893
6894 if (netif_device_present(netdev))
6895 ixgbe_close_suspend(adapter);
6896
6897 ixgbe_fdir_filter_exit(adapter);
6898
6899 ixgbe_release_hw_control(adapter);
6900
6901 return 0;
6902 }
6903
ixgbe_resume(struct device * dev_d)6904 static int __maybe_unused ixgbe_resume(struct device *dev_d)
6905 {
6906 struct pci_dev *pdev = to_pci_dev(dev_d);
6907 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6908 struct net_device *netdev = adapter->netdev;
6909 u32 err;
6910
6911 adapter->hw.hw_addr = adapter->io_addr;
6912
6913 err = pci_enable_device_mem(pdev);
6914 if (err) {
6915 e_dev_err("Cannot enable PCI device from suspend\n");
6916 return err;
6917 }
6918 smp_mb__before_atomic();
6919 clear_bit(__IXGBE_DISABLED, &adapter->state);
6920 pci_set_master(pdev);
6921
6922 device_wakeup_disable(dev_d);
6923
6924 ixgbe_reset(adapter);
6925
6926 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6927
6928 rtnl_lock();
6929 err = ixgbe_init_interrupt_scheme(adapter);
6930 if (!err && netif_running(netdev))
6931 err = ixgbe_open(netdev);
6932
6933
6934 if (!err)
6935 netif_device_attach(netdev);
6936 rtnl_unlock();
6937
6938 return err;
6939 }
6940
__ixgbe_shutdown(struct pci_dev * pdev,bool * enable_wake)6941 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
6942 {
6943 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6944 struct net_device *netdev = adapter->netdev;
6945 struct ixgbe_hw *hw = &adapter->hw;
6946 u32 ctrl;
6947 u32 wufc = adapter->wol;
6948
6949 rtnl_lock();
6950 netif_device_detach(netdev);
6951
6952 if (netif_running(netdev))
6953 ixgbe_close_suspend(adapter);
6954
6955 ixgbe_clear_interrupt_scheme(adapter);
6956 rtnl_unlock();
6957
6958 if (hw->mac.ops.stop_link_on_d3)
6959 hw->mac.ops.stop_link_on_d3(hw);
6960
6961 if (wufc) {
6962 u32 fctrl;
6963
6964 ixgbe_set_rx_mode(netdev);
6965
6966 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6967 if (hw->mac.ops.enable_tx_laser)
6968 hw->mac.ops.enable_tx_laser(hw);
6969
6970 /* enable the reception of multicast packets */
6971 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6972 fctrl |= IXGBE_FCTRL_MPE;
6973 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6974
6975 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6976 ctrl |= IXGBE_CTRL_GIO_DIS;
6977 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6978
6979 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6980 } else {
6981 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6982 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6983 }
6984
6985 switch (hw->mac.type) {
6986 case ixgbe_mac_82598EB:
6987 pci_wake_from_d3(pdev, false);
6988 break;
6989 case ixgbe_mac_82599EB:
6990 case ixgbe_mac_X540:
6991 case ixgbe_mac_X550:
6992 case ixgbe_mac_X550EM_x:
6993 case ixgbe_mac_x550em_a:
6994 pci_wake_from_d3(pdev, !!wufc);
6995 break;
6996 default:
6997 break;
6998 }
6999
7000 *enable_wake = !!wufc;
7001 if (hw->phy.ops.set_phy_power && !*enable_wake)
7002 hw->phy.ops.set_phy_power(hw, false);
7003
7004 ixgbe_release_hw_control(adapter);
7005
7006 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
7007 pci_disable_device(pdev);
7008
7009 return 0;
7010 }
7011
ixgbe_suspend(struct device * dev_d)7012 static int __maybe_unused ixgbe_suspend(struct device *dev_d)
7013 {
7014 struct pci_dev *pdev = to_pci_dev(dev_d);
7015 int retval;
7016 bool wake;
7017
7018 retval = __ixgbe_shutdown(pdev, &wake);
7019
7020 device_set_wakeup_enable(dev_d, wake);
7021
7022 return retval;
7023 }
7024
ixgbe_shutdown(struct pci_dev * pdev)7025 static void ixgbe_shutdown(struct pci_dev *pdev)
7026 {
7027 bool wake;
7028
7029 __ixgbe_shutdown(pdev, &wake);
7030
7031 if (system_state == SYSTEM_POWER_OFF) {
7032 pci_wake_from_d3(pdev, wake);
7033 pci_set_power_state(pdev, PCI_D3hot);
7034 }
7035 }
7036
7037 /**
7038 * ixgbe_update_stats - Update the board statistics counters.
7039 * @adapter: board private structure
7040 **/
ixgbe_update_stats(struct ixgbe_adapter * adapter)7041 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
7042 {
7043 struct net_device *netdev = adapter->netdev;
7044 struct ixgbe_hw *hw = &adapter->hw;
7045 struct ixgbe_hw_stats *hwstats = &adapter->stats;
7046 u64 total_mpc = 0;
7047 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
7048 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
7049 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
7050 u64 alloc_rx_page = 0;
7051 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7052
7053 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7054 test_bit(__IXGBE_RESETTING, &adapter->state))
7055 return;
7056
7057 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
7058 u64 rsc_count = 0;
7059 u64 rsc_flush = 0;
7060 for (i = 0; i < adapter->num_rx_queues; i++) {
7061 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
7062 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
7063 }
7064 adapter->rsc_total_count = rsc_count;
7065 adapter->rsc_total_flush = rsc_flush;
7066 }
7067
7068 for (i = 0; i < adapter->num_rx_queues; i++) {
7069 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]);
7070
7071 if (!rx_ring)
7072 continue;
7073 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
7074 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page;
7075 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
7076 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
7077 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
7078 bytes += rx_ring->stats.bytes;
7079 packets += rx_ring->stats.packets;
7080 }
7081 adapter->non_eop_descs = non_eop_descs;
7082 adapter->alloc_rx_page = alloc_rx_page;
7083 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
7084 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
7085 adapter->hw_csum_rx_error = hw_csum_rx_error;
7086 netdev->stats.rx_bytes = bytes;
7087 netdev->stats.rx_packets = packets;
7088
7089 bytes = 0;
7090 packets = 0;
7091 /* gather some stats to the adapter struct that are per queue */
7092 for (i = 0; i < adapter->num_tx_queues; i++) {
7093 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]);
7094
7095 if (!tx_ring)
7096 continue;
7097 restart_queue += tx_ring->tx_stats.restart_queue;
7098 tx_busy += tx_ring->tx_stats.tx_busy;
7099 bytes += tx_ring->stats.bytes;
7100 packets += tx_ring->stats.packets;
7101 }
7102 for (i = 0; i < adapter->num_xdp_queues; i++) {
7103 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]);
7104
7105 if (!xdp_ring)
7106 continue;
7107 restart_queue += xdp_ring->tx_stats.restart_queue;
7108 tx_busy += xdp_ring->tx_stats.tx_busy;
7109 bytes += xdp_ring->stats.bytes;
7110 packets += xdp_ring->stats.packets;
7111 }
7112 adapter->restart_queue = restart_queue;
7113 adapter->tx_busy = tx_busy;
7114 netdev->stats.tx_bytes = bytes;
7115 netdev->stats.tx_packets = packets;
7116
7117 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
7118
7119 /* 8 register reads */
7120 for (i = 0; i < 8; i++) {
7121 /* for packet buffers not used, the register should read 0 */
7122 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
7123 missed_rx += mpc;
7124 hwstats->mpc[i] += mpc;
7125 total_mpc += hwstats->mpc[i];
7126 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
7127 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
7128 switch (hw->mac.type) {
7129 case ixgbe_mac_82598EB:
7130 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
7131 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
7132 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7133 hwstats->pxonrxc[i] +=
7134 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
7135 break;
7136 case ixgbe_mac_82599EB:
7137 case ixgbe_mac_X540:
7138 case ixgbe_mac_X550:
7139 case ixgbe_mac_X550EM_x:
7140 case ixgbe_mac_x550em_a:
7141 hwstats->pxonrxc[i] +=
7142 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
7143 break;
7144 default:
7145 break;
7146 }
7147 }
7148
7149 /*16 register reads */
7150 for (i = 0; i < 16; i++) {
7151 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
7152 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
7153 if ((hw->mac.type == ixgbe_mac_82599EB) ||
7154 (hw->mac.type == ixgbe_mac_X540) ||
7155 (hw->mac.type == ixgbe_mac_X550) ||
7156 (hw->mac.type == ixgbe_mac_X550EM_x) ||
7157 (hw->mac.type == ixgbe_mac_x550em_a)) {
7158 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
7159 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
7160 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
7161 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
7162 }
7163 }
7164
7165 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
7166 /* work around hardware counting issue */
7167 hwstats->gprc -= missed_rx;
7168
7169 ixgbe_update_xoff_received(adapter);
7170
7171 /* 82598 hardware only has a 32 bit counter in the high register */
7172 switch (hw->mac.type) {
7173 case ixgbe_mac_82598EB:
7174 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
7175 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
7176 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
7177 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
7178 break;
7179 case ixgbe_mac_X540:
7180 case ixgbe_mac_X550:
7181 case ixgbe_mac_X550EM_x:
7182 case ixgbe_mac_x550em_a:
7183 /* OS2BMC stats are X540 and later */
7184 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
7185 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
7186 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
7187 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
7188 fallthrough;
7189 case ixgbe_mac_82599EB:
7190 for (i = 0; i < 16; i++)
7191 adapter->hw_rx_no_dma_resources +=
7192 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7193 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
7194 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7195 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
7196 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7197 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
7198 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7199 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7200 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
7201 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
7202 #ifdef IXGBE_FCOE
7203 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
7204 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
7205 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
7206 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
7207 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
7208 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7209 /* Add up per cpu counters for total ddp aloc fail */
7210 if (adapter->fcoe.ddp_pool) {
7211 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
7212 struct ixgbe_fcoe_ddp_pool *ddp_pool;
7213 unsigned int cpu;
7214 u64 noddp = 0, noddp_ext_buff = 0;
7215 for_each_possible_cpu(cpu) {
7216 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
7217 noddp += ddp_pool->noddp;
7218 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7219 }
7220 hwstats->fcoe_noddp = noddp;
7221 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7222 }
7223 #endif /* IXGBE_FCOE */
7224 break;
7225 default:
7226 break;
7227 }
7228 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7229 hwstats->bprc += bprc;
7230 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
7231 if (hw->mac.type == ixgbe_mac_82598EB)
7232 hwstats->mprc -= bprc;
7233 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
7234 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
7235 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
7236 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
7237 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
7238 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
7239 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
7240 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
7241 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7242 hwstats->lxontxc += lxon;
7243 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7244 hwstats->lxofftxc += lxoff;
7245 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
7246 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
7247 /*
7248 * 82598 errata - tx of flow control packets is included in tx counters
7249 */
7250 xon_off_tot = lxon + lxoff;
7251 hwstats->gptc -= xon_off_tot;
7252 hwstats->mptc -= xon_off_tot;
7253 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
7254 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
7255 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
7256 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
7257 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
7258 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
7259 hwstats->ptc64 -= xon_off_tot;
7260 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
7261 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
7262 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
7263 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
7264 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
7265 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
7266
7267 /* Fill out the OS statistics structure */
7268 netdev->stats.multicast = hwstats->mprc;
7269
7270 /* Rx Errors */
7271 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
7272 netdev->stats.rx_dropped = 0;
7273 netdev->stats.rx_length_errors = hwstats->rlec;
7274 netdev->stats.rx_crc_errors = hwstats->crcerrs;
7275 netdev->stats.rx_missed_errors = total_mpc;
7276 }
7277
7278 /**
7279 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
7280 * @adapter: pointer to the device adapter structure
7281 **/
ixgbe_fdir_reinit_subtask(struct ixgbe_adapter * adapter)7282 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
7283 {
7284 struct ixgbe_hw *hw = &adapter->hw;
7285 int i;
7286
7287 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
7288 return;
7289
7290 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7291
7292 /* if interface is down do nothing */
7293 if (test_bit(__IXGBE_DOWN, &adapter->state))
7294 return;
7295
7296 /* do nothing if we are not using signature filters */
7297 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
7298 return;
7299
7300 adapter->fdir_overflow++;
7301
7302 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
7303 for (i = 0; i < adapter->num_tx_queues; i++)
7304 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7305 &(adapter->tx_ring[i]->state));
7306 for (i = 0; i < adapter->num_xdp_queues; i++)
7307 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7308 &adapter->xdp_ring[i]->state);
7309 /* re-enable flow director interrupts */
7310 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
7311 } else {
7312 e_err(probe, "failed to finish FDIR re-initialization, "
7313 "ignored adding FDIR ATR filters\n");
7314 }
7315 }
7316
7317 /**
7318 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
7319 * @adapter: pointer to the device adapter structure
7320 *
7321 * This function serves two purposes. First it strobes the interrupt lines
7322 * in order to make certain interrupts are occurring. Secondly it sets the
7323 * bits needed to check for TX hangs. As a result we should immediately
7324 * determine if a hang has occurred.
7325 */
ixgbe_check_hang_subtask(struct ixgbe_adapter * adapter)7326 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
7327 {
7328 struct ixgbe_hw *hw = &adapter->hw;
7329 u64 eics = 0;
7330 int i;
7331
7332 /* If we're down, removing or resetting, just bail */
7333 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7334 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7335 test_bit(__IXGBE_RESETTING, &adapter->state))
7336 return;
7337
7338 /* Force detection of hung controller */
7339 if (netif_carrier_ok(adapter->netdev)) {
7340 for (i = 0; i < adapter->num_tx_queues; i++)
7341 set_check_for_tx_hang(adapter->tx_ring[i]);
7342 for (i = 0; i < adapter->num_xdp_queues; i++)
7343 set_check_for_tx_hang(adapter->xdp_ring[i]);
7344 }
7345
7346 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7347 /*
7348 * for legacy and MSI interrupts don't set any bits
7349 * that are enabled for EIAM, because this operation
7350 * would set *both* EIMS and EICS for any bit in EIAM
7351 */
7352 IXGBE_WRITE_REG(hw, IXGBE_EICS,
7353 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
7354 } else {
7355 /* get one bit for every active tx/rx interrupt vector */
7356 for (i = 0; i < adapter->num_q_vectors; i++) {
7357 struct ixgbe_q_vector *qv = adapter->q_vector[i];
7358 if (qv->rx.ring || qv->tx.ring)
7359 eics |= BIT_ULL(i);
7360 }
7361 }
7362
7363 /* Cause software interrupt to ensure rings are cleaned */
7364 ixgbe_irq_rearm_queues(adapter, eics);
7365 }
7366
7367 /**
7368 * ixgbe_watchdog_update_link - update the link status
7369 * @adapter: pointer to the device adapter structure
7370 **/
ixgbe_watchdog_update_link(struct ixgbe_adapter * adapter)7371 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
7372 {
7373 struct ixgbe_hw *hw = &adapter->hw;
7374 u32 link_speed = adapter->link_speed;
7375 bool link_up = adapter->link_up;
7376 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
7377
7378 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
7379 return;
7380
7381 if (hw->mac.ops.check_link) {
7382 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
7383 } else {
7384 /* always assume link is up, if no check link function */
7385 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
7386 link_up = true;
7387 }
7388
7389 if (adapter->ixgbe_ieee_pfc)
7390 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
7391
7392 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
7393 hw->mac.ops.fc_enable(hw);
7394 ixgbe_set_rx_drop_en(adapter);
7395 }
7396
7397 if (link_up ||
7398 time_after(jiffies, (adapter->link_check_timeout +
7399 IXGBE_TRY_LINK_TIMEOUT))) {
7400 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
7401 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
7402 IXGBE_WRITE_FLUSH(hw);
7403 }
7404
7405 adapter->link_up = link_up;
7406 adapter->link_speed = link_speed;
7407 }
7408
ixgbe_update_default_up(struct ixgbe_adapter * adapter)7409 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
7410 {
7411 #ifdef CONFIG_IXGBE_DCB
7412 struct net_device *netdev = adapter->netdev;
7413 struct dcb_app app = {
7414 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
7415 .protocol = 0,
7416 };
7417 u8 up = 0;
7418
7419 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
7420 up = dcb_ieee_getapp_mask(netdev, &app);
7421
7422 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
7423 #endif
7424 }
7425
7426 /**
7427 * ixgbe_watchdog_link_is_up - update netif_carrier status and
7428 * print link up message
7429 * @adapter: pointer to the device adapter structure
7430 **/
ixgbe_watchdog_link_is_up(struct ixgbe_adapter * adapter)7431 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
7432 {
7433 struct net_device *netdev = adapter->netdev;
7434 struct ixgbe_hw *hw = &adapter->hw;
7435 u32 link_speed = adapter->link_speed;
7436 const char *speed_str;
7437 bool flow_rx, flow_tx;
7438
7439 /* only continue if link was previously down */
7440 if (netif_carrier_ok(netdev))
7441 return;
7442
7443 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7444
7445 switch (hw->mac.type) {
7446 case ixgbe_mac_82598EB: {
7447 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
7448 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
7449 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
7450 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
7451 }
7452 break;
7453 case ixgbe_mac_X540:
7454 case ixgbe_mac_X550:
7455 case ixgbe_mac_X550EM_x:
7456 case ixgbe_mac_x550em_a:
7457 case ixgbe_mac_82599EB: {
7458 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
7459 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
7460 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
7461 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
7462 }
7463 break;
7464 default:
7465 flow_tx = false;
7466 flow_rx = false;
7467 break;
7468 }
7469
7470 adapter->last_rx_ptp_check = jiffies;
7471
7472 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7473 ixgbe_ptp_start_cyclecounter(adapter);
7474
7475 switch (link_speed) {
7476 case IXGBE_LINK_SPEED_10GB_FULL:
7477 speed_str = "10 Gbps";
7478 break;
7479 case IXGBE_LINK_SPEED_5GB_FULL:
7480 speed_str = "5 Gbps";
7481 break;
7482 case IXGBE_LINK_SPEED_2_5GB_FULL:
7483 speed_str = "2.5 Gbps";
7484 break;
7485 case IXGBE_LINK_SPEED_1GB_FULL:
7486 speed_str = "1 Gbps";
7487 break;
7488 case IXGBE_LINK_SPEED_100_FULL:
7489 speed_str = "100 Mbps";
7490 break;
7491 case IXGBE_LINK_SPEED_10_FULL:
7492 speed_str = "10 Mbps";
7493 break;
7494 default:
7495 speed_str = "unknown speed";
7496 break;
7497 }
7498 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
7499 ((flow_rx && flow_tx) ? "RX/TX" :
7500 (flow_rx ? "RX" :
7501 (flow_tx ? "TX" : "None"))));
7502
7503 netif_carrier_on(netdev);
7504 ixgbe_check_vf_rate_limit(adapter);
7505
7506 /* enable transmits */
7507 netif_tx_wake_all_queues(adapter->netdev);
7508
7509 /* update the default user priority for VFs */
7510 ixgbe_update_default_up(adapter);
7511
7512 /* ping all the active vfs to let them know link has changed */
7513 ixgbe_ping_all_vfs(adapter);
7514 }
7515
7516 /**
7517 * ixgbe_watchdog_link_is_down - update netif_carrier status and
7518 * print link down message
7519 * @adapter: pointer to the adapter structure
7520 **/
ixgbe_watchdog_link_is_down(struct ixgbe_adapter * adapter)7521 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
7522 {
7523 struct net_device *netdev = adapter->netdev;
7524 struct ixgbe_hw *hw = &adapter->hw;
7525
7526 adapter->link_up = false;
7527 adapter->link_speed = 0;
7528
7529 /* only continue if link was up previously */
7530 if (!netif_carrier_ok(netdev))
7531 return;
7532
7533 /* poll for SFP+ cable when link is down */
7534 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
7535 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
7536
7537 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7538 ixgbe_ptp_start_cyclecounter(adapter);
7539
7540 e_info(drv, "NIC Link is Down\n");
7541 netif_carrier_off(netdev);
7542
7543 /* ping all the active vfs to let them know link has changed */
7544 ixgbe_ping_all_vfs(adapter);
7545 }
7546
ixgbe_ring_tx_pending(struct ixgbe_adapter * adapter)7547 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
7548 {
7549 int i;
7550
7551 for (i = 0; i < adapter->num_tx_queues; i++) {
7552 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
7553
7554 if (tx_ring->next_to_use != tx_ring->next_to_clean)
7555 return true;
7556 }
7557
7558 for (i = 0; i < adapter->num_xdp_queues; i++) {
7559 struct ixgbe_ring *ring = adapter->xdp_ring[i];
7560
7561 if (ring->next_to_use != ring->next_to_clean)
7562 return true;
7563 }
7564
7565 return false;
7566 }
7567
ixgbe_vf_tx_pending(struct ixgbe_adapter * adapter)7568 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
7569 {
7570 struct ixgbe_hw *hw = &adapter->hw;
7571 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
7572 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
7573
7574 int i, j;
7575
7576 if (!adapter->num_vfs)
7577 return false;
7578
7579 /* resetting the PF is only needed for MAC before X550 */
7580 if (hw->mac.type >= ixgbe_mac_X550)
7581 return false;
7582
7583 for (i = 0; i < adapter->num_vfs; i++) {
7584 for (j = 0; j < q_per_pool; j++) {
7585 u32 h, t;
7586
7587 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
7588 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
7589
7590 if (h != t)
7591 return true;
7592 }
7593 }
7594
7595 return false;
7596 }
7597
7598 /**
7599 * ixgbe_watchdog_flush_tx - flush queues on link down
7600 * @adapter: pointer to the device adapter structure
7601 **/
ixgbe_watchdog_flush_tx(struct ixgbe_adapter * adapter)7602 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
7603 {
7604 if (!netif_carrier_ok(adapter->netdev)) {
7605 if (ixgbe_ring_tx_pending(adapter) ||
7606 ixgbe_vf_tx_pending(adapter)) {
7607 /* We've lost link, so the controller stops DMA,
7608 * but we've got queued Tx work that's never going
7609 * to get done, so reset controller to flush Tx.
7610 * (Do the reset outside of interrupt context).
7611 */
7612 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
7613 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
7614 }
7615 }
7616 }
7617
7618 #ifdef CONFIG_PCI_IOV
ixgbe_bad_vf_abort(struct ixgbe_adapter * adapter,u32 vf)7619 static void ixgbe_bad_vf_abort(struct ixgbe_adapter *adapter, u32 vf)
7620 {
7621 struct ixgbe_hw *hw = &adapter->hw;
7622
7623 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
7624 adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF) {
7625 adapter->vfinfo[vf].primary_abort_count++;
7626 if (adapter->vfinfo[vf].primary_abort_count ==
7627 IXGBE_PRIMARY_ABORT_LIMIT) {
7628 ixgbe_set_vf_link_state(adapter, vf,
7629 IFLA_VF_LINK_STATE_DISABLE);
7630 adapter->vfinfo[vf].primary_abort_count = 0;
7631
7632 e_info(drv,
7633 "Malicious Driver Detection event detected on PF %d VF %d MAC: %pM mdd-disable-vf=on",
7634 hw->bus.func, vf,
7635 adapter->vfinfo[vf].vf_mac_addresses);
7636 }
7637 }
7638 }
7639
ixgbe_check_for_bad_vf(struct ixgbe_adapter * adapter)7640 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
7641 {
7642 struct ixgbe_hw *hw = &adapter->hw;
7643 struct pci_dev *pdev = adapter->pdev;
7644 unsigned int vf;
7645 u32 gpc;
7646
7647 if (!(netif_carrier_ok(adapter->netdev)))
7648 return;
7649
7650 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
7651 if (gpc) /* If incrementing then no need for the check below */
7652 return;
7653 /* Check to see if a bad DMA write target from an errant or
7654 * malicious VF has caused a PCIe error. If so then we can
7655 * issue a VFLR to the offending VF(s) and then resume without
7656 * requesting a full slot reset.
7657 */
7658
7659 if (!pdev)
7660 return;
7661
7662 /* check status reg for all VFs owned by this PF */
7663 for (vf = 0; vf < adapter->num_vfs; ++vf) {
7664 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
7665 u16 status_reg;
7666
7667 if (!vfdev)
7668 continue;
7669 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
7670 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
7671 status_reg & PCI_STATUS_REC_MASTER_ABORT) {
7672 ixgbe_bad_vf_abort(adapter, vf);
7673 pcie_flr(vfdev);
7674 }
7675 }
7676 }
7677
ixgbe_spoof_check(struct ixgbe_adapter * adapter)7678 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
7679 {
7680 u32 ssvpc;
7681
7682 /* Do not perform spoof check for 82598 or if not in IOV mode */
7683 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7684 adapter->num_vfs == 0)
7685 return;
7686
7687 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
7688
7689 /*
7690 * ssvpc register is cleared on read, if zero then no
7691 * spoofed packets in the last interval.
7692 */
7693 if (!ssvpc)
7694 return;
7695
7696 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
7697 }
7698 #else
ixgbe_spoof_check(struct ixgbe_adapter __always_unused * adapter)7699 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7700 {
7701 }
7702
7703 static void
ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused * adapter)7704 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7705 {
7706 }
7707 #endif /* CONFIG_PCI_IOV */
7708
7709
7710 /**
7711 * ixgbe_watchdog_subtask - check and bring link up
7712 * @adapter: pointer to the device adapter structure
7713 **/
ixgbe_watchdog_subtask(struct ixgbe_adapter * adapter)7714 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7715 {
7716 /* if interface is down, removing or resetting, do nothing */
7717 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7718 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7719 test_bit(__IXGBE_RESETTING, &adapter->state))
7720 return;
7721
7722 ixgbe_watchdog_update_link(adapter);
7723
7724 if (adapter->link_up)
7725 ixgbe_watchdog_link_is_up(adapter);
7726 else
7727 ixgbe_watchdog_link_is_down(adapter);
7728
7729 ixgbe_check_for_bad_vf(adapter);
7730 ixgbe_spoof_check(adapter);
7731 ixgbe_update_stats(adapter);
7732
7733 ixgbe_watchdog_flush_tx(adapter);
7734 }
7735
7736 /**
7737 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
7738 * @adapter: the ixgbe adapter structure
7739 **/
ixgbe_sfp_detection_subtask(struct ixgbe_adapter * adapter)7740 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
7741 {
7742 struct ixgbe_hw *hw = &adapter->hw;
7743 s32 err;
7744
7745 /* not searching for SFP so there is nothing to do here */
7746 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7747 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7748 return;
7749
7750 if (adapter->sfp_poll_time &&
7751 time_after(adapter->sfp_poll_time, jiffies))
7752 return; /* If not yet time to poll for SFP */
7753
7754 /* someone else is in init, wait until next service event */
7755 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7756 return;
7757
7758 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7759
7760 err = hw->phy.ops.identify_sfp(hw);
7761 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7762 goto sfp_out;
7763
7764 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7765 /* If no cable is present, then we need to reset
7766 * the next time we find a good cable. */
7767 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
7768 }
7769
7770 /* exit on error */
7771 if (err)
7772 goto sfp_out;
7773
7774 /* exit if reset not needed */
7775 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7776 goto sfp_out;
7777
7778 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
7779
7780 /*
7781 * A module may be identified correctly, but the EEPROM may not have
7782 * support for that module. setup_sfp() will fail in that case, so
7783 * we should not allow that module to load.
7784 */
7785 if (hw->mac.type == ixgbe_mac_82598EB)
7786 err = hw->phy.ops.reset(hw);
7787 else
7788 err = hw->mac.ops.setup_sfp(hw);
7789
7790 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7791 goto sfp_out;
7792
7793 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7794 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7795
7796 sfp_out:
7797 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7798
7799 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7800 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7801 e_dev_err("failed to initialize because an unsupported "
7802 "SFP+ module type was detected.\n");
7803 e_dev_err("Reload the driver after installing a "
7804 "supported module.\n");
7805 unregister_netdev(adapter->netdev);
7806 }
7807 }
7808
7809 /**
7810 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
7811 * @adapter: the ixgbe adapter structure
7812 **/
ixgbe_sfp_link_config_subtask(struct ixgbe_adapter * adapter)7813 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7814 {
7815 struct ixgbe_hw *hw = &adapter->hw;
7816 u32 cap_speed;
7817 u32 speed;
7818 bool autoneg = false;
7819
7820 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7821 return;
7822
7823 /* someone else is in init, wait until next service event */
7824 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7825 return;
7826
7827 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7828
7829 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg);
7830
7831 /* advertise highest capable link speed */
7832 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL))
7833 speed = IXGBE_LINK_SPEED_10GB_FULL;
7834 else
7835 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL |
7836 IXGBE_LINK_SPEED_1GB_FULL);
7837
7838 if (hw->mac.ops.setup_link)
7839 hw->mac.ops.setup_link(hw, speed, true);
7840
7841 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7842 adapter->link_check_timeout = jiffies;
7843 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7844 }
7845
7846 /**
7847 * ixgbe_service_timer - Timer Call-back
7848 * @t: pointer to timer_list structure
7849 **/
ixgbe_service_timer(struct timer_list * t)7850 static void ixgbe_service_timer(struct timer_list *t)
7851 {
7852 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer);
7853 unsigned long next_event_offset;
7854
7855 /* poll faster when waiting for link */
7856 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7857 next_event_offset = HZ / 10;
7858 else
7859 next_event_offset = HZ * 2;
7860
7861 /* Reset the timer */
7862 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7863
7864 ixgbe_service_event_schedule(adapter);
7865 }
7866
ixgbe_phy_interrupt_subtask(struct ixgbe_adapter * adapter)7867 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7868 {
7869 struct ixgbe_hw *hw = &adapter->hw;
7870 u32 status;
7871
7872 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7873 return;
7874
7875 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7876
7877 if (!hw->phy.ops.handle_lasi)
7878 return;
7879
7880 status = hw->phy.ops.handle_lasi(&adapter->hw);
7881 if (status != IXGBE_ERR_OVERTEMP)
7882 return;
7883
7884 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7885 }
7886
ixgbe_reset_subtask(struct ixgbe_adapter * adapter)7887 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7888 {
7889 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
7890 return;
7891
7892 rtnl_lock();
7893 /* If we're already down, removing or resetting, just bail */
7894 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7895 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7896 test_bit(__IXGBE_RESETTING, &adapter->state)) {
7897 rtnl_unlock();
7898 return;
7899 }
7900
7901 ixgbe_dump(adapter);
7902 netdev_err(adapter->netdev, "Reset adapter\n");
7903 adapter->tx_timeout_count++;
7904
7905 ixgbe_reinit_locked(adapter);
7906 rtnl_unlock();
7907 }
7908
7909 /**
7910 * ixgbe_check_fw_error - Check firmware for errors
7911 * @adapter: the adapter private structure
7912 *
7913 * Check firmware errors in register FWSM
7914 */
ixgbe_check_fw_error(struct ixgbe_adapter * adapter)7915 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter)
7916 {
7917 struct ixgbe_hw *hw = &adapter->hw;
7918 u32 fwsm;
7919
7920 /* read fwsm.ext_err_ind register and log errors */
7921 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
7922
7923 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK ||
7924 !(fwsm & IXGBE_FWSM_FW_VAL_BIT))
7925 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n",
7926 fwsm);
7927
7928 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
7929 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n");
7930 return true;
7931 }
7932
7933 return false;
7934 }
7935
7936 /**
7937 * ixgbe_service_task - manages and runs subtasks
7938 * @work: pointer to work_struct containing our data
7939 **/
ixgbe_service_task(struct work_struct * work)7940 static void ixgbe_service_task(struct work_struct *work)
7941 {
7942 struct ixgbe_adapter *adapter = container_of(work,
7943 struct ixgbe_adapter,
7944 service_task);
7945 if (ixgbe_removed(adapter->hw.hw_addr)) {
7946 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7947 rtnl_lock();
7948 ixgbe_down(adapter);
7949 rtnl_unlock();
7950 }
7951 ixgbe_service_event_complete(adapter);
7952 return;
7953 }
7954 if (ixgbe_check_fw_error(adapter)) {
7955 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7956 unregister_netdev(adapter->netdev);
7957 ixgbe_service_event_complete(adapter);
7958 return;
7959 }
7960 ixgbe_reset_subtask(adapter);
7961 ixgbe_phy_interrupt_subtask(adapter);
7962 ixgbe_sfp_detection_subtask(adapter);
7963 ixgbe_sfp_link_config_subtask(adapter);
7964 ixgbe_check_overtemp_subtask(adapter);
7965 ixgbe_watchdog_subtask(adapter);
7966 ixgbe_fdir_reinit_subtask(adapter);
7967 ixgbe_check_hang_subtask(adapter);
7968
7969 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
7970 ixgbe_ptp_overflow_check(adapter);
7971 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER)
7972 ixgbe_ptp_rx_hang(adapter);
7973 ixgbe_ptp_tx_hang(adapter);
7974 }
7975
7976 ixgbe_service_event_complete(adapter);
7977 }
7978
ixgbe_tso(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,u8 * hdr_len,struct ixgbe_ipsec_tx_data * itd)7979 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7980 struct ixgbe_tx_buffer *first,
7981 u8 *hdr_len,
7982 struct ixgbe_ipsec_tx_data *itd)
7983 {
7984 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
7985 struct sk_buff *skb = first->skb;
7986 union {
7987 struct iphdr *v4;
7988 struct ipv6hdr *v6;
7989 unsigned char *hdr;
7990 } ip;
7991 union {
7992 struct tcphdr *tcp;
7993 struct udphdr *udp;
7994 unsigned char *hdr;
7995 } l4;
7996 u32 paylen, l4_offset;
7997 u32 fceof_saidx = 0;
7998 int err;
7999
8000 if (skb->ip_summed != CHECKSUM_PARTIAL)
8001 return 0;
8002
8003 if (!skb_is_gso(skb))
8004 return 0;
8005
8006 err = skb_cow_head(skb, 0);
8007 if (err < 0)
8008 return err;
8009
8010 if (eth_p_mpls(first->protocol))
8011 ip.hdr = skb_inner_network_header(skb);
8012 else
8013 ip.hdr = skb_network_header(skb);
8014 l4.hdr = skb_checksum_start(skb);
8015
8016 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
8017 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
8018 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP;
8019
8020 /* initialize outer IP header fields */
8021 if (ip.v4->version == 4) {
8022 unsigned char *csum_start = skb_checksum_start(skb);
8023 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
8024 int len = csum_start - trans_start;
8025
8026 /* IP header will have to cancel out any data that
8027 * is not a part of the outer IP header, so set to
8028 * a reverse csum if needed, else init check to 0.
8029 */
8030 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ?
8031 csum_fold(csum_partial(trans_start,
8032 len, 0)) : 0;
8033 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
8034
8035 ip.v4->tot_len = 0;
8036 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
8037 IXGBE_TX_FLAGS_CSUM |
8038 IXGBE_TX_FLAGS_IPV4;
8039 } else {
8040 ip.v6->payload_len = 0;
8041 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
8042 IXGBE_TX_FLAGS_CSUM;
8043 }
8044
8045 /* determine offset of inner transport header */
8046 l4_offset = l4.hdr - skb->data;
8047
8048 /* remove payload length from inner checksum */
8049 paylen = skb->len - l4_offset;
8050
8051 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) {
8052 /* compute length of segmentation header */
8053 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
8054 csum_replace_by_diff(&l4.tcp->check,
8055 (__force __wsum)htonl(paylen));
8056 } else {
8057 /* compute length of segmentation header */
8058 *hdr_len = sizeof(*l4.udp) + l4_offset;
8059 csum_replace_by_diff(&l4.udp->check,
8060 (__force __wsum)htonl(paylen));
8061 }
8062
8063 /* update gso size and bytecount with header size */
8064 first->gso_segs = skb_shinfo(skb)->gso_segs;
8065 first->bytecount += (first->gso_segs - 1) * *hdr_len;
8066
8067 /* mss_l4len_id: use 0 as index for TSO */
8068 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
8069 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
8070
8071 fceof_saidx |= itd->sa_idx;
8072 type_tucmd |= itd->flags | itd->trailer_len;
8073
8074 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
8075 vlan_macip_lens = l4.hdr - ip.hdr;
8076 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
8077 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8078
8079 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd,
8080 mss_l4len_idx);
8081
8082 return 1;
8083 }
8084
ixgbe_ipv6_csum_is_sctp(struct sk_buff * skb)8085 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
8086 {
8087 unsigned int offset = 0;
8088
8089 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
8090
8091 return offset == skb_checksum_start_offset(skb);
8092 }
8093
ixgbe_tx_csum(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,struct ixgbe_ipsec_tx_data * itd)8094 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
8095 struct ixgbe_tx_buffer *first,
8096 struct ixgbe_ipsec_tx_data *itd)
8097 {
8098 struct sk_buff *skb = first->skb;
8099 u32 vlan_macip_lens = 0;
8100 u32 fceof_saidx = 0;
8101 u32 type_tucmd = 0;
8102
8103 if (skb->ip_summed != CHECKSUM_PARTIAL) {
8104 csum_failed:
8105 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
8106 IXGBE_TX_FLAGS_CC)))
8107 return;
8108 goto no_csum;
8109 }
8110
8111 switch (skb->csum_offset) {
8112 case offsetof(struct tcphdr, check):
8113 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
8114 fallthrough;
8115 case offsetof(struct udphdr, check):
8116 break;
8117 case offsetof(struct sctphdr, checksum):
8118 /* validate that this is actually an SCTP request */
8119 if (((first->protocol == htons(ETH_P_IP)) &&
8120 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
8121 ((first->protocol == htons(ETH_P_IPV6)) &&
8122 ixgbe_ipv6_csum_is_sctp(skb))) {
8123 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
8124 break;
8125 }
8126 fallthrough;
8127 default:
8128 skb_checksum_help(skb);
8129 goto csum_failed;
8130 }
8131
8132 /* update TX checksum flag */
8133 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
8134 vlan_macip_lens = skb_checksum_start_offset(skb) -
8135 skb_network_offset(skb);
8136 no_csum:
8137 /* vlan_macip_lens: MACLEN, VLAN tag */
8138 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
8139 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8140
8141 fceof_saidx |= itd->sa_idx;
8142 type_tucmd |= itd->flags | itd->trailer_len;
8143
8144 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0);
8145 }
8146
8147 #define IXGBE_SET_FLAG(_input, _flag, _result) \
8148 ((_flag <= _result) ? \
8149 ((u32)(_input & _flag) * (_result / _flag)) : \
8150 ((u32)(_input & _flag) / (_flag / _result)))
8151
ixgbe_tx_cmd_type(struct sk_buff * skb,u32 tx_flags)8152 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
8153 {
8154 /* set type for advanced descriptor with frame checksum insertion */
8155 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8156 IXGBE_ADVTXD_DCMD_DEXT |
8157 IXGBE_ADVTXD_DCMD_IFCS;
8158
8159 /* set HW vlan bit if vlan is present */
8160 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
8161 IXGBE_ADVTXD_DCMD_VLE);
8162
8163 /* set segmentation enable bits for TSO/FSO */
8164 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
8165 IXGBE_ADVTXD_DCMD_TSE);
8166
8167 /* set timestamp bit if present */
8168 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
8169 IXGBE_ADVTXD_MAC_TSTAMP);
8170
8171 /* insert frame checksum */
8172 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
8173
8174 return cmd_type;
8175 }
8176
ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc * tx_desc,u32 tx_flags,unsigned int paylen)8177 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
8178 u32 tx_flags, unsigned int paylen)
8179 {
8180 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
8181
8182 /* enable L4 checksum for TSO and TX checksum offload */
8183 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8184 IXGBE_TX_FLAGS_CSUM,
8185 IXGBE_ADVTXD_POPTS_TXSM);
8186
8187 /* enable IPv4 checksum for TSO */
8188 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8189 IXGBE_TX_FLAGS_IPV4,
8190 IXGBE_ADVTXD_POPTS_IXSM);
8191
8192 /* enable IPsec */
8193 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8194 IXGBE_TX_FLAGS_IPSEC,
8195 IXGBE_ADVTXD_POPTS_IPSEC);
8196
8197 /*
8198 * Check Context must be set if Tx switch is enabled, which it
8199 * always is for case where virtual functions are running
8200 */
8201 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8202 IXGBE_TX_FLAGS_CC,
8203 IXGBE_ADVTXD_CC);
8204
8205 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
8206 }
8207
__ixgbe_maybe_stop_tx(struct ixgbe_ring * tx_ring,u16 size)8208 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8209 {
8210 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
8211
8212 /* Herbert's original patch had:
8213 * smp_mb__after_netif_stop_queue();
8214 * but since that doesn't exist yet, just open code it.
8215 */
8216 smp_mb();
8217
8218 /* We need to check again in a case another CPU has just
8219 * made room available.
8220 */
8221 if (likely(ixgbe_desc_unused(tx_ring) < size))
8222 return -EBUSY;
8223
8224 /* A reprieve! - use start_queue because it doesn't call schedule */
8225 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
8226 ++tx_ring->tx_stats.restart_queue;
8227 return 0;
8228 }
8229
ixgbe_maybe_stop_tx(struct ixgbe_ring * tx_ring,u16 size)8230 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8231 {
8232 if (likely(ixgbe_desc_unused(tx_ring) >= size))
8233 return 0;
8234
8235 return __ixgbe_maybe_stop_tx(tx_ring, size);
8236 }
8237
ixgbe_tx_map(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,const u8 hdr_len)8238 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring,
8239 struct ixgbe_tx_buffer *first,
8240 const u8 hdr_len)
8241 {
8242 struct sk_buff *skb = first->skb;
8243 struct ixgbe_tx_buffer *tx_buffer;
8244 union ixgbe_adv_tx_desc *tx_desc;
8245 skb_frag_t *frag;
8246 dma_addr_t dma;
8247 unsigned int data_len, size;
8248 u32 tx_flags = first->tx_flags;
8249 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
8250 u16 i = tx_ring->next_to_use;
8251
8252 tx_desc = IXGBE_TX_DESC(tx_ring, i);
8253
8254 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
8255
8256 size = skb_headlen(skb);
8257 data_len = skb->data_len;
8258
8259 #ifdef IXGBE_FCOE
8260 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
8261 if (data_len < sizeof(struct fcoe_crc_eof)) {
8262 size -= sizeof(struct fcoe_crc_eof) - data_len;
8263 data_len = 0;
8264 } else {
8265 data_len -= sizeof(struct fcoe_crc_eof);
8266 }
8267 }
8268
8269 #endif
8270 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8271
8272 tx_buffer = first;
8273
8274 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
8275 if (dma_mapping_error(tx_ring->dev, dma))
8276 goto dma_error;
8277
8278 /* record length, and DMA address */
8279 dma_unmap_len_set(tx_buffer, len, size);
8280 dma_unmap_addr_set(tx_buffer, dma, dma);
8281
8282 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8283
8284 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
8285 tx_desc->read.cmd_type_len =
8286 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
8287
8288 i++;
8289 tx_desc++;
8290 if (i == tx_ring->count) {
8291 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8292 i = 0;
8293 }
8294 tx_desc->read.olinfo_status = 0;
8295
8296 dma += IXGBE_MAX_DATA_PER_TXD;
8297 size -= IXGBE_MAX_DATA_PER_TXD;
8298
8299 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8300 }
8301
8302 if (likely(!data_len))
8303 break;
8304
8305 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
8306
8307 i++;
8308 tx_desc++;
8309 if (i == tx_ring->count) {
8310 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8311 i = 0;
8312 }
8313 tx_desc->read.olinfo_status = 0;
8314
8315 #ifdef IXGBE_FCOE
8316 size = min_t(unsigned int, data_len, skb_frag_size(frag));
8317 #else
8318 size = skb_frag_size(frag);
8319 #endif
8320 data_len -= size;
8321
8322 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
8323 DMA_TO_DEVICE);
8324
8325 tx_buffer = &tx_ring->tx_buffer_info[i];
8326 }
8327
8328 /* write last descriptor with RS and EOP bits */
8329 cmd_type |= size | IXGBE_TXD_CMD;
8330 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8331
8332 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
8333
8334 /* set the timestamp */
8335 first->time_stamp = jiffies;
8336
8337 skb_tx_timestamp(skb);
8338
8339 /*
8340 * Force memory writes to complete before letting h/w know there
8341 * are new descriptors to fetch. (Only applicable for weak-ordered
8342 * memory model archs, such as IA-64).
8343 *
8344 * We also need this memory barrier to make certain all of the
8345 * status bits have been updated before next_to_watch is written.
8346 */
8347 wmb();
8348
8349 /* set next_to_watch value indicating a packet is present */
8350 first->next_to_watch = tx_desc;
8351
8352 i++;
8353 if (i == tx_ring->count)
8354 i = 0;
8355
8356 tx_ring->next_to_use = i;
8357
8358 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
8359
8360 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
8361 writel(i, tx_ring->tail);
8362 }
8363
8364 return 0;
8365 dma_error:
8366 dev_err(tx_ring->dev, "TX DMA map failed\n");
8367
8368 /* clear dma mappings for failed tx_buffer_info map */
8369 for (;;) {
8370 tx_buffer = &tx_ring->tx_buffer_info[i];
8371 if (dma_unmap_len(tx_buffer, len))
8372 dma_unmap_page(tx_ring->dev,
8373 dma_unmap_addr(tx_buffer, dma),
8374 dma_unmap_len(tx_buffer, len),
8375 DMA_TO_DEVICE);
8376 dma_unmap_len_set(tx_buffer, len, 0);
8377 if (tx_buffer == first)
8378 break;
8379 if (i == 0)
8380 i += tx_ring->count;
8381 i--;
8382 }
8383
8384 dev_kfree_skb_any(first->skb);
8385 first->skb = NULL;
8386
8387 tx_ring->next_to_use = i;
8388
8389 return -1;
8390 }
8391
ixgbe_atr(struct ixgbe_ring * ring,struct ixgbe_tx_buffer * first)8392 static void ixgbe_atr(struct ixgbe_ring *ring,
8393 struct ixgbe_tx_buffer *first)
8394 {
8395 struct ixgbe_q_vector *q_vector = ring->q_vector;
8396 union ixgbe_atr_hash_dword input = { .dword = 0 };
8397 union ixgbe_atr_hash_dword common = { .dword = 0 };
8398 union {
8399 unsigned char *network;
8400 struct iphdr *ipv4;
8401 struct ipv6hdr *ipv6;
8402 } hdr;
8403 struct tcphdr *th;
8404 unsigned int hlen;
8405 struct sk_buff *skb;
8406 __be16 vlan_id;
8407 int l4_proto;
8408
8409 /* if ring doesn't have a interrupt vector, cannot perform ATR */
8410 if (!q_vector)
8411 return;
8412
8413 /* do nothing if sampling is disabled */
8414 if (!ring->atr_sample_rate)
8415 return;
8416
8417 ring->atr_count++;
8418
8419 /* currently only IPv4/IPv6 with TCP is supported */
8420 if ((first->protocol != htons(ETH_P_IP)) &&
8421 (first->protocol != htons(ETH_P_IPV6)))
8422 return;
8423
8424 /* snag network header to get L4 type and address */
8425 skb = first->skb;
8426 hdr.network = skb_network_header(skb);
8427 if (unlikely(hdr.network <= skb->data))
8428 return;
8429 if (skb->encapsulation &&
8430 first->protocol == htons(ETH_P_IP) &&
8431 hdr.ipv4->protocol == IPPROTO_UDP) {
8432 struct ixgbe_adapter *adapter = q_vector->adapter;
8433
8434 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8435 VXLAN_HEADROOM))
8436 return;
8437
8438 /* verify the port is recognized as VXLAN */
8439 if (adapter->vxlan_port &&
8440 udp_hdr(skb)->dest == adapter->vxlan_port)
8441 hdr.network = skb_inner_network_header(skb);
8442
8443 if (adapter->geneve_port &&
8444 udp_hdr(skb)->dest == adapter->geneve_port)
8445 hdr.network = skb_inner_network_header(skb);
8446 }
8447
8448 /* Make sure we have at least [minimum IPv4 header + TCP]
8449 * or [IPv6 header] bytes
8450 */
8451 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40))
8452 return;
8453
8454 /* Currently only IPv4/IPv6 with TCP is supported */
8455 switch (hdr.ipv4->version) {
8456 case IPVERSION:
8457 /* access ihl as u8 to avoid unaligned access on ia64 */
8458 hlen = (hdr.network[0] & 0x0F) << 2;
8459 l4_proto = hdr.ipv4->protocol;
8460 break;
8461 case 6:
8462 hlen = hdr.network - skb->data;
8463 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
8464 hlen -= hdr.network - skb->data;
8465 break;
8466 default:
8467 return;
8468 }
8469
8470 if (l4_proto != IPPROTO_TCP)
8471 return;
8472
8473 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8474 hlen + sizeof(struct tcphdr)))
8475 return;
8476
8477 th = (struct tcphdr *)(hdr.network + hlen);
8478
8479 /* skip this packet since the socket is closing */
8480 if (th->fin)
8481 return;
8482
8483 /* sample on all syn packets or once every atr sample count */
8484 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
8485 return;
8486
8487 /* reset sample count */
8488 ring->atr_count = 0;
8489
8490 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
8491
8492 /*
8493 * src and dst are inverted, think how the receiver sees them
8494 *
8495 * The input is broken into two sections, a non-compressed section
8496 * containing vm_pool, vlan_id, and flow_type. The rest of the data
8497 * is XORed together and stored in the compressed dword.
8498 */
8499 input.formatted.vlan_id = vlan_id;
8500
8501 /*
8502 * since src port and flex bytes occupy the same word XOR them together
8503 * and write the value to source port portion of compressed dword
8504 */
8505 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
8506 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
8507 else
8508 common.port.src ^= th->dest ^ first->protocol;
8509 common.port.dst ^= th->source;
8510
8511 switch (hdr.ipv4->version) {
8512 case IPVERSION:
8513 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
8514 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
8515 break;
8516 case 6:
8517 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
8518 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
8519 hdr.ipv6->saddr.s6_addr32[1] ^
8520 hdr.ipv6->saddr.s6_addr32[2] ^
8521 hdr.ipv6->saddr.s6_addr32[3] ^
8522 hdr.ipv6->daddr.s6_addr32[0] ^
8523 hdr.ipv6->daddr.s6_addr32[1] ^
8524 hdr.ipv6->daddr.s6_addr32[2] ^
8525 hdr.ipv6->daddr.s6_addr32[3];
8526 break;
8527 default:
8528 break;
8529 }
8530
8531 if (hdr.network != skb_network_header(skb))
8532 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
8533
8534 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
8535 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
8536 input, common, ring->queue_index);
8537 }
8538
8539 #ifdef IXGBE_FCOE
ixgbe_select_queue(struct net_device * dev,struct sk_buff * skb,struct net_device * sb_dev)8540 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
8541 struct net_device *sb_dev)
8542 {
8543 struct ixgbe_adapter *adapter;
8544 struct ixgbe_ring_feature *f;
8545 int txq;
8546
8547 if (sb_dev) {
8548 u8 tc = netdev_get_prio_tc_map(dev, skb->priority);
8549 struct net_device *vdev = sb_dev;
8550
8551 txq = vdev->tc_to_txq[tc].offset;
8552 txq += reciprocal_scale(skb_get_hash(skb),
8553 vdev->tc_to_txq[tc].count);
8554
8555 return txq;
8556 }
8557
8558 /*
8559 * only execute the code below if protocol is FCoE
8560 * or FIP and we have FCoE enabled on the adapter
8561 */
8562 switch (vlan_get_protocol(skb)) {
8563 case htons(ETH_P_FCOE):
8564 case htons(ETH_P_FIP):
8565 adapter = netdev_priv(dev);
8566
8567 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
8568 break;
8569 fallthrough;
8570 default:
8571 return netdev_pick_tx(dev, skb, sb_dev);
8572 }
8573
8574 f = &adapter->ring_feature[RING_F_FCOE];
8575
8576 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
8577 smp_processor_id();
8578
8579 while (txq >= f->indices)
8580 txq -= f->indices;
8581
8582 return txq + f->offset;
8583 }
8584
8585 #endif
ixgbe_xmit_xdp_ring(struct ixgbe_adapter * adapter,struct xdp_frame * xdpf)8586 int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
8587 struct xdp_frame *xdpf)
8588 {
8589 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
8590 struct ixgbe_tx_buffer *tx_buffer;
8591 union ixgbe_adv_tx_desc *tx_desc;
8592 u32 len, cmd_type;
8593 dma_addr_t dma;
8594 u16 i;
8595
8596 len = xdpf->len;
8597
8598 if (unlikely(!ixgbe_desc_unused(ring)))
8599 return IXGBE_XDP_CONSUMED;
8600
8601 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE);
8602 if (dma_mapping_error(ring->dev, dma))
8603 return IXGBE_XDP_CONSUMED;
8604
8605 /* record the location of the first descriptor for this packet */
8606 tx_buffer = &ring->tx_buffer_info[ring->next_to_use];
8607 tx_buffer->bytecount = len;
8608 tx_buffer->gso_segs = 1;
8609 tx_buffer->protocol = 0;
8610
8611 i = ring->next_to_use;
8612 tx_desc = IXGBE_TX_DESC(ring, i);
8613
8614 dma_unmap_len_set(tx_buffer, len, len);
8615 dma_unmap_addr_set(tx_buffer, dma, dma);
8616 tx_buffer->xdpf = xdpf;
8617
8618 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8619
8620 /* put descriptor type bits */
8621 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8622 IXGBE_ADVTXD_DCMD_DEXT |
8623 IXGBE_ADVTXD_DCMD_IFCS;
8624 cmd_type |= len | IXGBE_TXD_CMD;
8625 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8626 tx_desc->read.olinfo_status =
8627 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT);
8628
8629 /* Avoid any potential race with xdp_xmit and cleanup */
8630 smp_wmb();
8631
8632 /* set next_to_watch value indicating a packet is present */
8633 i++;
8634 if (i == ring->count)
8635 i = 0;
8636
8637 tx_buffer->next_to_watch = tx_desc;
8638 ring->next_to_use = i;
8639
8640 return IXGBE_XDP_TX;
8641 }
8642
ixgbe_xmit_frame_ring(struct sk_buff * skb,struct ixgbe_adapter * adapter,struct ixgbe_ring * tx_ring)8643 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
8644 struct ixgbe_adapter *adapter,
8645 struct ixgbe_ring *tx_ring)
8646 {
8647 struct ixgbe_tx_buffer *first;
8648 int tso;
8649 u32 tx_flags = 0;
8650 unsigned short f;
8651 u16 count = TXD_USE_COUNT(skb_headlen(skb));
8652 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 };
8653 __be16 protocol = skb->protocol;
8654 u8 hdr_len = 0;
8655
8656 /*
8657 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
8658 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
8659 * + 2 desc gap to keep tail from touching head,
8660 * + 1 desc for context descriptor,
8661 * otherwise try next time
8662 */
8663 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
8664 count += TXD_USE_COUNT(skb_frag_size(
8665 &skb_shinfo(skb)->frags[f]));
8666
8667 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
8668 tx_ring->tx_stats.tx_busy++;
8669 return NETDEV_TX_BUSY;
8670 }
8671
8672 /* record the location of the first descriptor for this packet */
8673 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
8674 first->skb = skb;
8675 first->bytecount = skb->len;
8676 first->gso_segs = 1;
8677
8678 /* if we have a HW VLAN tag being added default to the HW one */
8679 if (skb_vlan_tag_present(skb)) {
8680 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
8681 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8682 /* else if it is a SW VLAN check the next protocol and store the tag */
8683 } else if (protocol == htons(ETH_P_8021Q)) {
8684 struct vlan_hdr *vhdr, _vhdr;
8685 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
8686 if (!vhdr)
8687 goto out_drop;
8688
8689 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
8690 IXGBE_TX_FLAGS_VLAN_SHIFT;
8691 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
8692 }
8693 protocol = vlan_get_protocol(skb);
8694
8695 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
8696 adapter->ptp_clock) {
8697 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
8698 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
8699 &adapter->state)) {
8700 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8701 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
8702
8703 /* schedule check for Tx timestamp */
8704 adapter->ptp_tx_skb = skb_get(skb);
8705 adapter->ptp_tx_start = jiffies;
8706 schedule_work(&adapter->ptp_tx_work);
8707 } else {
8708 adapter->tx_hwtstamp_skipped++;
8709 }
8710 }
8711
8712 #ifdef CONFIG_PCI_IOV
8713 /*
8714 * Use the l2switch_enable flag - would be false if the DMA
8715 * Tx switch had been disabled.
8716 */
8717 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8718 tx_flags |= IXGBE_TX_FLAGS_CC;
8719
8720 #endif
8721 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
8722 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8723 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
8724 (skb->priority != TC_PRIO_CONTROL))) {
8725 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
8726 tx_flags |= (skb->priority & 0x7) <<
8727 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
8728 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
8729 struct vlan_ethhdr *vhdr;
8730
8731 if (skb_cow_head(skb, 0))
8732 goto out_drop;
8733 vhdr = (struct vlan_ethhdr *)skb->data;
8734 vhdr->h_vlan_TCI = htons(tx_flags >>
8735 IXGBE_TX_FLAGS_VLAN_SHIFT);
8736 } else {
8737 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8738 }
8739 }
8740
8741 /* record initial flags and protocol */
8742 first->tx_flags = tx_flags;
8743 first->protocol = protocol;
8744
8745 #ifdef IXGBE_FCOE
8746 /* setup tx offload for FCoE */
8747 if ((protocol == htons(ETH_P_FCOE)) &&
8748 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
8749 tso = ixgbe_fso(tx_ring, first, &hdr_len);
8750 if (tso < 0)
8751 goto out_drop;
8752
8753 goto xmit_fcoe;
8754 }
8755
8756 #endif /* IXGBE_FCOE */
8757
8758 #ifdef CONFIG_IXGBE_IPSEC
8759 if (xfrm_offload(skb) &&
8760 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx))
8761 goto out_drop;
8762 #endif
8763 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx);
8764 if (tso < 0)
8765 goto out_drop;
8766 else if (!tso)
8767 ixgbe_tx_csum(tx_ring, first, &ipsec_tx);
8768
8769 /* add the ATR filter if ATR is on */
8770 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
8771 ixgbe_atr(tx_ring, first);
8772
8773 #ifdef IXGBE_FCOE
8774 xmit_fcoe:
8775 #endif /* IXGBE_FCOE */
8776 if (ixgbe_tx_map(tx_ring, first, hdr_len))
8777 goto cleanup_tx_timestamp;
8778
8779 return NETDEV_TX_OK;
8780
8781 out_drop:
8782 dev_kfree_skb_any(first->skb);
8783 first->skb = NULL;
8784 cleanup_tx_timestamp:
8785 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) {
8786 dev_kfree_skb_any(adapter->ptp_tx_skb);
8787 adapter->ptp_tx_skb = NULL;
8788 cancel_work_sync(&adapter->ptp_tx_work);
8789 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
8790 }
8791
8792 return NETDEV_TX_OK;
8793 }
8794
__ixgbe_xmit_frame(struct sk_buff * skb,struct net_device * netdev,struct ixgbe_ring * ring)8795 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
8796 struct net_device *netdev,
8797 struct ixgbe_ring *ring)
8798 {
8799 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8800 struct ixgbe_ring *tx_ring;
8801
8802 /*
8803 * The minimum packet size for olinfo paylen is 17 so pad the skb
8804 * in order to meet this minimum size requirement.
8805 */
8806 if (skb_put_padto(skb, 17))
8807 return NETDEV_TX_OK;
8808
8809 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)];
8810 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state)))
8811 return NETDEV_TX_BUSY;
8812
8813 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
8814 }
8815
ixgbe_xmit_frame(struct sk_buff * skb,struct net_device * netdev)8816 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
8817 struct net_device *netdev)
8818 {
8819 return __ixgbe_xmit_frame(skb, netdev, NULL);
8820 }
8821
8822 /**
8823 * ixgbe_set_mac - Change the Ethernet Address of the NIC
8824 * @netdev: network interface device structure
8825 * @p: pointer to an address structure
8826 *
8827 * Returns 0 on success, negative on failure
8828 **/
ixgbe_set_mac(struct net_device * netdev,void * p)8829 static int ixgbe_set_mac(struct net_device *netdev, void *p)
8830 {
8831 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8832 struct ixgbe_hw *hw = &adapter->hw;
8833 struct sockaddr *addr = p;
8834
8835 if (!is_valid_ether_addr(addr->sa_data))
8836 return -EADDRNOTAVAIL;
8837
8838 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
8839 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
8840
8841 ixgbe_mac_set_default_filter(adapter);
8842
8843 return 0;
8844 }
8845
8846 static int
ixgbe_mdio_read(struct net_device * netdev,int prtad,int devad,u16 addr)8847 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
8848 {
8849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8850 struct ixgbe_hw *hw = &adapter->hw;
8851 u16 value;
8852 int rc;
8853
8854 if (adapter->mii_bus) {
8855 int regnum = addr;
8856
8857 if (devad != MDIO_DEVAD_NONE)
8858 regnum |= (devad << 16) | MII_ADDR_C45;
8859
8860 return mdiobus_read(adapter->mii_bus, prtad, regnum);
8861 }
8862
8863 if (prtad != hw->phy.mdio.prtad)
8864 return -EINVAL;
8865 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
8866 if (!rc)
8867 rc = value;
8868 return rc;
8869 }
8870
ixgbe_mdio_write(struct net_device * netdev,int prtad,int devad,u16 addr,u16 value)8871 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8872 u16 addr, u16 value)
8873 {
8874 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8875 struct ixgbe_hw *hw = &adapter->hw;
8876
8877 if (adapter->mii_bus) {
8878 int regnum = addr;
8879
8880 if (devad != MDIO_DEVAD_NONE)
8881 regnum |= (devad << 16) | MII_ADDR_C45;
8882
8883 return mdiobus_write(adapter->mii_bus, prtad, regnum, value);
8884 }
8885
8886 if (prtad != hw->phy.mdio.prtad)
8887 return -EINVAL;
8888 return hw->phy.ops.write_reg(hw, addr, devad, value);
8889 }
8890
ixgbe_ioctl(struct net_device * netdev,struct ifreq * req,int cmd)8891 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8892 {
8893 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8894
8895 switch (cmd) {
8896 case SIOCSHWTSTAMP:
8897 return ixgbe_ptp_set_ts_config(adapter, req);
8898 case SIOCGHWTSTAMP:
8899 return ixgbe_ptp_get_ts_config(adapter, req);
8900 case SIOCGMIIPHY:
8901 if (!adapter->hw.phy.ops.read_reg)
8902 return -EOPNOTSUPP;
8903 fallthrough;
8904 default:
8905 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8906 }
8907 }
8908
8909 /**
8910 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
8911 * netdev->dev_addrs
8912 * @dev: network interface device structure
8913 *
8914 * Returns non-zero on failure
8915 **/
ixgbe_add_sanmac_netdev(struct net_device * dev)8916 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8917 {
8918 int err = 0;
8919 struct ixgbe_adapter *adapter = netdev_priv(dev);
8920 struct ixgbe_hw *hw = &adapter->hw;
8921
8922 if (is_valid_ether_addr(hw->mac.san_addr)) {
8923 rtnl_lock();
8924 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
8925 rtnl_unlock();
8926
8927 /* update SAN MAC vmdq pool selection */
8928 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
8929 }
8930 return err;
8931 }
8932
8933 /**
8934 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
8935 * netdev->dev_addrs
8936 * @dev: network interface device structure
8937 *
8938 * Returns non-zero on failure
8939 **/
ixgbe_del_sanmac_netdev(struct net_device * dev)8940 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8941 {
8942 int err = 0;
8943 struct ixgbe_adapter *adapter = netdev_priv(dev);
8944 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8945
8946 if (is_valid_ether_addr(mac->san_addr)) {
8947 rtnl_lock();
8948 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8949 rtnl_unlock();
8950 }
8951 return err;
8952 }
8953
ixgbe_get_ring_stats64(struct rtnl_link_stats64 * stats,struct ixgbe_ring * ring)8954 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats,
8955 struct ixgbe_ring *ring)
8956 {
8957 u64 bytes, packets;
8958 unsigned int start;
8959
8960 if (ring) {
8961 do {
8962 start = u64_stats_fetch_begin_irq(&ring->syncp);
8963 packets = ring->stats.packets;
8964 bytes = ring->stats.bytes;
8965 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8966 stats->tx_packets += packets;
8967 stats->tx_bytes += bytes;
8968 }
8969 }
8970
ixgbe_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)8971 static void ixgbe_get_stats64(struct net_device *netdev,
8972 struct rtnl_link_stats64 *stats)
8973 {
8974 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8975 int i;
8976
8977 rcu_read_lock();
8978 for (i = 0; i < adapter->num_rx_queues; i++) {
8979 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]);
8980 u64 bytes, packets;
8981 unsigned int start;
8982
8983 if (ring) {
8984 do {
8985 start = u64_stats_fetch_begin_irq(&ring->syncp);
8986 packets = ring->stats.packets;
8987 bytes = ring->stats.bytes;
8988 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8989 stats->rx_packets += packets;
8990 stats->rx_bytes += bytes;
8991 }
8992 }
8993
8994 for (i = 0; i < adapter->num_tx_queues; i++) {
8995 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]);
8996
8997 ixgbe_get_ring_stats64(stats, ring);
8998 }
8999 for (i = 0; i < adapter->num_xdp_queues; i++) {
9000 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]);
9001
9002 ixgbe_get_ring_stats64(stats, ring);
9003 }
9004 rcu_read_unlock();
9005
9006 /* following stats updated by ixgbe_watchdog_task() */
9007 stats->multicast = netdev->stats.multicast;
9008 stats->rx_errors = netdev->stats.rx_errors;
9009 stats->rx_length_errors = netdev->stats.rx_length_errors;
9010 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
9011 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
9012 }
9013
9014 #ifdef CONFIG_IXGBE_DCB
9015 /**
9016 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
9017 * @adapter: pointer to ixgbe_adapter
9018 * @tc: number of traffic classes currently enabled
9019 *
9020 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
9021 * 802.1Q priority maps to a packet buffer that exists.
9022 */
ixgbe_validate_rtr(struct ixgbe_adapter * adapter,u8 tc)9023 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
9024 {
9025 struct ixgbe_hw *hw = &adapter->hw;
9026 u32 reg, rsave;
9027 int i;
9028
9029 /* 82598 have a static priority to TC mapping that can not
9030 * be changed so no validation is needed.
9031 */
9032 if (hw->mac.type == ixgbe_mac_82598EB)
9033 return;
9034
9035 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
9036 rsave = reg;
9037
9038 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
9039 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
9040
9041 /* If up2tc is out of bounds default to zero */
9042 if (up2tc > tc)
9043 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
9044 }
9045
9046 if (reg != rsave)
9047 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
9048
9049 return;
9050 }
9051
9052 /**
9053 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
9054 * @adapter: Pointer to adapter struct
9055 *
9056 * Populate the netdev user priority to tc map
9057 */
ixgbe_set_prio_tc_map(struct ixgbe_adapter * adapter)9058 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
9059 {
9060 struct net_device *dev = adapter->netdev;
9061 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
9062 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
9063 u8 prio;
9064
9065 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
9066 u8 tc = 0;
9067
9068 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
9069 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
9070 else if (ets)
9071 tc = ets->prio_tc[prio];
9072
9073 netdev_set_prio_tc_map(dev, prio, tc);
9074 }
9075 }
9076
9077 #endif /* CONFIG_IXGBE_DCB */
ixgbe_reassign_macvlan_pool(struct net_device * vdev,struct netdev_nested_priv * priv)9078 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev,
9079 struct netdev_nested_priv *priv)
9080 {
9081 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
9082 struct ixgbe_fwd_adapter *accel;
9083 int pool;
9084
9085 /* we only care about macvlans... */
9086 if (!netif_is_macvlan(vdev))
9087 return 0;
9088
9089 /* that have hardware offload enabled... */
9090 accel = macvlan_accel_priv(vdev);
9091 if (!accel)
9092 return 0;
9093
9094 /* If we can relocate to a different bit do so */
9095 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9096 if (pool < adapter->num_rx_pools) {
9097 set_bit(pool, adapter->fwd_bitmask);
9098 accel->pool = pool;
9099 return 0;
9100 }
9101
9102 /* if we cannot find a free pool then disable the offload */
9103 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n");
9104 macvlan_release_l2fw_offload(vdev);
9105
9106 /* unbind the queues and drop the subordinate channel config */
9107 netdev_unbind_sb_channel(adapter->netdev, vdev);
9108 netdev_set_sb_channel(vdev, 0);
9109
9110 kfree(accel);
9111
9112 return 0;
9113 }
9114
ixgbe_defrag_macvlan_pools(struct net_device * dev)9115 static void ixgbe_defrag_macvlan_pools(struct net_device *dev)
9116 {
9117 struct ixgbe_adapter *adapter = netdev_priv(dev);
9118 struct netdev_nested_priv priv = {
9119 .data = (void *)adapter,
9120 };
9121
9122 /* flush any stale bits out of the fwd bitmask */
9123 bitmap_clear(adapter->fwd_bitmask, 1, 63);
9124
9125 /* walk through upper devices reassigning pools */
9126 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool,
9127 &priv);
9128 }
9129
9130 /**
9131 * ixgbe_setup_tc - configure net_device for multiple traffic classes
9132 *
9133 * @dev: net device to configure
9134 * @tc: number of traffic classes to enable
9135 */
ixgbe_setup_tc(struct net_device * dev,u8 tc)9136 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
9137 {
9138 struct ixgbe_adapter *adapter = netdev_priv(dev);
9139 struct ixgbe_hw *hw = &adapter->hw;
9140
9141 /* Hardware supports up to 8 traffic classes */
9142 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
9143 return -EINVAL;
9144
9145 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
9146 return -EINVAL;
9147
9148 /* Hardware has to reinitialize queues and interrupts to
9149 * match packet buffer alignment. Unfortunately, the
9150 * hardware is not flexible enough to do this dynamically.
9151 */
9152 if (netif_running(dev))
9153 ixgbe_close(dev);
9154 else
9155 ixgbe_reset(adapter);
9156
9157 ixgbe_clear_interrupt_scheme(adapter);
9158
9159 #ifdef CONFIG_IXGBE_DCB
9160 if (tc) {
9161 if (adapter->xdp_prog) {
9162 e_warn(probe, "DCB is not supported with XDP\n");
9163
9164 ixgbe_init_interrupt_scheme(adapter);
9165 if (netif_running(dev))
9166 ixgbe_open(dev);
9167 return -EINVAL;
9168 }
9169
9170 netdev_set_num_tc(dev, tc);
9171 ixgbe_set_prio_tc_map(adapter);
9172
9173 adapter->hw_tcs = tc;
9174 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
9175
9176 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
9177 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
9178 adapter->hw.fc.requested_mode = ixgbe_fc_none;
9179 }
9180 } else {
9181 netdev_reset_tc(dev);
9182
9183 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9184 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
9185
9186 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
9187 adapter->hw_tcs = tc;
9188
9189 adapter->temp_dcb_cfg.pfc_mode_enable = false;
9190 adapter->dcb_cfg.pfc_mode_enable = false;
9191 }
9192
9193 ixgbe_validate_rtr(adapter, tc);
9194
9195 #endif /* CONFIG_IXGBE_DCB */
9196 ixgbe_init_interrupt_scheme(adapter);
9197
9198 ixgbe_defrag_macvlan_pools(dev);
9199
9200 if (netif_running(dev))
9201 return ixgbe_open(dev);
9202
9203 return 0;
9204 }
9205
ixgbe_delete_clsu32(struct ixgbe_adapter * adapter,struct tc_cls_u32_offload * cls)9206 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
9207 struct tc_cls_u32_offload *cls)
9208 {
9209 u32 hdl = cls->knode.handle;
9210 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
9211 u32 loc = cls->knode.handle & 0xfffff;
9212 int err = 0, i, j;
9213 struct ixgbe_jump_table *jump = NULL;
9214
9215 if (loc > IXGBE_MAX_HW_ENTRIES)
9216 return -EINVAL;
9217
9218 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
9219 return -EINVAL;
9220
9221 /* Clear this filter in the link data it is associated with */
9222 if (uhtid != 0x800) {
9223 jump = adapter->jump_tables[uhtid];
9224 if (!jump)
9225 return -EINVAL;
9226 if (!test_bit(loc - 1, jump->child_loc_map))
9227 return -EINVAL;
9228 clear_bit(loc - 1, jump->child_loc_map);
9229 }
9230
9231 /* Check if the filter being deleted is a link */
9232 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9233 jump = adapter->jump_tables[i];
9234 if (jump && jump->link_hdl == hdl) {
9235 /* Delete filters in the hardware in the child hash
9236 * table associated with this link
9237 */
9238 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
9239 if (!test_bit(j, jump->child_loc_map))
9240 continue;
9241 spin_lock(&adapter->fdir_perfect_lock);
9242 err = ixgbe_update_ethtool_fdir_entry(adapter,
9243 NULL,
9244 j + 1);
9245 spin_unlock(&adapter->fdir_perfect_lock);
9246 clear_bit(j, jump->child_loc_map);
9247 }
9248 /* Remove resources for this link */
9249 kfree(jump->input);
9250 kfree(jump->mask);
9251 kfree(jump);
9252 adapter->jump_tables[i] = NULL;
9253 return err;
9254 }
9255 }
9256
9257 spin_lock(&adapter->fdir_perfect_lock);
9258 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
9259 spin_unlock(&adapter->fdir_perfect_lock);
9260 return err;
9261 }
9262
ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter * adapter,struct tc_cls_u32_offload * cls)9263 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
9264 struct tc_cls_u32_offload *cls)
9265 {
9266 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9267
9268 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9269 return -EINVAL;
9270
9271 /* This ixgbe devices do not support hash tables at the moment
9272 * so abort when given hash tables.
9273 */
9274 if (cls->hnode.divisor > 0)
9275 return -EINVAL;
9276
9277 set_bit(uhtid - 1, &adapter->tables);
9278 return 0;
9279 }
9280
ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter * adapter,struct tc_cls_u32_offload * cls)9281 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
9282 struct tc_cls_u32_offload *cls)
9283 {
9284 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9285
9286 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9287 return -EINVAL;
9288
9289 clear_bit(uhtid - 1, &adapter->tables);
9290 return 0;
9291 }
9292
9293 #ifdef CONFIG_NET_CLS_ACT
9294 struct upper_walk_data {
9295 struct ixgbe_adapter *adapter;
9296 u64 action;
9297 int ifindex;
9298 u8 queue;
9299 };
9300
get_macvlan_queue(struct net_device * upper,struct netdev_nested_priv * priv)9301 static int get_macvlan_queue(struct net_device *upper,
9302 struct netdev_nested_priv *priv)
9303 {
9304 if (netif_is_macvlan(upper)) {
9305 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper);
9306 struct ixgbe_adapter *adapter;
9307 struct upper_walk_data *data;
9308 int ifindex;
9309
9310 data = (struct upper_walk_data *)priv->data;
9311 ifindex = data->ifindex;
9312 adapter = data->adapter;
9313 if (vadapter && upper->ifindex == ifindex) {
9314 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
9315 data->action = data->queue;
9316 return 1;
9317 }
9318 }
9319
9320 return 0;
9321 }
9322
handle_redirect_action(struct ixgbe_adapter * adapter,int ifindex,u8 * queue,u64 * action)9323 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
9324 u8 *queue, u64 *action)
9325 {
9326 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
9327 unsigned int num_vfs = adapter->num_vfs, vf;
9328 struct netdev_nested_priv priv;
9329 struct upper_walk_data data;
9330 struct net_device *upper;
9331
9332 /* redirect to a SRIOV VF */
9333 for (vf = 0; vf < num_vfs; ++vf) {
9334 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
9335 if (upper->ifindex == ifindex) {
9336 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask);
9337 *action = vf + 1;
9338 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
9339 return 0;
9340 }
9341 }
9342
9343 /* redirect to a offloaded macvlan netdev */
9344 data.adapter = adapter;
9345 data.ifindex = ifindex;
9346 data.action = 0;
9347 data.queue = 0;
9348 priv.data = (void *)&data;
9349 if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
9350 get_macvlan_queue, &priv)) {
9351 *action = data.action;
9352 *queue = data.queue;
9353
9354 return 0;
9355 }
9356
9357 return -EINVAL;
9358 }
9359
parse_tc_actions(struct ixgbe_adapter * adapter,struct tcf_exts * exts,u64 * action,u8 * queue)9360 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9361 struct tcf_exts *exts, u64 *action, u8 *queue)
9362 {
9363 const struct tc_action *a;
9364 int i;
9365
9366 if (!tcf_exts_has_actions(exts))
9367 return -EINVAL;
9368
9369 tcf_exts_for_each_action(i, a, exts) {
9370 /* Drop action */
9371 if (is_tcf_gact_shot(a)) {
9372 *action = IXGBE_FDIR_DROP_QUEUE;
9373 *queue = IXGBE_FDIR_DROP_QUEUE;
9374 return 0;
9375 }
9376
9377 /* Redirect to a VF or a offloaded macvlan */
9378 if (is_tcf_mirred_egress_redirect(a)) {
9379 struct net_device *dev = tcf_mirred_dev(a);
9380
9381 if (!dev)
9382 return -EINVAL;
9383 return handle_redirect_action(adapter, dev->ifindex,
9384 queue, action);
9385 }
9386
9387 return -EINVAL;
9388 }
9389
9390 return -EINVAL;
9391 }
9392 #else
parse_tc_actions(struct ixgbe_adapter * adapter,struct tcf_exts * exts,u64 * action,u8 * queue)9393 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9394 struct tcf_exts *exts, u64 *action, u8 *queue)
9395 {
9396 return -EINVAL;
9397 }
9398 #endif /* CONFIG_NET_CLS_ACT */
9399
ixgbe_clsu32_build_input(struct ixgbe_fdir_filter * input,union ixgbe_atr_input * mask,struct tc_cls_u32_offload * cls,struct ixgbe_mat_field * field_ptr,struct ixgbe_nexthdr * nexthdr)9400 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
9401 union ixgbe_atr_input *mask,
9402 struct tc_cls_u32_offload *cls,
9403 struct ixgbe_mat_field *field_ptr,
9404 struct ixgbe_nexthdr *nexthdr)
9405 {
9406 int i, j, off;
9407 __be32 val, m;
9408 bool found_entry = false, found_jump_field = false;
9409
9410 for (i = 0; i < cls->knode.sel->nkeys; i++) {
9411 off = cls->knode.sel->keys[i].off;
9412 val = cls->knode.sel->keys[i].val;
9413 m = cls->knode.sel->keys[i].mask;
9414
9415 for (j = 0; field_ptr[j].val; j++) {
9416 if (field_ptr[j].off == off) {
9417 field_ptr[j].val(input, mask, (__force u32)val,
9418 (__force u32)m);
9419 input->filter.formatted.flow_type |=
9420 field_ptr[j].type;
9421 found_entry = true;
9422 break;
9423 }
9424 }
9425 if (nexthdr) {
9426 if (nexthdr->off == cls->knode.sel->keys[i].off &&
9427 nexthdr->val ==
9428 (__force u32)cls->knode.sel->keys[i].val &&
9429 nexthdr->mask ==
9430 (__force u32)cls->knode.sel->keys[i].mask)
9431 found_jump_field = true;
9432 else
9433 continue;
9434 }
9435 }
9436
9437 if (nexthdr && !found_jump_field)
9438 return -EINVAL;
9439
9440 if (!found_entry)
9441 return 0;
9442
9443 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
9444 IXGBE_ATR_L4TYPE_MASK;
9445
9446 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
9447 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
9448
9449 return 0;
9450 }
9451
ixgbe_configure_clsu32(struct ixgbe_adapter * adapter,struct tc_cls_u32_offload * cls)9452 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
9453 struct tc_cls_u32_offload *cls)
9454 {
9455 __be16 protocol = cls->common.protocol;
9456 u32 loc = cls->knode.handle & 0xfffff;
9457 struct ixgbe_hw *hw = &adapter->hw;
9458 struct ixgbe_mat_field *field_ptr;
9459 struct ixgbe_fdir_filter *input = NULL;
9460 union ixgbe_atr_input *mask = NULL;
9461 struct ixgbe_jump_table *jump = NULL;
9462 int i, err = -EINVAL;
9463 u8 queue;
9464 u32 uhtid, link_uhtid;
9465
9466 uhtid = TC_U32_USERHTID(cls->knode.handle);
9467 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
9468
9469 /* At the moment cls_u32 jumps to network layer and skips past
9470 * L2 headers. The canonical method to match L2 frames is to use
9471 * negative values. However this is error prone at best but really
9472 * just broken because there is no way to "know" what sort of hdr
9473 * is in front of the network layer. Fix cls_u32 to support L2
9474 * headers when needed.
9475 */
9476 if (protocol != htons(ETH_P_IP))
9477 return err;
9478
9479 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
9480 e_err(drv, "Location out of range\n");
9481 return err;
9482 }
9483
9484 /* cls u32 is a graph starting at root node 0x800. The driver tracks
9485 * links and also the fields used to advance the parser across each
9486 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
9487 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
9488 * To add support for new nodes update ixgbe_model.h parse structures
9489 * this function _should_ be generic try not to hardcode values here.
9490 */
9491 if (uhtid == 0x800) {
9492 field_ptr = (adapter->jump_tables[0])->mat;
9493 } else {
9494 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9495 return err;
9496 if (!adapter->jump_tables[uhtid])
9497 return err;
9498 field_ptr = (adapter->jump_tables[uhtid])->mat;
9499 }
9500
9501 if (!field_ptr)
9502 return err;
9503
9504 /* At this point we know the field_ptr is valid and need to either
9505 * build cls_u32 link or attach filter. Because adding a link to
9506 * a handle that does not exist is invalid and the same for adding
9507 * rules to handles that don't exist.
9508 */
9509
9510 if (link_uhtid) {
9511 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
9512
9513 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
9514 return err;
9515
9516 if (!test_bit(link_uhtid - 1, &adapter->tables))
9517 return err;
9518
9519 /* Multiple filters as links to the same hash table are not
9520 * supported. To add a new filter with the same next header
9521 * but different match/jump conditions, create a new hash table
9522 * and link to it.
9523 */
9524 if (adapter->jump_tables[link_uhtid] &&
9525 (adapter->jump_tables[link_uhtid])->link_hdl) {
9526 e_err(drv, "Link filter exists for link: %x\n",
9527 link_uhtid);
9528 return err;
9529 }
9530
9531 for (i = 0; nexthdr[i].jump; i++) {
9532 if (nexthdr[i].o != cls->knode.sel->offoff ||
9533 nexthdr[i].s != cls->knode.sel->offshift ||
9534 nexthdr[i].m !=
9535 (__force u32)cls->knode.sel->offmask)
9536 return err;
9537
9538 jump = kzalloc(sizeof(*jump), GFP_KERNEL);
9539 if (!jump)
9540 return -ENOMEM;
9541 input = kzalloc(sizeof(*input), GFP_KERNEL);
9542 if (!input) {
9543 err = -ENOMEM;
9544 goto free_jump;
9545 }
9546 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9547 if (!mask) {
9548 err = -ENOMEM;
9549 goto free_input;
9550 }
9551 jump->input = input;
9552 jump->mask = mask;
9553 jump->link_hdl = cls->knode.handle;
9554
9555 err = ixgbe_clsu32_build_input(input, mask, cls,
9556 field_ptr, &nexthdr[i]);
9557 if (!err) {
9558 jump->mat = nexthdr[i].jump;
9559 adapter->jump_tables[link_uhtid] = jump;
9560 break;
9561 } else {
9562 kfree(mask);
9563 kfree(input);
9564 kfree(jump);
9565 }
9566 }
9567 return 0;
9568 }
9569
9570 input = kzalloc(sizeof(*input), GFP_KERNEL);
9571 if (!input)
9572 return -ENOMEM;
9573 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9574 if (!mask) {
9575 err = -ENOMEM;
9576 goto free_input;
9577 }
9578
9579 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
9580 if ((adapter->jump_tables[uhtid])->input)
9581 memcpy(input, (adapter->jump_tables[uhtid])->input,
9582 sizeof(*input));
9583 if ((adapter->jump_tables[uhtid])->mask)
9584 memcpy(mask, (adapter->jump_tables[uhtid])->mask,
9585 sizeof(*mask));
9586
9587 /* Lookup in all child hash tables if this location is already
9588 * filled with a filter
9589 */
9590 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9591 struct ixgbe_jump_table *link = adapter->jump_tables[i];
9592
9593 if (link && (test_bit(loc - 1, link->child_loc_map))) {
9594 e_err(drv, "Filter exists in location: %x\n",
9595 loc);
9596 err = -EINVAL;
9597 goto err_out;
9598 }
9599 }
9600 }
9601 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
9602 if (err)
9603 goto err_out;
9604
9605 err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
9606 &queue);
9607 if (err < 0)
9608 goto err_out;
9609
9610 input->sw_idx = loc;
9611
9612 spin_lock(&adapter->fdir_perfect_lock);
9613
9614 if (hlist_empty(&adapter->fdir_filter_list)) {
9615 memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
9616 err = ixgbe_fdir_set_input_mask_82599(hw, mask);
9617 if (err)
9618 goto err_out_w_lock;
9619 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
9620 err = -EINVAL;
9621 goto err_out_w_lock;
9622 }
9623
9624 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
9625 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
9626 input->sw_idx, queue);
9627 if (err)
9628 goto err_out_w_lock;
9629
9630 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
9631 spin_unlock(&adapter->fdir_perfect_lock);
9632
9633 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
9634 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
9635
9636 kfree(mask);
9637 return err;
9638 err_out_w_lock:
9639 spin_unlock(&adapter->fdir_perfect_lock);
9640 err_out:
9641 kfree(mask);
9642 free_input:
9643 kfree(input);
9644 free_jump:
9645 kfree(jump);
9646 return err;
9647 }
9648
ixgbe_setup_tc_cls_u32(struct ixgbe_adapter * adapter,struct tc_cls_u32_offload * cls_u32)9649 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter,
9650 struct tc_cls_u32_offload *cls_u32)
9651 {
9652 switch (cls_u32->command) {
9653 case TC_CLSU32_NEW_KNODE:
9654 case TC_CLSU32_REPLACE_KNODE:
9655 return ixgbe_configure_clsu32(adapter, cls_u32);
9656 case TC_CLSU32_DELETE_KNODE:
9657 return ixgbe_delete_clsu32(adapter, cls_u32);
9658 case TC_CLSU32_NEW_HNODE:
9659 case TC_CLSU32_REPLACE_HNODE:
9660 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32);
9661 case TC_CLSU32_DELETE_HNODE:
9662 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32);
9663 default:
9664 return -EOPNOTSUPP;
9665 }
9666 }
9667
ixgbe_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)9668 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9669 void *cb_priv)
9670 {
9671 struct ixgbe_adapter *adapter = cb_priv;
9672
9673 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
9674 return -EOPNOTSUPP;
9675
9676 switch (type) {
9677 case TC_SETUP_CLSU32:
9678 return ixgbe_setup_tc_cls_u32(adapter, type_data);
9679 default:
9680 return -EOPNOTSUPP;
9681 }
9682 }
9683
ixgbe_setup_tc_mqprio(struct net_device * dev,struct tc_mqprio_qopt * mqprio)9684 static int ixgbe_setup_tc_mqprio(struct net_device *dev,
9685 struct tc_mqprio_qopt *mqprio)
9686 {
9687 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9688 return ixgbe_setup_tc(dev, mqprio->num_tc);
9689 }
9690
9691 static LIST_HEAD(ixgbe_block_cb_list);
9692
__ixgbe_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)9693 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type,
9694 void *type_data)
9695 {
9696 struct ixgbe_adapter *adapter = netdev_priv(dev);
9697
9698 switch (type) {
9699 case TC_SETUP_BLOCK:
9700 return flow_block_cb_setup_simple(type_data,
9701 &ixgbe_block_cb_list,
9702 ixgbe_setup_tc_block_cb,
9703 adapter, adapter, true);
9704 case TC_SETUP_QDISC_MQPRIO:
9705 return ixgbe_setup_tc_mqprio(dev, type_data);
9706 default:
9707 return -EOPNOTSUPP;
9708 }
9709 }
9710
9711 #ifdef CONFIG_PCI_IOV
ixgbe_sriov_reinit(struct ixgbe_adapter * adapter)9712 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
9713 {
9714 struct net_device *netdev = adapter->netdev;
9715
9716 rtnl_lock();
9717 ixgbe_setup_tc(netdev, adapter->hw_tcs);
9718 rtnl_unlock();
9719 }
9720
9721 #endif
ixgbe_do_reset(struct net_device * netdev)9722 void ixgbe_do_reset(struct net_device *netdev)
9723 {
9724 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9725
9726 if (netif_running(netdev))
9727 ixgbe_reinit_locked(adapter);
9728 else
9729 ixgbe_reset(adapter);
9730 }
9731
ixgbe_fix_features(struct net_device * netdev,netdev_features_t features)9732 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
9733 netdev_features_t features)
9734 {
9735 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9736
9737 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
9738 if (!(features & NETIF_F_RXCSUM))
9739 features &= ~NETIF_F_LRO;
9740
9741 /* Turn off LRO if not RSC capable */
9742 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
9743 features &= ~NETIF_F_LRO;
9744
9745 if (adapter->xdp_prog && (features & NETIF_F_LRO)) {
9746 e_dev_err("LRO is not supported with XDP\n");
9747 features &= ~NETIF_F_LRO;
9748 }
9749
9750 return features;
9751 }
9752
ixgbe_reset_l2fw_offload(struct ixgbe_adapter * adapter)9753 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter)
9754 {
9755 int rss = min_t(int, ixgbe_max_rss_indices(adapter),
9756 num_online_cpus());
9757
9758 /* go back to full RSS if we're not running SR-IOV */
9759 if (!adapter->ring_feature[RING_F_VMDQ].offset)
9760 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED |
9761 IXGBE_FLAG_SRIOV_ENABLED);
9762
9763 adapter->ring_feature[RING_F_RSS].limit = rss;
9764 adapter->ring_feature[RING_F_VMDQ].limit = 1;
9765
9766 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs);
9767 }
9768
ixgbe_set_features(struct net_device * netdev,netdev_features_t features)9769 static int ixgbe_set_features(struct net_device *netdev,
9770 netdev_features_t features)
9771 {
9772 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9773 netdev_features_t changed = netdev->features ^ features;
9774 bool need_reset = false;
9775
9776 /* Make sure RSC matches LRO, reset if change */
9777 if (!(features & NETIF_F_LRO)) {
9778 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
9779 need_reset = true;
9780 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
9781 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
9782 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
9783 if (adapter->rx_itr_setting == 1 ||
9784 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
9785 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9786 need_reset = true;
9787 } else if ((changed ^ features) & NETIF_F_LRO) {
9788 e_info(probe, "rx-usecs set too low, "
9789 "disabling RSC\n");
9790 }
9791 }
9792
9793 /*
9794 * Check if Flow Director n-tuple support or hw_tc support was
9795 * enabled or disabled. If the state changed, we need to reset.
9796 */
9797 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
9798 /* turn off ATR, enable perfect filters and reset */
9799 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
9800 need_reset = true;
9801
9802 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
9803 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9804 } else {
9805 /* turn off perfect filters, enable ATR and reset */
9806 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
9807 need_reset = true;
9808
9809 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9810
9811 /* We cannot enable ATR if SR-IOV is enabled */
9812 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
9813 /* We cannot enable ATR if we have 2 or more tcs */
9814 (adapter->hw_tcs > 1) ||
9815 /* We cannot enable ATR if RSS is disabled */
9816 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
9817 /* A sample rate of 0 indicates ATR disabled */
9818 (!adapter->atr_sample_rate))
9819 ; /* do nothing not supported */
9820 else /* otherwise supported and set the flag */
9821 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
9822 }
9823
9824 if (changed & NETIF_F_RXALL)
9825 need_reset = true;
9826
9827 netdev->features = features;
9828
9829 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1)
9830 ixgbe_reset_l2fw_offload(adapter);
9831 else if (need_reset)
9832 ixgbe_do_reset(netdev);
9833 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
9834 NETIF_F_HW_VLAN_CTAG_FILTER))
9835 ixgbe_set_rx_mode(netdev);
9836
9837 return 1;
9838 }
9839
ixgbe_ndo_fdb_add(struct ndmsg * ndm,struct nlattr * tb[],struct net_device * dev,const unsigned char * addr,u16 vid,u16 flags,struct netlink_ext_ack * extack)9840 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
9841 struct net_device *dev,
9842 const unsigned char *addr, u16 vid,
9843 u16 flags,
9844 struct netlink_ext_ack *extack)
9845 {
9846 /* guarantee we can provide a unique filter for the unicast address */
9847 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
9848 struct ixgbe_adapter *adapter = netdev_priv(dev);
9849 u16 pool = VMDQ_P(0);
9850
9851 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
9852 return -ENOMEM;
9853 }
9854
9855 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
9856 }
9857
9858 /**
9859 * ixgbe_configure_bridge_mode - set various bridge modes
9860 * @adapter: the private structure
9861 * @mode: requested bridge mode
9862 *
9863 * Configure some settings require for various bridge modes.
9864 **/
ixgbe_configure_bridge_mode(struct ixgbe_adapter * adapter,__u16 mode)9865 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9866 __u16 mode)
9867 {
9868 struct ixgbe_hw *hw = &adapter->hw;
9869 unsigned int p, num_pools;
9870 u32 vmdctl;
9871
9872 switch (mode) {
9873 case BRIDGE_MODE_VEPA:
9874 /* disable Tx loopback, rely on switch hairpin mode */
9875 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
9876
9877 /* must enable Rx switching replication to allow multicast
9878 * packet reception on all VFs, and to enable source address
9879 * pruning.
9880 */
9881 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9882 vmdctl |= IXGBE_VT_CTL_REPLEN;
9883 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9884
9885 /* enable Rx source address pruning. Note, this requires
9886 * replication to be enabled or else it does nothing.
9887 */
9888 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9889 for (p = 0; p < num_pools; p++) {
9890 if (hw->mac.ops.set_source_address_pruning)
9891 hw->mac.ops.set_source_address_pruning(hw,
9892 true,
9893 p);
9894 }
9895 break;
9896 case BRIDGE_MODE_VEB:
9897 /* enable Tx loopback for internal VF/PF communication */
9898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
9899 IXGBE_PFDTXGSWC_VT_LBEN);
9900
9901 /* disable Rx switching replication unless we have SR-IOV
9902 * virtual functions
9903 */
9904 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9905 if (!adapter->num_vfs)
9906 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
9907 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9908
9909 /* disable Rx source address pruning, since we don't expect to
9910 * be receiving external loopback of our transmitted frames.
9911 */
9912 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9913 for (p = 0; p < num_pools; p++) {
9914 if (hw->mac.ops.set_source_address_pruning)
9915 hw->mac.ops.set_source_address_pruning(hw,
9916 false,
9917 p);
9918 }
9919 break;
9920 default:
9921 return -EINVAL;
9922 }
9923
9924 adapter->bridge_mode = mode;
9925
9926 e_info(drv, "enabling bridge mode: %s\n",
9927 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
9928
9929 return 0;
9930 }
9931
ixgbe_ndo_bridge_setlink(struct net_device * dev,struct nlmsghdr * nlh,u16 flags,struct netlink_ext_ack * extack)9932 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
9933 struct nlmsghdr *nlh, u16 flags,
9934 struct netlink_ext_ack *extack)
9935 {
9936 struct ixgbe_adapter *adapter = netdev_priv(dev);
9937 struct nlattr *attr, *br_spec;
9938 int rem;
9939
9940 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9941 return -EOPNOTSUPP;
9942
9943 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
9944 if (!br_spec)
9945 return -EINVAL;
9946
9947 nla_for_each_nested(attr, br_spec, rem) {
9948 int status;
9949 __u16 mode;
9950
9951 if (nla_type(attr) != IFLA_BRIDGE_MODE)
9952 continue;
9953
9954 if (nla_len(attr) < sizeof(mode))
9955 return -EINVAL;
9956
9957 mode = nla_get_u16(attr);
9958 status = ixgbe_configure_bridge_mode(adapter, mode);
9959 if (status)
9960 return status;
9961
9962 break;
9963 }
9964
9965 return 0;
9966 }
9967
ixgbe_ndo_bridge_getlink(struct sk_buff * skb,u32 pid,u32 seq,struct net_device * dev,u32 filter_mask,int nlflags)9968 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
9969 struct net_device *dev,
9970 u32 filter_mask, int nlflags)
9971 {
9972 struct ixgbe_adapter *adapter = netdev_priv(dev);
9973
9974 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9975 return 0;
9976
9977 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
9978 adapter->bridge_mode, 0, 0, nlflags,
9979 filter_mask, NULL);
9980 }
9981
ixgbe_fwd_add(struct net_device * pdev,struct net_device * vdev)9982 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
9983 {
9984 struct ixgbe_adapter *adapter = netdev_priv(pdev);
9985 struct ixgbe_fwd_adapter *accel;
9986 int tcs = adapter->hw_tcs ? : 1;
9987 int pool, err;
9988
9989 if (adapter->xdp_prog) {
9990 e_warn(probe, "L2FW offload is not supported with XDP\n");
9991 return ERR_PTR(-EINVAL);
9992 }
9993
9994 /* The hardware supported by ixgbe only filters on the destination MAC
9995 * address. In order to avoid issues we only support offloading modes
9996 * where the hardware can actually provide the functionality.
9997 */
9998 if (!macvlan_supports_dest_filter(vdev))
9999 return ERR_PTR(-EMEDIUMTYPE);
10000
10001 /* We need to lock down the macvlan to be a single queue device so that
10002 * we can reuse the tc_to_txq field in the macvlan netdev to represent
10003 * the queue mapping to our netdev.
10004 */
10005 if (netif_is_multiqueue(vdev))
10006 return ERR_PTR(-ERANGE);
10007
10008 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
10009 if (pool == adapter->num_rx_pools) {
10010 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools;
10011 u16 reserved_pools;
10012
10013 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
10014 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) ||
10015 adapter->num_rx_pools > IXGBE_MAX_MACVLANS)
10016 return ERR_PTR(-EBUSY);
10017
10018 /* Hardware has a limited number of available pools. Each VF,
10019 * and the PF require a pool. Check to ensure we don't
10020 * attempt to use more then the available number of pools.
10021 */
10022 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
10023 return ERR_PTR(-EBUSY);
10024
10025 /* Enable VMDq flag so device will be set in VM mode */
10026 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED |
10027 IXGBE_FLAG_SRIOV_ENABLED;
10028
10029 /* Try to reserve as many queues per pool as possible,
10030 * we start with the configurations that support 4 queues
10031 * per pools, followed by 2, and then by just 1 per pool.
10032 */
10033 if (used_pools < 32 && adapter->num_rx_pools < 16)
10034 reserved_pools = min_t(u16,
10035 32 - used_pools,
10036 16 - adapter->num_rx_pools);
10037 else if (adapter->num_rx_pools < 32)
10038 reserved_pools = min_t(u16,
10039 64 - used_pools,
10040 32 - adapter->num_rx_pools);
10041 else
10042 reserved_pools = 64 - used_pools;
10043
10044
10045 if (!reserved_pools)
10046 return ERR_PTR(-EBUSY);
10047
10048 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools;
10049
10050 /* Force reinit of ring allocation with VMDQ enabled */
10051 err = ixgbe_setup_tc(pdev, adapter->hw_tcs);
10052 if (err)
10053 return ERR_PTR(err);
10054
10055 if (pool >= adapter->num_rx_pools)
10056 return ERR_PTR(-ENOMEM);
10057 }
10058
10059 accel = kzalloc(sizeof(*accel), GFP_KERNEL);
10060 if (!accel)
10061 return ERR_PTR(-ENOMEM);
10062
10063 set_bit(pool, adapter->fwd_bitmask);
10064 netdev_set_sb_channel(vdev, pool);
10065 accel->pool = pool;
10066 accel->netdev = vdev;
10067
10068 if (!netif_running(pdev))
10069 return accel;
10070
10071 err = ixgbe_fwd_ring_up(adapter, accel);
10072 if (err)
10073 return ERR_PTR(err);
10074
10075 return accel;
10076 }
10077
ixgbe_fwd_del(struct net_device * pdev,void * priv)10078 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
10079 {
10080 struct ixgbe_fwd_adapter *accel = priv;
10081 struct ixgbe_adapter *adapter = netdev_priv(pdev);
10082 unsigned int rxbase = accel->rx_base_queue;
10083 unsigned int i;
10084
10085 /* delete unicast filter associated with offloaded interface */
10086 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr,
10087 VMDQ_P(accel->pool));
10088
10089 /* Allow remaining Rx packets to get flushed out of the
10090 * Rx FIFO before we drop the netdev for the ring.
10091 */
10092 usleep_range(10000, 20000);
10093
10094 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
10095 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i];
10096 struct ixgbe_q_vector *qv = ring->q_vector;
10097
10098 /* Make sure we aren't processing any packets and clear
10099 * netdev to shut down the ring.
10100 */
10101 if (netif_running(adapter->netdev))
10102 napi_synchronize(&qv->napi);
10103 ring->netdev = NULL;
10104 }
10105
10106 /* unbind the queues and drop the subordinate channel config */
10107 netdev_unbind_sb_channel(pdev, accel->netdev);
10108 netdev_set_sb_channel(accel->netdev, 0);
10109
10110 clear_bit(accel->pool, adapter->fwd_bitmask);
10111 kfree(accel);
10112 }
10113
10114 #define IXGBE_MAX_MAC_HDR_LEN 127
10115 #define IXGBE_MAX_NETWORK_HDR_LEN 511
10116
10117 static netdev_features_t
ixgbe_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)10118 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
10119 netdev_features_t features)
10120 {
10121 unsigned int network_hdr_len, mac_hdr_len;
10122
10123 /* Make certain the headers can be described by a context descriptor */
10124 mac_hdr_len = skb_network_header(skb) - skb->data;
10125 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
10126 return features & ~(NETIF_F_HW_CSUM |
10127 NETIF_F_SCTP_CRC |
10128 NETIF_F_GSO_UDP_L4 |
10129 NETIF_F_HW_VLAN_CTAG_TX |
10130 NETIF_F_TSO |
10131 NETIF_F_TSO6);
10132
10133 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
10134 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
10135 return features & ~(NETIF_F_HW_CSUM |
10136 NETIF_F_SCTP_CRC |
10137 NETIF_F_GSO_UDP_L4 |
10138 NETIF_F_TSO |
10139 NETIF_F_TSO6);
10140
10141 /* We can only support IPV4 TSO in tunnels if we can mangle the
10142 * inner IP ID field, so strip TSO if MANGLEID is not supported.
10143 * IPsec offoad sets skb->encapsulation but still can handle
10144 * the TSO, so it's the exception.
10145 */
10146 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) {
10147 #ifdef CONFIG_IXGBE_IPSEC
10148 if (!secpath_exists(skb))
10149 #endif
10150 features &= ~NETIF_F_TSO;
10151 }
10152
10153 return features;
10154 }
10155
ixgbe_xdp_setup(struct net_device * dev,struct bpf_prog * prog)10156 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog)
10157 {
10158 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
10159 struct ixgbe_adapter *adapter = netdev_priv(dev);
10160 struct bpf_prog *old_prog;
10161 bool need_reset;
10162 int num_queues;
10163
10164 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
10165 return -EINVAL;
10166
10167 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
10168 return -EINVAL;
10169
10170 /* verify ixgbe ring attributes are sufficient for XDP */
10171 for (i = 0; i < adapter->num_rx_queues; i++) {
10172 struct ixgbe_ring *ring = adapter->rx_ring[i];
10173
10174 if (ring_is_rsc_enabled(ring))
10175 return -EINVAL;
10176
10177 if (frame_size > ixgbe_rx_bufsz(ring))
10178 return -EINVAL;
10179 }
10180
10181 if (nr_cpu_ids > MAX_XDP_QUEUES)
10182 return -ENOMEM;
10183
10184 old_prog = xchg(&adapter->xdp_prog, prog);
10185 need_reset = (!!prog != !!old_prog);
10186
10187 /* If transitioning XDP modes reconfigure rings */
10188 if (need_reset) {
10189 int err;
10190
10191 if (!prog)
10192 /* Wait until ndo_xsk_wakeup completes. */
10193 synchronize_rcu();
10194 err = ixgbe_setup_tc(dev, adapter->hw_tcs);
10195
10196 if (err) {
10197 rcu_assign_pointer(adapter->xdp_prog, old_prog);
10198 return -EINVAL;
10199 }
10200 } else {
10201 for (i = 0; i < adapter->num_rx_queues; i++)
10202 (void)xchg(&adapter->rx_ring[i]->xdp_prog,
10203 adapter->xdp_prog);
10204 }
10205
10206 if (old_prog)
10207 bpf_prog_put(old_prog);
10208
10209 /* Kick start the NAPI context if there is an AF_XDP socket open
10210 * on that queue id. This so that receiving will start.
10211 */
10212 if (need_reset && prog) {
10213 num_queues = min_t(int, adapter->num_rx_queues,
10214 adapter->num_xdp_queues);
10215 for (i = 0; i < num_queues; i++)
10216 if (adapter->xdp_ring[i]->xsk_pool)
10217 (void)ixgbe_xsk_wakeup(adapter->netdev, i,
10218 XDP_WAKEUP_RX);
10219 }
10220
10221 return 0;
10222 }
10223
ixgbe_xdp(struct net_device * dev,struct netdev_bpf * xdp)10224 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp)
10225 {
10226 struct ixgbe_adapter *adapter = netdev_priv(dev);
10227
10228 switch (xdp->command) {
10229 case XDP_SETUP_PROG:
10230 return ixgbe_xdp_setup(dev, xdp->prog);
10231 case XDP_SETUP_XSK_POOL:
10232 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool,
10233 xdp->xsk.queue_id);
10234
10235 default:
10236 return -EINVAL;
10237 }
10238 }
10239
ixgbe_xdp_ring_update_tail(struct ixgbe_ring * ring)10240 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring)
10241 {
10242 /* Force memory writes to complete before letting h/w know there
10243 * are new descriptors to fetch.
10244 */
10245 wmb();
10246 writel(ring->next_to_use, ring->tail);
10247 }
10248
ixgbe_xdp_xmit(struct net_device * dev,int n,struct xdp_frame ** frames,u32 flags)10249 static int ixgbe_xdp_xmit(struct net_device *dev, int n,
10250 struct xdp_frame **frames, u32 flags)
10251 {
10252 struct ixgbe_adapter *adapter = netdev_priv(dev);
10253 struct ixgbe_ring *ring;
10254 int drops = 0;
10255 int i;
10256
10257 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state)))
10258 return -ENETDOWN;
10259
10260 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
10261 return -EINVAL;
10262
10263 /* During program transitions its possible adapter->xdp_prog is assigned
10264 * but ring has not been configured yet. In this case simply abort xmit.
10265 */
10266 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL;
10267 if (unlikely(!ring))
10268 return -ENXIO;
10269
10270 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state)))
10271 return -ENXIO;
10272
10273 for (i = 0; i < n; i++) {
10274 struct xdp_frame *xdpf = frames[i];
10275 int err;
10276
10277 err = ixgbe_xmit_xdp_ring(adapter, xdpf);
10278 if (err != IXGBE_XDP_TX) {
10279 xdp_return_frame_rx_napi(xdpf);
10280 drops++;
10281 }
10282 }
10283
10284 if (unlikely(flags & XDP_XMIT_FLUSH))
10285 ixgbe_xdp_ring_update_tail(ring);
10286
10287 return n - drops;
10288 }
10289
10290 static const struct net_device_ops ixgbe_netdev_ops = {
10291 .ndo_open = ixgbe_open,
10292 .ndo_stop = ixgbe_close,
10293 .ndo_start_xmit = ixgbe_xmit_frame,
10294 .ndo_set_rx_mode = ixgbe_set_rx_mode,
10295 .ndo_validate_addr = eth_validate_addr,
10296 .ndo_set_mac_address = ixgbe_set_mac,
10297 .ndo_change_mtu = ixgbe_change_mtu,
10298 .ndo_tx_timeout = ixgbe_tx_timeout,
10299 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
10300 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
10301 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
10302 .ndo_do_ioctl = ixgbe_ioctl,
10303 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
10304 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
10305 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
10306 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
10307 .ndo_set_vf_link_state = ixgbe_ndo_set_vf_link_state,
10308 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
10309 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
10310 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
10311 .ndo_get_stats64 = ixgbe_get_stats64,
10312 .ndo_setup_tc = __ixgbe_setup_tc,
10313 #ifdef IXGBE_FCOE
10314 .ndo_select_queue = ixgbe_select_queue,
10315 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
10316 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
10317 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
10318 .ndo_fcoe_enable = ixgbe_fcoe_enable,
10319 .ndo_fcoe_disable = ixgbe_fcoe_disable,
10320 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
10321 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
10322 #endif /* IXGBE_FCOE */
10323 .ndo_set_features = ixgbe_set_features,
10324 .ndo_fix_features = ixgbe_fix_features,
10325 .ndo_fdb_add = ixgbe_ndo_fdb_add,
10326 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
10327 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
10328 .ndo_dfwd_add_station = ixgbe_fwd_add,
10329 .ndo_dfwd_del_station = ixgbe_fwd_del,
10330 .ndo_udp_tunnel_add = udp_tunnel_nic_add_port,
10331 .ndo_udp_tunnel_del = udp_tunnel_nic_del_port,
10332 .ndo_features_check = ixgbe_features_check,
10333 .ndo_bpf = ixgbe_xdp,
10334 .ndo_xdp_xmit = ixgbe_xdp_xmit,
10335 .ndo_xsk_wakeup = ixgbe_xsk_wakeup,
10336 };
10337
ixgbe_disable_txr_hw(struct ixgbe_adapter * adapter,struct ixgbe_ring * tx_ring)10338 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter,
10339 struct ixgbe_ring *tx_ring)
10340 {
10341 unsigned long wait_delay, delay_interval;
10342 struct ixgbe_hw *hw = &adapter->hw;
10343 u8 reg_idx = tx_ring->reg_idx;
10344 int wait_loop;
10345 u32 txdctl;
10346
10347 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
10348
10349 /* delay mechanism from ixgbe_disable_tx */
10350 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10351
10352 wait_loop = IXGBE_MAX_RX_DESC_POLL;
10353 wait_delay = delay_interval;
10354
10355 while (wait_loop--) {
10356 usleep_range(wait_delay, wait_delay + 10);
10357 wait_delay += delay_interval * 2;
10358 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
10359
10360 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
10361 return;
10362 }
10363
10364 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n");
10365 }
10366
ixgbe_disable_txr(struct ixgbe_adapter * adapter,struct ixgbe_ring * tx_ring)10367 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter,
10368 struct ixgbe_ring *tx_ring)
10369 {
10370 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10371 ixgbe_disable_txr_hw(adapter, tx_ring);
10372 }
10373
ixgbe_disable_rxr_hw(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring)10374 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter,
10375 struct ixgbe_ring *rx_ring)
10376 {
10377 unsigned long wait_delay, delay_interval;
10378 struct ixgbe_hw *hw = &adapter->hw;
10379 u8 reg_idx = rx_ring->reg_idx;
10380 int wait_loop;
10381 u32 rxdctl;
10382
10383 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10384 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
10385 rxdctl |= IXGBE_RXDCTL_SWFLSH;
10386
10387 /* write value back with RXDCTL.ENABLE bit cleared */
10388 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
10389
10390 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
10391 if (hw->mac.type == ixgbe_mac_82598EB &&
10392 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
10393 return;
10394
10395 /* delay mechanism from ixgbe_disable_rx */
10396 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10397
10398 wait_loop = IXGBE_MAX_RX_DESC_POLL;
10399 wait_delay = delay_interval;
10400
10401 while (wait_loop--) {
10402 usleep_range(wait_delay, wait_delay + 10);
10403 wait_delay += delay_interval * 2;
10404 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10405
10406 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
10407 return;
10408 }
10409
10410 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n");
10411 }
10412
ixgbe_reset_txr_stats(struct ixgbe_ring * tx_ring)10413 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring)
10414 {
10415 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats));
10416 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats));
10417 }
10418
ixgbe_reset_rxr_stats(struct ixgbe_ring * rx_ring)10419 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring)
10420 {
10421 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats));
10422 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats));
10423 }
10424
10425 /**
10426 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings
10427 * @adapter: adapter structure
10428 * @ring: ring index
10429 *
10430 * This function disables a certain Rx/Tx/XDP Tx ring. The function
10431 * assumes that the netdev is running.
10432 **/
ixgbe_txrx_ring_disable(struct ixgbe_adapter * adapter,int ring)10433 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring)
10434 {
10435 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10436
10437 rx_ring = adapter->rx_ring[ring];
10438 tx_ring = adapter->tx_ring[ring];
10439 xdp_ring = adapter->xdp_ring[ring];
10440
10441 ixgbe_disable_txr(adapter, tx_ring);
10442 if (xdp_ring)
10443 ixgbe_disable_txr(adapter, xdp_ring);
10444 ixgbe_disable_rxr_hw(adapter, rx_ring);
10445
10446 if (xdp_ring)
10447 synchronize_rcu();
10448
10449 /* Rx/Tx/XDP Tx share the same napi context. */
10450 napi_disable(&rx_ring->q_vector->napi);
10451
10452 ixgbe_clean_tx_ring(tx_ring);
10453 if (xdp_ring)
10454 ixgbe_clean_tx_ring(xdp_ring);
10455 ixgbe_clean_rx_ring(rx_ring);
10456
10457 ixgbe_reset_txr_stats(tx_ring);
10458 if (xdp_ring)
10459 ixgbe_reset_txr_stats(xdp_ring);
10460 ixgbe_reset_rxr_stats(rx_ring);
10461 }
10462
10463 /**
10464 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings
10465 * @adapter: adapter structure
10466 * @ring: ring index
10467 *
10468 * This function enables a certain Rx/Tx/XDP Tx ring. The function
10469 * assumes that the netdev is running.
10470 **/
ixgbe_txrx_ring_enable(struct ixgbe_adapter * adapter,int ring)10471 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring)
10472 {
10473 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10474
10475 rx_ring = adapter->rx_ring[ring];
10476 tx_ring = adapter->tx_ring[ring];
10477 xdp_ring = adapter->xdp_ring[ring];
10478
10479 /* Rx/Tx/XDP Tx share the same napi context. */
10480 napi_enable(&rx_ring->q_vector->napi);
10481
10482 ixgbe_configure_tx_ring(adapter, tx_ring);
10483 if (xdp_ring)
10484 ixgbe_configure_tx_ring(adapter, xdp_ring);
10485 ixgbe_configure_rx_ring(adapter, rx_ring);
10486
10487 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10488 if (xdp_ring)
10489 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state);
10490 }
10491
10492 /**
10493 * ixgbe_enumerate_functions - Get the number of ports this device has
10494 * @adapter: adapter structure
10495 *
10496 * This function enumerates the phsyical functions co-located on a single slot,
10497 * in order to determine how many ports a device has. This is most useful in
10498 * determining the required GT/s of PCIe bandwidth necessary for optimal
10499 * performance.
10500 **/
ixgbe_enumerate_functions(struct ixgbe_adapter * adapter)10501 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
10502 {
10503 struct pci_dev *entry, *pdev = adapter->pdev;
10504 int physfns = 0;
10505
10506 /* Some cards can not use the generic count PCIe functions method,
10507 * because they are behind a parent switch, so we hardcode these with
10508 * the correct number of functions.
10509 */
10510 if (ixgbe_pcie_from_parent(&adapter->hw))
10511 physfns = 4;
10512
10513 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
10514 /* don't count virtual functions */
10515 if (entry->is_virtfn)
10516 continue;
10517
10518 /* When the devices on the bus don't all match our device ID,
10519 * we can't reliably determine the correct number of
10520 * functions. This can occur if a function has been direct
10521 * attached to a virtual machine using VT-d, for example. In
10522 * this case, simply return -1 to indicate this.
10523 */
10524 if ((entry->vendor != pdev->vendor) ||
10525 (entry->device != pdev->device))
10526 return -1;
10527
10528 physfns++;
10529 }
10530
10531 return physfns;
10532 }
10533
10534 /**
10535 * ixgbe_wol_supported - Check whether device supports WoL
10536 * @adapter: the adapter private structure
10537 * @device_id: the device ID
10538 * @subdevice_id: the subsystem device ID
10539 *
10540 * This function is used by probe and ethtool to determine
10541 * which devices have WoL support
10542 *
10543 **/
ixgbe_wol_supported(struct ixgbe_adapter * adapter,u16 device_id,u16 subdevice_id)10544 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
10545 u16 subdevice_id)
10546 {
10547 struct ixgbe_hw *hw = &adapter->hw;
10548 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
10549
10550 /* WOL not supported on 82598 */
10551 if (hw->mac.type == ixgbe_mac_82598EB)
10552 return false;
10553
10554 /* check eeprom to see if WOL is enabled for X540 and newer */
10555 if (hw->mac.type >= ixgbe_mac_X540) {
10556 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
10557 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
10558 (hw->bus.func == 0)))
10559 return true;
10560 }
10561
10562 /* WOL is determined based on device IDs for 82599 MACs */
10563 switch (device_id) {
10564 case IXGBE_DEV_ID_82599_SFP:
10565 /* Only these subdevices could supports WOL */
10566 switch (subdevice_id) {
10567 case IXGBE_SUBDEV_ID_82599_560FLR:
10568 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
10569 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
10570 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
10571 /* only support first port */
10572 if (hw->bus.func != 0)
10573 break;
10574 fallthrough;
10575 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
10576 case IXGBE_SUBDEV_ID_82599_SFP:
10577 case IXGBE_SUBDEV_ID_82599_RNDC:
10578 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
10579 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
10580 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
10581 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
10582 return true;
10583 }
10584 break;
10585 case IXGBE_DEV_ID_82599EN_SFP:
10586 /* Only these subdevices support WOL */
10587 switch (subdevice_id) {
10588 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
10589 return true;
10590 }
10591 break;
10592 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
10593 /* All except this subdevice support WOL */
10594 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
10595 return true;
10596 break;
10597 case IXGBE_DEV_ID_82599_KX4:
10598 return true;
10599 default:
10600 break;
10601 }
10602
10603 return false;
10604 }
10605
10606 /**
10607 * ixgbe_set_fw_version - Set FW version
10608 * @adapter: the adapter private structure
10609 *
10610 * This function is used by probe and ethtool to determine the FW version to
10611 * format to display. The FW version is taken from the EEPROM/NVM.
10612 */
ixgbe_set_fw_version(struct ixgbe_adapter * adapter)10613 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter)
10614 {
10615 struct ixgbe_hw *hw = &adapter->hw;
10616 struct ixgbe_nvm_version nvm_ver;
10617
10618 ixgbe_get_oem_prod_version(hw, &nvm_ver);
10619 if (nvm_ver.oem_valid) {
10620 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10621 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor,
10622 nvm_ver.oem_release);
10623 return;
10624 }
10625
10626 ixgbe_get_etk_id(hw, &nvm_ver);
10627 ixgbe_get_orom_version(hw, &nvm_ver);
10628
10629 if (nvm_ver.or_valid) {
10630 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10631 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major,
10632 nvm_ver.or_build, nvm_ver.or_patch);
10633 return;
10634 }
10635
10636 /* Set ETrack ID format */
10637 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10638 "0x%08x", nvm_ver.etk_id);
10639 }
10640
10641 /**
10642 * ixgbe_probe - Device Initialization Routine
10643 * @pdev: PCI device information struct
10644 * @ent: entry in ixgbe_pci_tbl
10645 *
10646 * Returns 0 on success, negative on failure
10647 *
10648 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
10649 * The OS initialization, configuring of the adapter private structure,
10650 * and a hardware reset occur.
10651 **/
ixgbe_probe(struct pci_dev * pdev,const struct pci_device_id * ent)10652 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10653 {
10654 struct net_device *netdev;
10655 struct ixgbe_adapter *adapter = NULL;
10656 struct ixgbe_hw *hw;
10657 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
10658 int i, err, pci_using_dac, expected_gts;
10659 unsigned int indices = MAX_TX_QUEUES;
10660 u8 part_str[IXGBE_PBANUM_LENGTH];
10661 bool disable_dev = false;
10662 #ifdef IXGBE_FCOE
10663 u16 device_caps;
10664 #endif
10665 u32 eec;
10666
10667 /* Catch broken hardware that put the wrong VF device ID in
10668 * the PCIe SR-IOV capability.
10669 */
10670 if (pdev->is_virtfn) {
10671 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
10672 pci_name(pdev), pdev->vendor, pdev->device);
10673 return -EINVAL;
10674 }
10675
10676 err = pci_enable_device_mem(pdev);
10677 if (err)
10678 return err;
10679
10680 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
10681 pci_using_dac = 1;
10682 } else {
10683 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10684 if (err) {
10685 dev_err(&pdev->dev,
10686 "No usable DMA configuration, aborting\n");
10687 goto err_dma;
10688 }
10689 pci_using_dac = 0;
10690 }
10691
10692 err = pci_request_mem_regions(pdev, ixgbe_driver_name);
10693 if (err) {
10694 dev_err(&pdev->dev,
10695 "pci_request_selected_regions failed 0x%x\n", err);
10696 goto err_pci_reg;
10697 }
10698
10699 pci_enable_pcie_error_reporting(pdev);
10700
10701 pci_set_master(pdev);
10702 pci_save_state(pdev);
10703
10704 if (ii->mac == ixgbe_mac_82598EB) {
10705 #ifdef CONFIG_IXGBE_DCB
10706 /* 8 TC w/ 4 queues per TC */
10707 indices = 4 * MAX_TRAFFIC_CLASS;
10708 #else
10709 indices = IXGBE_MAX_RSS_INDICES;
10710 #endif
10711 }
10712
10713 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
10714 if (!netdev) {
10715 err = -ENOMEM;
10716 goto err_alloc_etherdev;
10717 }
10718
10719 SET_NETDEV_DEV(netdev, &pdev->dev);
10720
10721 adapter = netdev_priv(netdev);
10722
10723 adapter->netdev = netdev;
10724 adapter->pdev = pdev;
10725 hw = &adapter->hw;
10726 hw->back = adapter;
10727 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
10728
10729 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
10730 pci_resource_len(pdev, 0));
10731 adapter->io_addr = hw->hw_addr;
10732 if (!hw->hw_addr) {
10733 err = -EIO;
10734 goto err_ioremap;
10735 }
10736
10737 netdev->netdev_ops = &ixgbe_netdev_ops;
10738 ixgbe_set_ethtool_ops(netdev);
10739 netdev->watchdog_timeo = 5 * HZ;
10740 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
10741
10742 /* Setup hw api */
10743 hw->mac.ops = *ii->mac_ops;
10744 hw->mac.type = ii->mac;
10745 hw->mvals = ii->mvals;
10746 if (ii->link_ops)
10747 hw->link.ops = *ii->link_ops;
10748
10749 /* EEPROM */
10750 hw->eeprom.ops = *ii->eeprom_ops;
10751 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
10752 if (ixgbe_removed(hw->hw_addr)) {
10753 err = -EIO;
10754 goto err_ioremap;
10755 }
10756 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
10757 if (!(eec & BIT(8)))
10758 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
10759
10760 /* PHY */
10761 hw->phy.ops = *ii->phy_ops;
10762 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
10763 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
10764 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
10765 hw->phy.mdio.mmds = 0;
10766 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10767 hw->phy.mdio.dev = netdev;
10768 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
10769 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
10770
10771 /* setup the private structure */
10772 err = ixgbe_sw_init(adapter, ii);
10773 if (err)
10774 goto err_sw_init;
10775
10776 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
10777 adapter->flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF;
10778
10779 switch (adapter->hw.mac.type) {
10780 case ixgbe_mac_X550:
10781 case ixgbe_mac_X550EM_x:
10782 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550;
10783 break;
10784 case ixgbe_mac_x550em_a:
10785 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a;
10786 break;
10787 default:
10788 break;
10789 }
10790
10791 /* Make sure the SWFW semaphore is in a valid state */
10792 if (hw->mac.ops.init_swfw_sync)
10793 hw->mac.ops.init_swfw_sync(hw);
10794
10795 /* Make it possible the adapter to be woken up via WOL */
10796 switch (adapter->hw.mac.type) {
10797 case ixgbe_mac_82599EB:
10798 case ixgbe_mac_X540:
10799 case ixgbe_mac_X550:
10800 case ixgbe_mac_X550EM_x:
10801 case ixgbe_mac_x550em_a:
10802 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
10803 break;
10804 default:
10805 break;
10806 }
10807
10808 /*
10809 * If there is a fan on this device and it has failed log the
10810 * failure.
10811 */
10812 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
10813 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
10814 if (esdp & IXGBE_ESDP_SDP1)
10815 e_crit(probe, "Fan has stopped, replace the adapter\n");
10816 }
10817
10818 if (allow_unsupported_sfp)
10819 hw->allow_unsupported_sfp = allow_unsupported_sfp;
10820
10821 /* reset_hw fills in the perm_addr as well */
10822 hw->phy.reset_if_overtemp = true;
10823 err = hw->mac.ops.reset_hw(hw);
10824 hw->phy.reset_if_overtemp = false;
10825 ixgbe_set_eee_capable(adapter);
10826 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
10827 err = 0;
10828 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
10829 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
10830 e_dev_err("Reload the driver after installing a supported module.\n");
10831 goto err_sw_init;
10832 } else if (err) {
10833 e_dev_err("HW Init failed: %d\n", err);
10834 goto err_sw_init;
10835 }
10836
10837 #ifdef CONFIG_PCI_IOV
10838 /* SR-IOV not supported on the 82598 */
10839 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
10840 goto skip_sriov;
10841 /* Mailbox */
10842 ixgbe_init_mbx_params_pf(hw);
10843 hw->mbx.ops = ii->mbx_ops;
10844 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
10845 ixgbe_enable_sriov(adapter, max_vfs);
10846 skip_sriov:
10847
10848 #endif
10849 netdev->features = NETIF_F_SG |
10850 NETIF_F_TSO |
10851 NETIF_F_TSO6 |
10852 NETIF_F_RXHASH |
10853 NETIF_F_RXCSUM |
10854 NETIF_F_HW_CSUM;
10855
10856 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
10857 NETIF_F_GSO_GRE_CSUM | \
10858 NETIF_F_GSO_IPXIP4 | \
10859 NETIF_F_GSO_IPXIP6 | \
10860 NETIF_F_GSO_UDP_TUNNEL | \
10861 NETIF_F_GSO_UDP_TUNNEL_CSUM)
10862
10863 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
10864 netdev->features |= NETIF_F_GSO_PARTIAL |
10865 IXGBE_GSO_PARTIAL_FEATURES;
10866
10867 if (hw->mac.type >= ixgbe_mac_82599EB)
10868 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
10869
10870 #ifdef CONFIG_IXGBE_IPSEC
10871 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \
10872 NETIF_F_HW_ESP_TX_CSUM | \
10873 NETIF_F_GSO_ESP)
10874
10875 if (adapter->ipsec)
10876 netdev->features |= IXGBE_ESP_FEATURES;
10877 #endif
10878 /* copy netdev features into list of user selectable features */
10879 netdev->hw_features |= netdev->features |
10880 NETIF_F_HW_VLAN_CTAG_FILTER |
10881 NETIF_F_HW_VLAN_CTAG_RX |
10882 NETIF_F_HW_VLAN_CTAG_TX |
10883 NETIF_F_RXALL |
10884 NETIF_F_HW_L2FW_DOFFLOAD;
10885
10886 if (hw->mac.type >= ixgbe_mac_82599EB)
10887 netdev->hw_features |= NETIF_F_NTUPLE |
10888 NETIF_F_HW_TC;
10889
10890 if (pci_using_dac)
10891 netdev->features |= NETIF_F_HIGHDMA;
10892
10893 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
10894 netdev->hw_enc_features |= netdev->vlan_features;
10895 netdev->mpls_features |= NETIF_F_SG |
10896 NETIF_F_TSO |
10897 NETIF_F_TSO6 |
10898 NETIF_F_HW_CSUM;
10899 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES;
10900
10901 /* set this bit last since it cannot be part of vlan_features */
10902 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
10903 NETIF_F_HW_VLAN_CTAG_RX |
10904 NETIF_F_HW_VLAN_CTAG_TX;
10905
10906 netdev->priv_flags |= IFF_UNICAST_FLT;
10907 netdev->priv_flags |= IFF_SUPP_NOFCS;
10908
10909 /* MTU range: 68 - 9710 */
10910 netdev->min_mtu = ETH_MIN_MTU;
10911 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
10912
10913 #ifdef CONFIG_IXGBE_DCB
10914 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
10915 netdev->dcbnl_ops = &ixgbe_dcbnl_ops;
10916 #endif
10917
10918 #ifdef IXGBE_FCOE
10919 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
10920 unsigned int fcoe_l;
10921
10922 if (hw->mac.ops.get_device_caps) {
10923 hw->mac.ops.get_device_caps(hw, &device_caps);
10924 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
10925 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
10926 }
10927
10928
10929 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
10930 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
10931
10932 netdev->features |= NETIF_F_FSO |
10933 NETIF_F_FCOE_CRC;
10934
10935 netdev->vlan_features |= NETIF_F_FSO |
10936 NETIF_F_FCOE_CRC |
10937 NETIF_F_FCOE_MTU;
10938 }
10939 #endif /* IXGBE_FCOE */
10940 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
10941 netdev->hw_features |= NETIF_F_LRO;
10942 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
10943 netdev->features |= NETIF_F_LRO;
10944
10945 if (ixgbe_check_fw_error(adapter)) {
10946 err = -EIO;
10947 goto err_sw_init;
10948 }
10949
10950 /* make sure the EEPROM is good */
10951 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
10952 e_dev_err("The EEPROM Checksum Is Not Valid\n");
10953 err = -EIO;
10954 goto err_sw_init;
10955 }
10956
10957 eth_platform_get_mac_address(&adapter->pdev->dev,
10958 adapter->hw.mac.perm_addr);
10959
10960 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
10961
10962 if (!is_valid_ether_addr(netdev->dev_addr)) {
10963 e_dev_err("invalid MAC address\n");
10964 err = -EIO;
10965 goto err_sw_init;
10966 }
10967
10968 /* Set hw->mac.addr to permanent MAC address */
10969 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
10970 ixgbe_mac_set_default_filter(adapter);
10971
10972 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0);
10973
10974 if (ixgbe_removed(hw->hw_addr)) {
10975 err = -EIO;
10976 goto err_sw_init;
10977 }
10978 INIT_WORK(&adapter->service_task, ixgbe_service_task);
10979 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
10980 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
10981
10982 err = ixgbe_init_interrupt_scheme(adapter);
10983 if (err)
10984 goto err_sw_init;
10985
10986 for (i = 0; i < adapter->num_rx_queues; i++)
10987 u64_stats_init(&adapter->rx_ring[i]->syncp);
10988 for (i = 0; i < adapter->num_tx_queues; i++)
10989 u64_stats_init(&adapter->tx_ring[i]->syncp);
10990 for (i = 0; i < adapter->num_xdp_queues; i++)
10991 u64_stats_init(&adapter->xdp_ring[i]->syncp);
10992
10993 /* WOL not supported for all devices */
10994 adapter->wol = 0;
10995 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
10996 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
10997 pdev->subsystem_device);
10998 if (hw->wol_enabled)
10999 adapter->wol = IXGBE_WUFC_MAG;
11000
11001 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
11002
11003 /* save off EEPROM version number */
11004 ixgbe_set_fw_version(adapter);
11005
11006 /* pick up the PCI bus settings for reporting later */
11007 if (ixgbe_pcie_from_parent(hw))
11008 ixgbe_get_parent_bus_info(adapter);
11009 else
11010 hw->mac.ops.get_bus_info(hw);
11011
11012 /* calculate the expected PCIe bandwidth required for optimal
11013 * performance. Note that some older parts will never have enough
11014 * bandwidth due to being older generation PCIe parts. We clamp these
11015 * parts to ensure no warning is displayed if it can't be fixed.
11016 */
11017 switch (hw->mac.type) {
11018 case ixgbe_mac_82598EB:
11019 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
11020 break;
11021 default:
11022 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
11023 break;
11024 }
11025
11026 /* don't check link if we failed to enumerate functions */
11027 if (expected_gts > 0)
11028 ixgbe_check_minimum_link(adapter, expected_gts);
11029
11030 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
11031 if (err)
11032 strlcpy(part_str, "Unknown", sizeof(part_str));
11033 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
11034 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
11035 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
11036 part_str);
11037 else
11038 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
11039 hw->mac.type, hw->phy.type, part_str);
11040
11041 e_dev_info("%pM\n", netdev->dev_addr);
11042
11043 /* reset the hardware with the new settings */
11044 err = hw->mac.ops.start_hw(hw);
11045 if (err == IXGBE_ERR_EEPROM_VERSION) {
11046 /* We are running on a pre-production device, log a warning */
11047 e_dev_warn("This device is a pre-production adapter/LOM. "
11048 "Please be aware there may be issues associated "
11049 "with your hardware. If you are experiencing "
11050 "problems please contact your Intel or hardware "
11051 "representative who provided you with this "
11052 "hardware.\n");
11053 }
11054 strcpy(netdev->name, "eth%d");
11055 pci_set_drvdata(pdev, adapter);
11056 err = register_netdev(netdev);
11057 if (err)
11058 goto err_register;
11059
11060
11061 /* power down the optics for 82599 SFP+ fiber */
11062 if (hw->mac.ops.disable_tx_laser)
11063 hw->mac.ops.disable_tx_laser(hw);
11064
11065 /* carrier off reporting is important to ethtool even BEFORE open */
11066 netif_carrier_off(netdev);
11067
11068 #ifdef CONFIG_IXGBE_DCA
11069 if (dca_add_requester(&pdev->dev) == 0) {
11070 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
11071 ixgbe_setup_dca(adapter);
11072 }
11073 #endif
11074 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
11075 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
11076 for (i = 0; i < adapter->num_vfs; i++)
11077 ixgbe_vf_configuration(pdev, (i | 0x10000000));
11078 }
11079
11080 /* firmware requires driver version to be 0xFFFFFFFF
11081 * since os does not support feature
11082 */
11083 if (hw->mac.ops.set_fw_drv_ver)
11084 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF,
11085 sizeof(UTS_RELEASE) - 1,
11086 UTS_RELEASE);
11087
11088 /* add san mac addr to netdev */
11089 ixgbe_add_sanmac_netdev(netdev);
11090
11091 e_dev_info("%s\n", ixgbe_default_device_descr);
11092
11093 #ifdef CONFIG_IXGBE_HWMON
11094 if (ixgbe_sysfs_init(adapter))
11095 e_err(probe, "failed to allocate sysfs resources\n");
11096 #endif /* CONFIG_IXGBE_HWMON */
11097
11098 ixgbe_dbg_adapter_init(adapter);
11099
11100 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
11101 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
11102 hw->mac.ops.setup_link(hw,
11103 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
11104 true);
11105
11106 err = ixgbe_mii_bus_init(hw);
11107 if (err)
11108 goto err_netdev;
11109
11110 return 0;
11111
11112 err_netdev:
11113 unregister_netdev(netdev);
11114 err_register:
11115 ixgbe_release_hw_control(adapter);
11116 ixgbe_clear_interrupt_scheme(adapter);
11117 err_sw_init:
11118 ixgbe_disable_sriov(adapter);
11119 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
11120 iounmap(adapter->io_addr);
11121 kfree(adapter->jump_tables[0]);
11122 kfree(adapter->mac_table);
11123 kfree(adapter->rss_key);
11124 bitmap_free(adapter->af_xdp_zc_qps);
11125 err_ioremap:
11126 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
11127 free_netdev(netdev);
11128 err_alloc_etherdev:
11129 pci_disable_pcie_error_reporting(pdev);
11130 pci_release_mem_regions(pdev);
11131 err_pci_reg:
11132 err_dma:
11133 if (!adapter || disable_dev)
11134 pci_disable_device(pdev);
11135 return err;
11136 }
11137
11138 /**
11139 * ixgbe_remove - Device Removal Routine
11140 * @pdev: PCI device information struct
11141 *
11142 * ixgbe_remove is called by the PCI subsystem to alert the driver
11143 * that it should release a PCI device. The could be caused by a
11144 * Hot-Plug event, or because the driver is going to be removed from
11145 * memory.
11146 **/
ixgbe_remove(struct pci_dev * pdev)11147 static void ixgbe_remove(struct pci_dev *pdev)
11148 {
11149 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11150 struct net_device *netdev;
11151 bool disable_dev;
11152 int i;
11153
11154 /* if !adapter then we already cleaned up in probe */
11155 if (!adapter)
11156 return;
11157
11158 netdev = adapter->netdev;
11159 ixgbe_dbg_adapter_exit(adapter);
11160
11161 set_bit(__IXGBE_REMOVING, &adapter->state);
11162 cancel_work_sync(&adapter->service_task);
11163
11164 if (adapter->mii_bus)
11165 mdiobus_unregister(adapter->mii_bus);
11166
11167 #ifdef CONFIG_IXGBE_DCA
11168 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
11169 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
11170 dca_remove_requester(&pdev->dev);
11171 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
11172 IXGBE_DCA_CTRL_DCA_DISABLE);
11173 }
11174
11175 #endif
11176 #ifdef CONFIG_IXGBE_HWMON
11177 ixgbe_sysfs_exit(adapter);
11178 #endif /* CONFIG_IXGBE_HWMON */
11179
11180 /* remove the added san mac */
11181 ixgbe_del_sanmac_netdev(netdev);
11182
11183 #ifdef CONFIG_PCI_IOV
11184 ixgbe_disable_sriov(adapter);
11185 #endif
11186 if (netdev->reg_state == NETREG_REGISTERED)
11187 unregister_netdev(netdev);
11188
11189 ixgbe_stop_ipsec_offload(adapter);
11190 ixgbe_clear_interrupt_scheme(adapter);
11191
11192 ixgbe_release_hw_control(adapter);
11193
11194 #ifdef CONFIG_DCB
11195 kfree(adapter->ixgbe_ieee_pfc);
11196 kfree(adapter->ixgbe_ieee_ets);
11197
11198 #endif
11199 iounmap(adapter->io_addr);
11200 pci_release_mem_regions(pdev);
11201
11202 e_dev_info("complete\n");
11203
11204 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
11205 if (adapter->jump_tables[i]) {
11206 kfree(adapter->jump_tables[i]->input);
11207 kfree(adapter->jump_tables[i]->mask);
11208 }
11209 kfree(adapter->jump_tables[i]);
11210 }
11211
11212 kfree(adapter->mac_table);
11213 kfree(adapter->rss_key);
11214 bitmap_free(adapter->af_xdp_zc_qps);
11215 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
11216 free_netdev(netdev);
11217
11218 pci_disable_pcie_error_reporting(pdev);
11219
11220 if (disable_dev)
11221 pci_disable_device(pdev);
11222 }
11223
11224 /**
11225 * ixgbe_io_error_detected - called when PCI error is detected
11226 * @pdev: Pointer to PCI device
11227 * @state: The current pci connection state
11228 *
11229 * This function is called after a PCI bus error affecting
11230 * this device has been detected.
11231 */
ixgbe_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)11232 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
11233 pci_channel_state_t state)
11234 {
11235 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11236 struct net_device *netdev = adapter->netdev;
11237
11238 #ifdef CONFIG_PCI_IOV
11239 struct ixgbe_hw *hw = &adapter->hw;
11240 struct pci_dev *bdev, *vfdev;
11241 u32 dw0, dw1, dw2, dw3;
11242 int vf, pos;
11243 u16 req_id, pf_func;
11244
11245 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
11246 adapter->num_vfs == 0)
11247 goto skip_bad_vf_detection;
11248
11249 bdev = pdev->bus->self;
11250 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
11251 bdev = bdev->bus->self;
11252
11253 if (!bdev)
11254 goto skip_bad_vf_detection;
11255
11256 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
11257 if (!pos)
11258 goto skip_bad_vf_detection;
11259
11260 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
11261 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
11262 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
11263 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
11264 if (ixgbe_removed(hw->hw_addr))
11265 goto skip_bad_vf_detection;
11266
11267 req_id = dw1 >> 16;
11268 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
11269 if (!(req_id & 0x0080))
11270 goto skip_bad_vf_detection;
11271
11272 pf_func = req_id & 0x01;
11273 if ((pf_func & 1) == (pdev->devfn & 1)) {
11274 unsigned int device_id;
11275
11276 vf = (req_id & 0x7F) >> 1;
11277 e_dev_err("VF %d has caused a PCIe error\n", vf);
11278 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
11279 "%8.8x\tdw3: %8.8x\n",
11280 dw0, dw1, dw2, dw3);
11281 switch (adapter->hw.mac.type) {
11282 case ixgbe_mac_82599EB:
11283 device_id = IXGBE_82599_VF_DEVICE_ID;
11284 break;
11285 case ixgbe_mac_X540:
11286 device_id = IXGBE_X540_VF_DEVICE_ID;
11287 break;
11288 case ixgbe_mac_X550:
11289 device_id = IXGBE_DEV_ID_X550_VF;
11290 break;
11291 case ixgbe_mac_X550EM_x:
11292 device_id = IXGBE_DEV_ID_X550EM_X_VF;
11293 break;
11294 case ixgbe_mac_x550em_a:
11295 device_id = IXGBE_DEV_ID_X550EM_A_VF;
11296 break;
11297 default:
11298 device_id = 0;
11299 break;
11300 }
11301
11302 /* Find the pci device of the offending VF */
11303 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
11304 while (vfdev) {
11305 if (vfdev->devfn == (req_id & 0xFF))
11306 break;
11307 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
11308 device_id, vfdev);
11309 }
11310 /*
11311 * There's a slim chance the VF could have been hot plugged,
11312 * so if it is no longer present we don't need to issue the
11313 * VFLR. Just clean up the AER in that case.
11314 */
11315 if (vfdev) {
11316 pcie_flr(vfdev);
11317 /* Free device reference count */
11318 pci_dev_put(vfdev);
11319 }
11320 }
11321
11322 /*
11323 * Even though the error may have occurred on the other port
11324 * we still need to increment the vf error reference count for
11325 * both ports because the I/O resume function will be called
11326 * for both of them.
11327 */
11328 adapter->vferr_refcount++;
11329
11330 return PCI_ERS_RESULT_RECOVERED;
11331
11332 skip_bad_vf_detection:
11333 #endif /* CONFIG_PCI_IOV */
11334 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
11335 return PCI_ERS_RESULT_DISCONNECT;
11336
11337 if (!netif_device_present(netdev))
11338 return PCI_ERS_RESULT_DISCONNECT;
11339
11340 rtnl_lock();
11341 netif_device_detach(netdev);
11342
11343 if (netif_running(netdev))
11344 ixgbe_close_suspend(adapter);
11345
11346 if (state == pci_channel_io_perm_failure) {
11347 rtnl_unlock();
11348 return PCI_ERS_RESULT_DISCONNECT;
11349 }
11350
11351 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
11352 pci_disable_device(pdev);
11353 rtnl_unlock();
11354
11355 /* Request a slot reset. */
11356 return PCI_ERS_RESULT_NEED_RESET;
11357 }
11358
11359 /**
11360 * ixgbe_io_slot_reset - called after the pci bus has been reset.
11361 * @pdev: Pointer to PCI device
11362 *
11363 * Restart the card from scratch, as if from a cold-boot.
11364 */
ixgbe_io_slot_reset(struct pci_dev * pdev)11365 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
11366 {
11367 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11368 pci_ers_result_t result;
11369
11370 if (pci_enable_device_mem(pdev)) {
11371 e_err(probe, "Cannot re-enable PCI device after reset.\n");
11372 result = PCI_ERS_RESULT_DISCONNECT;
11373 } else {
11374 smp_mb__before_atomic();
11375 clear_bit(__IXGBE_DISABLED, &adapter->state);
11376 adapter->hw.hw_addr = adapter->io_addr;
11377 pci_set_master(pdev);
11378 pci_restore_state(pdev);
11379 pci_save_state(pdev);
11380
11381 pci_wake_from_d3(pdev, false);
11382
11383 ixgbe_reset(adapter);
11384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
11385 result = PCI_ERS_RESULT_RECOVERED;
11386 }
11387
11388 return result;
11389 }
11390
11391 /**
11392 * ixgbe_io_resume - called when traffic can start flowing again.
11393 * @pdev: Pointer to PCI device
11394 *
11395 * This callback is called when the error recovery driver tells us that
11396 * its OK to resume normal operation.
11397 */
ixgbe_io_resume(struct pci_dev * pdev)11398 static void ixgbe_io_resume(struct pci_dev *pdev)
11399 {
11400 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11401 struct net_device *netdev = adapter->netdev;
11402
11403 #ifdef CONFIG_PCI_IOV
11404 if (adapter->vferr_refcount) {
11405 e_info(drv, "Resuming after VF err\n");
11406 adapter->vferr_refcount--;
11407 return;
11408 }
11409
11410 #endif
11411 rtnl_lock();
11412 if (netif_running(netdev))
11413 ixgbe_open(netdev);
11414
11415 netif_device_attach(netdev);
11416 rtnl_unlock();
11417 }
11418
11419 static const struct pci_error_handlers ixgbe_err_handler = {
11420 .error_detected = ixgbe_io_error_detected,
11421 .slot_reset = ixgbe_io_slot_reset,
11422 .resume = ixgbe_io_resume,
11423 };
11424
11425 static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume);
11426
11427 static struct pci_driver ixgbe_driver = {
11428 .name = ixgbe_driver_name,
11429 .id_table = ixgbe_pci_tbl,
11430 .probe = ixgbe_probe,
11431 .remove = ixgbe_remove,
11432 .driver.pm = &ixgbe_pm_ops,
11433 .shutdown = ixgbe_shutdown,
11434 .sriov_configure = ixgbe_pci_sriov_configure,
11435 .err_handler = &ixgbe_err_handler
11436 };
11437
11438 /**
11439 * ixgbe_init_module - Driver Registration Routine
11440 *
11441 * ixgbe_init_module is the first routine called when the driver is
11442 * loaded. All it does is register with the PCI subsystem.
11443 **/
ixgbe_init_module(void)11444 static int __init ixgbe_init_module(void)
11445 {
11446 int ret;
11447 pr_info("%s\n", ixgbe_driver_string);
11448 pr_info("%s\n", ixgbe_copyright);
11449
11450 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
11451 if (!ixgbe_wq) {
11452 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
11453 return -ENOMEM;
11454 }
11455
11456 ixgbe_dbg_init();
11457
11458 ret = pci_register_driver(&ixgbe_driver);
11459 if (ret) {
11460 destroy_workqueue(ixgbe_wq);
11461 ixgbe_dbg_exit();
11462 return ret;
11463 }
11464
11465 #ifdef CONFIG_IXGBE_DCA
11466 dca_register_notify(&dca_notifier);
11467 #endif
11468
11469 return 0;
11470 }
11471
11472 module_init(ixgbe_init_module);
11473
11474 /**
11475 * ixgbe_exit_module - Driver Exit Cleanup Routine
11476 *
11477 * ixgbe_exit_module is called just before the driver is removed
11478 * from memory.
11479 **/
ixgbe_exit_module(void)11480 static void __exit ixgbe_exit_module(void)
11481 {
11482 #ifdef CONFIG_IXGBE_DCA
11483 dca_unregister_notify(&dca_notifier);
11484 #endif
11485 pci_unregister_driver(&ixgbe_driver);
11486
11487 ixgbe_dbg_exit();
11488 if (ixgbe_wq) {
11489 destroy_workqueue(ixgbe_wq);
11490 ixgbe_wq = NULL;
11491 }
11492 }
11493
11494 #ifdef CONFIG_IXGBE_DCA
ixgbe_notify_dca(struct notifier_block * nb,unsigned long event,void * p)11495 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
11496 void *p)
11497 {
11498 int ret_val;
11499
11500 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
11501 __ixgbe_notify_dca);
11502
11503 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
11504 }
11505
11506 #endif /* CONFIG_IXGBE_DCA */
11507
11508 module_exit(ixgbe_exit_module);
11509
11510 /* ixgbe_main.c */
11511