1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2008 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI program scan utility.
31 * Used to determine which registers and instructions are used by a shader.
32 *
33 * Authors: Brian Paul
34 */
35
36
37 #include "util/u_debug.h"
38 #include "util/u_math.h"
39 #include "util/u_memory.h"
40 #include "util/u_prim.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_scan.h"
45
46
47 static bool
is_memory_file(unsigned file)48 is_memory_file(unsigned file)
49 {
50 return file == TGSI_FILE_SAMPLER ||
51 file == TGSI_FILE_SAMPLER_VIEW ||
52 file == TGSI_FILE_IMAGE ||
53 file == TGSI_FILE_BUFFER ||
54 file == TGSI_FILE_HW_ATOMIC;
55 }
56
57
58 static bool
is_mem_query_inst(enum tgsi_opcode opcode)59 is_mem_query_inst(enum tgsi_opcode opcode)
60 {
61 return opcode == TGSI_OPCODE_RESQ ||
62 opcode == TGSI_OPCODE_TXQ ||
63 opcode == TGSI_OPCODE_TXQS ||
64 opcode == TGSI_OPCODE_LODQ;
65 }
66
67 /**
68 * Is the opcode a "true" texture instruction which samples from a
69 * texture map?
70 */
71 static bool
is_texture_inst(enum tgsi_opcode opcode)72 is_texture_inst(enum tgsi_opcode opcode)
73 {
74 return (!is_mem_query_inst(opcode) &&
75 tgsi_get_opcode_info(opcode)->is_tex);
76 }
77
78
79 /**
80 * Is the opcode an instruction which computes a derivative explicitly or
81 * implicitly?
82 */
83 static bool
computes_derivative(enum tgsi_opcode opcode)84 computes_derivative(enum tgsi_opcode opcode)
85 {
86 if (tgsi_get_opcode_info(opcode)->is_tex) {
87 return opcode != TGSI_OPCODE_TG4 &&
88 opcode != TGSI_OPCODE_TXD &&
89 opcode != TGSI_OPCODE_TXF &&
90 opcode != TGSI_OPCODE_TXF_LZ &&
91 opcode != TGSI_OPCODE_TEX_LZ &&
92 opcode != TGSI_OPCODE_TXL &&
93 opcode != TGSI_OPCODE_TXL2 &&
94 opcode != TGSI_OPCODE_TXQ &&
95 opcode != TGSI_OPCODE_TXQS;
96 }
97
98 return opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE ||
99 opcode == TGSI_OPCODE_DDY || opcode == TGSI_OPCODE_DDY_FINE ||
100 opcode == TGSI_OPCODE_SAMPLE ||
101 opcode == TGSI_OPCODE_SAMPLE_B ||
102 opcode == TGSI_OPCODE_SAMPLE_C;
103 }
104
105
106 static void
scan_src_operand(struct tgsi_shader_info * info,const struct tgsi_full_instruction * fullinst,const struct tgsi_full_src_register * src,unsigned src_index,unsigned usage_mask_after_swizzle,bool is_interp_instruction,bool * is_mem_inst)107 scan_src_operand(struct tgsi_shader_info *info,
108 const struct tgsi_full_instruction *fullinst,
109 const struct tgsi_full_src_register *src,
110 unsigned src_index,
111 unsigned usage_mask_after_swizzle,
112 bool is_interp_instruction,
113 bool *is_mem_inst)
114 {
115 int ind = src->Register.Index;
116
117 if (info->processor == PIPE_SHADER_COMPUTE &&
118 src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
119 unsigned name, mask;
120
121 name = info->system_value_semantic_name[src->Register.Index];
122
123 switch (name) {
124 case TGSI_SEMANTIC_THREAD_ID:
125 case TGSI_SEMANTIC_BLOCK_ID:
126 mask = usage_mask_after_swizzle & TGSI_WRITEMASK_XYZ;
127 while (mask) {
128 unsigned i = u_bit_scan(&mask);
129
130 if (name == TGSI_SEMANTIC_THREAD_ID)
131 info->uses_thread_id[i] = true;
132 else
133 info->uses_block_id[i] = true;
134 }
135 break;
136 case TGSI_SEMANTIC_BLOCK_SIZE:
137 /* The block size is translated to IMM with a fixed block size. */
138 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
139 info->uses_block_size = true;
140 break;
141 case TGSI_SEMANTIC_GRID_SIZE:
142 info->uses_grid_size = true;
143 break;
144 }
145 }
146
147 /* Mark which inputs are effectively used */
148 if (src->Register.File == TGSI_FILE_INPUT) {
149 if (src->Register.Indirect) {
150 for (ind = 0; ind < info->num_inputs; ++ind) {
151 info->input_usage_mask[ind] |= usage_mask_after_swizzle;
152 }
153 } else {
154 assert(ind >= 0);
155 assert(ind < PIPE_MAX_SHADER_INPUTS);
156 info->input_usage_mask[ind] |= usage_mask_after_swizzle;
157 }
158
159 if (info->processor == PIPE_SHADER_FRAGMENT) {
160 unsigned name, index, input;
161
162 if (src->Register.Indirect && src->Indirect.ArrayID)
163 input = info->input_array_first[src->Indirect.ArrayID];
164 else
165 input = src->Register.Index;
166
167 name = info->input_semantic_name[input];
168 index = info->input_semantic_index[input];
169
170 if (name == TGSI_SEMANTIC_POSITION &&
171 usage_mask_after_swizzle & TGSI_WRITEMASK_Z)
172 info->reads_z = true;
173
174 if (name == TGSI_SEMANTIC_COLOR)
175 info->colors_read |= usage_mask_after_swizzle << (index * 4);
176
177 /* Process only interpolated varyings. Don't include POSITION.
178 * Don't include integer varyings, because they are not
179 * interpolated. Don't process inputs interpolated by INTERP
180 * opcodes. Those are tracked separately.
181 */
182 if ((!is_interp_instruction || src_index != 0) &&
183 (name == TGSI_SEMANTIC_GENERIC ||
184 name == TGSI_SEMANTIC_TEXCOORD ||
185 name == TGSI_SEMANTIC_COLOR ||
186 name == TGSI_SEMANTIC_BCOLOR ||
187 name == TGSI_SEMANTIC_FOG ||
188 name == TGSI_SEMANTIC_CLIPDIST)) {
189 switch (info->input_interpolate[input]) {
190 case TGSI_INTERPOLATE_COLOR:
191 case TGSI_INTERPOLATE_PERSPECTIVE:
192 switch (info->input_interpolate_loc[input]) {
193 case TGSI_INTERPOLATE_LOC_CENTER:
194 info->uses_persp_center = TRUE;
195 break;
196 case TGSI_INTERPOLATE_LOC_CENTROID:
197 info->uses_persp_centroid = TRUE;
198 break;
199 case TGSI_INTERPOLATE_LOC_SAMPLE:
200 info->uses_persp_sample = TRUE;
201 break;
202 }
203 break;
204 case TGSI_INTERPOLATE_LINEAR:
205 switch (info->input_interpolate_loc[input]) {
206 case TGSI_INTERPOLATE_LOC_CENTER:
207 info->uses_linear_center = TRUE;
208 break;
209 case TGSI_INTERPOLATE_LOC_CENTROID:
210 info->uses_linear_centroid = TRUE;
211 break;
212 case TGSI_INTERPOLATE_LOC_SAMPLE:
213 info->uses_linear_sample = TRUE;
214 break;
215 }
216 break;
217 /* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
218 }
219 }
220 }
221 }
222
223 if (info->processor == PIPE_SHADER_TESS_CTRL &&
224 src->Register.File == TGSI_FILE_OUTPUT) {
225 unsigned input;
226
227 if (src->Register.Indirect && src->Indirect.ArrayID)
228 input = info->output_array_first[src->Indirect.ArrayID];
229 else
230 input = src->Register.Index;
231
232 switch (info->output_semantic_name[input]) {
233 case TGSI_SEMANTIC_PATCH:
234 info->reads_perpatch_outputs = true;
235 break;
236 case TGSI_SEMANTIC_TESSINNER:
237 case TGSI_SEMANTIC_TESSOUTER:
238 info->reads_tessfactor_outputs = true;
239 break;
240 default:
241 info->reads_pervertex_outputs = true;
242 }
243 }
244
245 /* check for indirect register reads */
246 if (src->Register.Indirect) {
247 info->indirect_files |= (1 << src->Register.File);
248 info->indirect_files_read |= (1 << src->Register.File);
249
250 /* record indirect constant buffer indexing */
251 if (src->Register.File == TGSI_FILE_CONSTANT) {
252 if (src->Register.Dimension) {
253 if (src->Dimension.Indirect)
254 info->const_buffers_indirect = info->const_buffers_declared;
255 else
256 info->const_buffers_indirect |= 1u << src->Dimension.Index;
257 } else {
258 info->const_buffers_indirect |= 1;
259 }
260 }
261 }
262
263 if (src->Register.Dimension && src->Dimension.Indirect)
264 info->dim_indirect_files |= 1u << src->Register.File;
265
266 /* Texture samplers */
267 if (src->Register.File == TGSI_FILE_SAMPLER) {
268 const unsigned index = src->Register.Index;
269
270 assert(fullinst->Instruction.Texture);
271 assert(index < PIPE_MAX_SAMPLERS);
272
273 if (is_texture_inst(fullinst->Instruction.Opcode)) {
274 const unsigned target = fullinst->Texture.Texture;
275 assert(target < TGSI_TEXTURE_UNKNOWN);
276 /* for texture instructions, check that the texture instruction
277 * target matches the previous sampler view declaration (if there
278 * was one.)
279 */
280 if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
281 /* probably no sampler view declaration */
282 info->sampler_targets[index] = target;
283 } else {
284 /* Make sure the texture instruction's sampler/target info
285 * agrees with the sampler view declaration.
286 */
287 assert(info->sampler_targets[index] == target);
288 }
289 }
290 }
291
292 if (is_memory_file(src->Register.File) &&
293 !is_mem_query_inst(fullinst->Instruction.Opcode)) {
294 *is_mem_inst = true;
295
296 if (src->Register.File == TGSI_FILE_IMAGE &&
297 (fullinst->Memory.Texture == TGSI_TEXTURE_2D_MSAA ||
298 fullinst->Memory.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
299 if (src->Register.Indirect)
300 info->msaa_images_declared = info->images_declared;
301 else
302 info->msaa_images_declared |= 1 << src->Register.Index;
303 }
304
305 if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
306 info->writes_memory = TRUE;
307
308 if (src->Register.File == TGSI_FILE_IMAGE) {
309 if (src->Register.Indirect)
310 info->images_atomic = info->images_declared;
311 else
312 info->images_atomic |= 1 << src->Register.Index;
313 } else if (src->Register.File == TGSI_FILE_BUFFER) {
314 if (src->Register.Indirect)
315 info->shader_buffers_atomic = info->shader_buffers_declared;
316 else
317 info->shader_buffers_atomic |= 1 << src->Register.Index;
318 }
319 } else {
320 if (src->Register.File == TGSI_FILE_IMAGE) {
321 if (src->Register.Indirect)
322 info->images_load = info->images_declared;
323 else
324 info->images_load |= 1 << src->Register.Index;
325 } else if (src->Register.File == TGSI_FILE_BUFFER) {
326 if (src->Register.Indirect)
327 info->shader_buffers_load = info->shader_buffers_declared;
328 else
329 info->shader_buffers_load |= 1 << src->Register.Index;
330 }
331 }
332 }
333 }
334
335
336 static void
scan_instruction(struct tgsi_shader_info * info,const struct tgsi_full_instruction * fullinst,unsigned * current_depth)337 scan_instruction(struct tgsi_shader_info *info,
338 const struct tgsi_full_instruction *fullinst,
339 unsigned *current_depth)
340 {
341 unsigned i;
342 bool is_mem_inst = false;
343 bool is_interp_instruction = false;
344 unsigned sampler_src;
345
346 assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
347 info->opcode_count[fullinst->Instruction.Opcode]++;
348
349 switch (fullinst->Instruction.Opcode) {
350 case TGSI_OPCODE_IF:
351 case TGSI_OPCODE_UIF:
352 case TGSI_OPCODE_BGNLOOP:
353 (*current_depth)++;
354 info->max_depth = MAX2(info->max_depth, *current_depth);
355 break;
356 case TGSI_OPCODE_ENDIF:
357 case TGSI_OPCODE_ENDLOOP:
358 (*current_depth)--;
359 break;
360 case TGSI_OPCODE_TEX:
361 case TGSI_OPCODE_TEX_LZ:
362 case TGSI_OPCODE_TXB:
363 case TGSI_OPCODE_TXD:
364 case TGSI_OPCODE_TXL:
365 case TGSI_OPCODE_TXP:
366 case TGSI_OPCODE_TXQ:
367 case TGSI_OPCODE_TXQS:
368 case TGSI_OPCODE_TXF:
369 case TGSI_OPCODE_TXF_LZ:
370 case TGSI_OPCODE_TEX2:
371 case TGSI_OPCODE_TXB2:
372 case TGSI_OPCODE_TXL2:
373 case TGSI_OPCODE_TG4:
374 case TGSI_OPCODE_LODQ:
375 sampler_src = fullinst->Instruction.NumSrcRegs - 1;
376 if (fullinst->Src[sampler_src].Register.File != TGSI_FILE_SAMPLER)
377 info->uses_bindless_samplers = true;
378 break;
379 case TGSI_OPCODE_RESQ:
380 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File))
381 info->uses_bindless_images = true;
382 break;
383 case TGSI_OPCODE_LOAD:
384 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File)) {
385 info->uses_bindless_images = true;
386
387 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
388 info->uses_bindless_buffer_load = true;
389 else
390 info->uses_bindless_image_load = true;
391 }
392 break;
393 case TGSI_OPCODE_ATOMUADD:
394 case TGSI_OPCODE_ATOMXCHG:
395 case TGSI_OPCODE_ATOMCAS:
396 case TGSI_OPCODE_ATOMAND:
397 case TGSI_OPCODE_ATOMOR:
398 case TGSI_OPCODE_ATOMXOR:
399 case TGSI_OPCODE_ATOMUMIN:
400 case TGSI_OPCODE_ATOMUMAX:
401 case TGSI_OPCODE_ATOMIMIN:
402 case TGSI_OPCODE_ATOMIMAX:
403 case TGSI_OPCODE_ATOMFADD:
404 case TGSI_OPCODE_ATOMINC_WRAP:
405 case TGSI_OPCODE_ATOMDEC_WRAP:
406 if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File)) {
407 info->uses_bindless_images = true;
408
409 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
410 info->uses_bindless_buffer_atomic = true;
411 else
412 info->uses_bindless_image_atomic = true;
413 }
414 break;
415 case TGSI_OPCODE_STORE:
416 if (tgsi_is_bindless_image_file(fullinst->Dst[0].Register.File)) {
417 info->uses_bindless_images = true;
418
419 if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
420 info->uses_bindless_buffer_store = true;
421 else
422 info->uses_bindless_image_store = true;
423 }
424 break;
425 case TGSI_OPCODE_FBFETCH:
426 info->uses_fbfetch = true;
427 break;
428 default:
429 break;
430 }
431
432 if (fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID ||
433 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
434 fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
435 const struct tgsi_full_src_register *src0 = &fullinst->Src[0];
436 unsigned input;
437
438 is_interp_instruction = true;
439
440 if (src0->Register.Indirect && src0->Indirect.ArrayID)
441 input = info->input_array_first[src0->Indirect.ArrayID];
442 else
443 input = src0->Register.Index;
444
445 /* For the INTERP opcodes, the interpolation is always
446 * PERSPECTIVE unless LINEAR is specified.
447 */
448 switch (info->input_interpolate[input]) {
449 case TGSI_INTERPOLATE_COLOR:
450 case TGSI_INTERPOLATE_CONSTANT:
451 case TGSI_INTERPOLATE_PERSPECTIVE:
452 switch (fullinst->Instruction.Opcode) {
453 case TGSI_OPCODE_INTERP_CENTROID:
454 info->uses_persp_opcode_interp_centroid = TRUE;
455 break;
456 case TGSI_OPCODE_INTERP_OFFSET:
457 info->uses_persp_opcode_interp_offset = TRUE;
458 break;
459 case TGSI_OPCODE_INTERP_SAMPLE:
460 info->uses_persp_opcode_interp_sample = TRUE;
461 break;
462 }
463 break;
464
465 case TGSI_INTERPOLATE_LINEAR:
466 switch (fullinst->Instruction.Opcode) {
467 case TGSI_OPCODE_INTERP_CENTROID:
468 info->uses_linear_opcode_interp_centroid = TRUE;
469 break;
470 case TGSI_OPCODE_INTERP_OFFSET:
471 info->uses_linear_opcode_interp_offset = TRUE;
472 break;
473 case TGSI_OPCODE_INTERP_SAMPLE:
474 info->uses_linear_opcode_interp_sample = TRUE;
475 break;
476 }
477 break;
478 }
479 }
480
481 if ((fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
482 fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG) ||
483 fullinst->Instruction.Opcode == TGSI_OPCODE_DFMA ||
484 fullinst->Instruction.Opcode == TGSI_OPCODE_DDIV ||
485 fullinst->Instruction.Opcode == TGSI_OPCODE_D2U64 ||
486 fullinst->Instruction.Opcode == TGSI_OPCODE_D2I64 ||
487 fullinst->Instruction.Opcode == TGSI_OPCODE_U642D ||
488 fullinst->Instruction.Opcode == TGSI_OPCODE_I642D)
489 info->uses_doubles = TRUE;
490
491 for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
492 scan_src_operand(info, fullinst, &fullinst->Src[i], i,
493 tgsi_util_get_inst_usage_mask(fullinst, i),
494 is_interp_instruction, &is_mem_inst);
495
496 if (fullinst->Src[i].Register.Indirect) {
497 struct tgsi_full_src_register src = {{0}};
498
499 src.Register.File = fullinst->Src[i].Indirect.File;
500 src.Register.Index = fullinst->Src[i].Indirect.Index;
501
502 scan_src_operand(info, fullinst, &src, -1,
503 1 << fullinst->Src[i].Indirect.Swizzle,
504 false, NULL);
505 }
506
507 if (fullinst->Src[i].Register.Dimension &&
508 fullinst->Src[i].Dimension.Indirect) {
509 struct tgsi_full_src_register src = {{0}};
510
511 src.Register.File = fullinst->Src[i].DimIndirect.File;
512 src.Register.Index = fullinst->Src[i].DimIndirect.Index;
513
514 scan_src_operand(info, fullinst, &src, -1,
515 1 << fullinst->Src[i].DimIndirect.Swizzle,
516 false, NULL);
517 }
518 }
519
520 if (fullinst->Instruction.Texture) {
521 for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
522 struct tgsi_full_src_register src = {{0}};
523
524 src.Register.File = fullinst->TexOffsets[i].File;
525 src.Register.Index = fullinst->TexOffsets[i].Index;
526
527 /* The usage mask is suboptimal but should be safe. */
528 scan_src_operand(info, fullinst, &src, -1,
529 (1 << fullinst->TexOffsets[i].SwizzleX) |
530 (1 << fullinst->TexOffsets[i].SwizzleY) |
531 (1 << fullinst->TexOffsets[i].SwizzleZ),
532 false, &is_mem_inst);
533 }
534 }
535
536 /* check for indirect register writes */
537 for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
538 const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
539
540 if (dst->Register.Indirect) {
541 struct tgsi_full_src_register src = {{0}};
542
543 src.Register.File = dst->Indirect.File;
544 src.Register.Index = dst->Indirect.Index;
545
546 scan_src_operand(info, fullinst, &src, -1,
547 1 << dst->Indirect.Swizzle, false, NULL);
548
549 info->indirect_files |= (1 << dst->Register.File);
550 info->indirect_files_written |= (1 << dst->Register.File);
551 }
552
553 if (dst->Register.Dimension && dst->Dimension.Indirect) {
554 struct tgsi_full_src_register src = {{0}};
555
556 src.Register.File = dst->DimIndirect.File;
557 src.Register.Index = dst->DimIndirect.Index;
558
559 scan_src_operand(info, fullinst, &src, -1,
560 1 << dst->DimIndirect.Swizzle, false, NULL);
561
562 info->dim_indirect_files |= 1u << dst->Register.File;
563 }
564
565 if (is_memory_file(dst->Register.File)) {
566 assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
567
568 is_mem_inst = true;
569 info->writes_memory = TRUE;
570
571 if (dst->Register.File == TGSI_FILE_IMAGE) {
572 if (fullinst->Memory.Texture == TGSI_TEXTURE_2D_MSAA ||
573 fullinst->Memory.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
574 if (dst->Register.Indirect)
575 info->msaa_images_declared = info->images_declared;
576 else
577 info->msaa_images_declared |= 1 << dst->Register.Index;
578 }
579
580 if (dst->Register.Indirect)
581 info->images_store = info->images_declared;
582 else
583 info->images_store |= 1 << dst->Register.Index;
584 } else if (dst->Register.File == TGSI_FILE_BUFFER) {
585 if (dst->Register.Indirect)
586 info->shader_buffers_store = info->shader_buffers_declared;
587 else
588 info->shader_buffers_store |= 1 << dst->Register.Index;
589 }
590 }
591 }
592
593 if (is_mem_inst)
594 info->num_memory_instructions++;
595
596 if (computes_derivative(fullinst->Instruction.Opcode))
597 info->uses_derivatives = true;
598
599 info->num_instructions++;
600 }
601
602
603 static void
scan_declaration(struct tgsi_shader_info * info,const struct tgsi_full_declaration * fulldecl)604 scan_declaration(struct tgsi_shader_info *info,
605 const struct tgsi_full_declaration *fulldecl)
606 {
607 const uint file = fulldecl->Declaration.File;
608 const unsigned procType = info->processor;
609 uint reg;
610
611 if (fulldecl->Declaration.Array) {
612 unsigned array_id = fulldecl->Array.ArrayID;
613
614 switch (file) {
615 case TGSI_FILE_INPUT:
616 assert(array_id < ARRAY_SIZE(info->input_array_first));
617 info->input_array_first[array_id] = fulldecl->Range.First;
618 break;
619 case TGSI_FILE_OUTPUT:
620 assert(array_id < ARRAY_SIZE(info->output_array_first));
621 info->output_array_first[array_id] = fulldecl->Range.First;
622 break;
623 }
624 info->array_max[file] = MAX2(info->array_max[file], array_id);
625 }
626
627 for (reg = fulldecl->Range.First; reg <= fulldecl->Range.Last; reg++) {
628 unsigned semName = fulldecl->Semantic.Name;
629 unsigned semIndex = fulldecl->Semantic.Index +
630 (reg - fulldecl->Range.First);
631 int buffer;
632 unsigned index, target, type;
633
634 /*
635 * only first 32 regs will appear in this bitfield, if larger
636 * bits will wrap around.
637 */
638 info->file_mask[file] |= (1u << (reg & 31));
639 info->file_count[file]++;
640 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
641
642 switch (file) {
643 case TGSI_FILE_CONSTANT:
644 buffer = 0;
645
646 if (fulldecl->Declaration.Dimension)
647 buffer = fulldecl->Dim.Index2D;
648
649 info->const_file_max[buffer] =
650 MAX2(info->const_file_max[buffer], (int)reg);
651 info->const_buffers_declared |= 1u << buffer;
652 break;
653
654 case TGSI_FILE_IMAGE:
655 info->images_declared |= 1u << reg;
656 if (fulldecl->Image.Resource == TGSI_TEXTURE_BUFFER)
657 info->images_buffers |= 1 << reg;
658 break;
659
660 case TGSI_FILE_BUFFER:
661 info->shader_buffers_declared |= 1u << reg;
662 break;
663
664 case TGSI_FILE_HW_ATOMIC:
665 info->hw_atomic_declared |= 1u << reg;
666 break;
667
668 case TGSI_FILE_INPUT:
669 info->input_semantic_name[reg] = (ubyte) semName;
670 info->input_semantic_index[reg] = (ubyte) semIndex;
671 info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
672 info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
673
674 /* Vertex shaders can have inputs with holes between them. */
675 info->num_inputs = MAX2(info->num_inputs, reg + 1);
676
677 switch (semName) {
678 case TGSI_SEMANTIC_PRIMID:
679 info->uses_primid = true;
680 break;
681 case TGSI_SEMANTIC_POSITION:
682 info->reads_position = true;
683 break;
684 case TGSI_SEMANTIC_FACE:
685 info->uses_frontface = true;
686 break;
687 }
688 break;
689
690 case TGSI_FILE_SYSTEM_VALUE:
691 index = fulldecl->Range.First;
692
693 info->system_value_semantic_name[index] = semName;
694 info->num_system_values = MAX2(info->num_system_values, index + 1);
695
696 switch (semName) {
697 case TGSI_SEMANTIC_INSTANCEID:
698 info->uses_instanceid = TRUE;
699 break;
700 case TGSI_SEMANTIC_VERTEXID:
701 info->uses_vertexid = TRUE;
702 break;
703 case TGSI_SEMANTIC_VERTEXID_NOBASE:
704 info->uses_vertexid_nobase = TRUE;
705 break;
706 case TGSI_SEMANTIC_BASEVERTEX:
707 info->uses_basevertex = TRUE;
708 break;
709 case TGSI_SEMANTIC_DRAWID:
710 info->uses_drawid = TRUE;
711 break;
712 case TGSI_SEMANTIC_PRIMID:
713 info->uses_primid = TRUE;
714 break;
715 case TGSI_SEMANTIC_INVOCATIONID:
716 info->uses_invocationid = TRUE;
717 break;
718 case TGSI_SEMANTIC_POSITION:
719 info->reads_position = TRUE;
720 break;
721 case TGSI_SEMANTIC_FACE:
722 info->uses_frontface = TRUE;
723 break;
724 case TGSI_SEMANTIC_SAMPLEMASK:
725 info->reads_samplemask = TRUE;
726 break;
727 case TGSI_SEMANTIC_TESSINNER:
728 case TGSI_SEMANTIC_TESSOUTER:
729 info->reads_tess_factors = true;
730 break;
731 }
732 break;
733
734 case TGSI_FILE_OUTPUT:
735 info->output_semantic_name[reg] = (ubyte) semName;
736 info->output_semantic_index[reg] = (ubyte) semIndex;
737 info->output_usagemask[reg] |= fulldecl->Declaration.UsageMask;
738 info->num_outputs = MAX2(info->num_outputs, reg + 1);
739
740 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_X) {
741 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamX;
742 info->num_stream_output_components[fulldecl->Semantic.StreamX]++;
743 }
744 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Y) {
745 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamY << 2;
746 info->num_stream_output_components[fulldecl->Semantic.StreamY]++;
747 }
748 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_Z) {
749 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamZ << 4;
750 info->num_stream_output_components[fulldecl->Semantic.StreamZ]++;
751 }
752 if (fulldecl->Declaration.UsageMask & TGSI_WRITEMASK_W) {
753 info->output_streams[reg] |= (ubyte)fulldecl->Semantic.StreamW << 6;
754 info->num_stream_output_components[fulldecl->Semantic.StreamW]++;
755 }
756
757 switch (semName) {
758 case TGSI_SEMANTIC_PRIMID:
759 info->writes_primid = true;
760 break;
761 case TGSI_SEMANTIC_VIEWPORT_INDEX:
762 info->writes_viewport_index = true;
763 break;
764 case TGSI_SEMANTIC_LAYER:
765 info->writes_layer = true;
766 break;
767 case TGSI_SEMANTIC_PSIZE:
768 info->writes_psize = true;
769 break;
770 case TGSI_SEMANTIC_CLIPVERTEX:
771 info->writes_clipvertex = true;
772 break;
773 case TGSI_SEMANTIC_COLOR:
774 info->colors_written |= 1 << semIndex;
775 break;
776 case TGSI_SEMANTIC_STENCIL:
777 info->writes_stencil = true;
778 break;
779 case TGSI_SEMANTIC_SAMPLEMASK:
780 info->writes_samplemask = true;
781 break;
782 case TGSI_SEMANTIC_EDGEFLAG:
783 info->writes_edgeflag = true;
784 break;
785 case TGSI_SEMANTIC_POSITION:
786 if (procType == PIPE_SHADER_FRAGMENT)
787 info->writes_z = true;
788 else
789 info->writes_position = true;
790 break;
791 }
792 break;
793
794 case TGSI_FILE_SAMPLER:
795 STATIC_ASSERT(sizeof(info->samplers_declared) * 8 >= PIPE_MAX_SAMPLERS);
796 info->samplers_declared |= 1u << reg;
797 break;
798
799 case TGSI_FILE_SAMPLER_VIEW:
800 target = fulldecl->SamplerView.Resource;
801 type = fulldecl->SamplerView.ReturnTypeX;
802
803 assert(target < TGSI_TEXTURE_UNKNOWN);
804 if (info->sampler_targets[reg] == TGSI_TEXTURE_UNKNOWN) {
805 /* Save sampler target for this sampler index */
806 info->sampler_targets[reg] = target;
807 info->sampler_type[reg] = type;
808 } else {
809 /* if previously declared, make sure targets agree */
810 assert(info->sampler_targets[reg] == target);
811 assert(info->sampler_type[reg] == type);
812 }
813 break;
814 }
815 }
816 }
817
818
819 static void
scan_immediate(struct tgsi_shader_info * info)820 scan_immediate(struct tgsi_shader_info *info)
821 {
822 uint reg = info->immediate_count++;
823 uint file = TGSI_FILE_IMMEDIATE;
824
825 info->file_mask[file] |= (1 << reg);
826 info->file_count[file]++;
827 info->file_max[file] = MAX2(info->file_max[file], (int)reg);
828 }
829
830
831 static void
scan_property(struct tgsi_shader_info * info,const struct tgsi_full_property * fullprop)832 scan_property(struct tgsi_shader_info *info,
833 const struct tgsi_full_property *fullprop)
834 {
835 unsigned name = fullprop->Property.PropertyName;
836 unsigned value = fullprop->u[0].Data;
837
838 assert(name < ARRAY_SIZE(info->properties));
839 info->properties[name] = value;
840
841 switch (name) {
842 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
843 info->num_written_clipdistance = value;
844 info->clipdist_writemask |= (1 << value) - 1;
845 break;
846 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
847 info->num_written_culldistance = value;
848 info->culldist_writemask |= (1 << value) - 1;
849 break;
850 }
851 }
852
853
854 /**
855 * Scan the given TGSI shader to collect information such as number of
856 * registers used, special instructions used, etc.
857 * \return info the result of the scan
858 */
859 void
tgsi_scan_shader(const struct tgsi_token * tokens,struct tgsi_shader_info * info)860 tgsi_scan_shader(const struct tgsi_token *tokens,
861 struct tgsi_shader_info *info)
862 {
863 uint procType, i;
864 struct tgsi_parse_context parse;
865 unsigned current_depth = 0;
866
867 memset(info, 0, sizeof(*info));
868 for (i = 0; i < TGSI_FILE_COUNT; i++)
869 info->file_max[i] = -1;
870 for (i = 0; i < ARRAY_SIZE(info->const_file_max); i++)
871 info->const_file_max[i] = -1;
872 for (i = 0; i < ARRAY_SIZE(info->sampler_targets); i++)
873 info->sampler_targets[i] = TGSI_TEXTURE_UNKNOWN;
874
875 /**
876 ** Setup to begin parsing input shader
877 **/
878 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
879 debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
880 return;
881 }
882 procType = parse.FullHeader.Processor.Processor;
883 assert(procType == PIPE_SHADER_FRAGMENT ||
884 procType == PIPE_SHADER_VERTEX ||
885 procType == PIPE_SHADER_GEOMETRY ||
886 procType == PIPE_SHADER_TESS_CTRL ||
887 procType == PIPE_SHADER_TESS_EVAL ||
888 procType == PIPE_SHADER_COMPUTE);
889 info->processor = procType;
890 info->num_tokens = tgsi_num_tokens(parse.Tokens);
891
892 if (procType == PIPE_SHADER_GEOMETRY)
893 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
894
895 /**
896 ** Loop over incoming program tokens/instructions
897 */
898 while (!tgsi_parse_end_of_tokens(&parse)) {
899 tgsi_parse_token( &parse );
900
901 switch( parse.FullToken.Token.Type ) {
902 case TGSI_TOKEN_TYPE_INSTRUCTION:
903 scan_instruction(info, &parse.FullToken.FullInstruction,
904 ¤t_depth);
905 break;
906 case TGSI_TOKEN_TYPE_DECLARATION:
907 scan_declaration(info, &parse.FullToken.FullDeclaration);
908 break;
909 case TGSI_TOKEN_TYPE_IMMEDIATE:
910 scan_immediate(info);
911 break;
912 case TGSI_TOKEN_TYPE_PROPERTY:
913 scan_property(info, &parse.FullToken.FullProperty);
914 break;
915 default:
916 assert(!"Unexpected TGSI token type");
917 }
918 }
919
920 info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
921 info->opcode_count[TGSI_OPCODE_KILL]);
922
923 /* The dimensions of the IN decleration in geometry shader have
924 * to be deduced from the type of the input primitive.
925 */
926 if (procType == PIPE_SHADER_GEOMETRY) {
927 unsigned input_primitive =
928 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
929 int num_verts = u_vertices_per_prim(input_primitive);
930 int j;
931 info->file_count[TGSI_FILE_INPUT] = num_verts;
932 info->file_max[TGSI_FILE_INPUT] =
933 MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
934 for (j = 0; j < num_verts; ++j) {
935 info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
936 }
937 }
938
939 tgsi_parse_free(&parse);
940 }
941
942 /**
943 * Collect information about the arrays of a given register file.
944 *
945 * @param tokens TGSI shader
946 * @param file the register file to scan through
947 * @param max_array_id number of entries in @p arrays; should be equal to the
948 * highest array id, i.e. tgsi_shader_info::array_max[file].
949 * @param arrays info for array of each ID will be written to arrays[ID - 1].
950 */
951 void
tgsi_scan_arrays(const struct tgsi_token * tokens,unsigned file,unsigned max_array_id,struct tgsi_array_info * arrays)952 tgsi_scan_arrays(const struct tgsi_token *tokens,
953 unsigned file,
954 unsigned max_array_id,
955 struct tgsi_array_info *arrays)
956 {
957 struct tgsi_parse_context parse;
958
959 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
960 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
961 return;
962 }
963
964 memset(arrays, 0, sizeof(arrays[0]) * max_array_id);
965
966 while (!tgsi_parse_end_of_tokens(&parse)) {
967 struct tgsi_full_instruction *inst;
968
969 tgsi_parse_token(&parse);
970
971 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
972 struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
973
974 if (decl->Declaration.Array && decl->Declaration.File == file &&
975 decl->Array.ArrayID > 0 && decl->Array.ArrayID <= max_array_id) {
976 struct tgsi_array_info *array = &arrays[decl->Array.ArrayID - 1];
977 assert(!array->declared);
978 array->declared = true;
979 array->range = decl->Range;
980 }
981 }
982
983 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
984 continue;
985
986 inst = &parse.FullToken.FullInstruction;
987 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
988 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
989 if (dst->Register.File != file)
990 continue;
991
992 if (dst->Register.Indirect) {
993 if (dst->Indirect.ArrayID > 0 &&
994 dst->Indirect.ArrayID <= max_array_id) {
995 arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
996 } else {
997 /* Indirect writes without an ArrayID can write anywhere. */
998 for (unsigned j = 0; j < max_array_id; ++j)
999 arrays[j].writemask |= dst->Register.WriteMask;
1000 }
1001 } else {
1002 /* Check whether the write falls into any of the arrays anyway. */
1003 for (unsigned j = 0; j < max_array_id; ++j) {
1004 struct tgsi_array_info *array = &arrays[j];
1005 if (array->declared &&
1006 dst->Register.Index >= array->range.First &&
1007 dst->Register.Index <= array->range.Last)
1008 array->writemask |= dst->Register.WriteMask;
1009 }
1010 }
1011 }
1012 }
1013
1014 tgsi_parse_free(&parse);
1015
1016 return;
1017 }
1018
1019 static void
check_no_subroutines(const struct tgsi_full_instruction * inst)1020 check_no_subroutines(const struct tgsi_full_instruction *inst)
1021 {
1022 switch (inst->Instruction.Opcode) {
1023 case TGSI_OPCODE_BGNSUB:
1024 case TGSI_OPCODE_ENDSUB:
1025 case TGSI_OPCODE_CAL:
1026 unreachable("subroutines unhandled");
1027 }
1028 }
1029
1030 static unsigned
get_inst_tessfactor_writemask(const struct tgsi_shader_info * info,const struct tgsi_full_instruction * inst)1031 get_inst_tessfactor_writemask(const struct tgsi_shader_info *info,
1032 const struct tgsi_full_instruction *inst)
1033 {
1034 unsigned writemask = 0;
1035
1036 for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
1037 const struct tgsi_full_dst_register *dst = &inst->Dst[i];
1038
1039 if (dst->Register.File == TGSI_FILE_OUTPUT &&
1040 !dst->Register.Indirect) {
1041 unsigned name = info->output_semantic_name[dst->Register.Index];
1042
1043 if (name == TGSI_SEMANTIC_TESSINNER)
1044 writemask |= dst->Register.WriteMask;
1045 else if (name == TGSI_SEMANTIC_TESSOUTER)
1046 writemask |= dst->Register.WriteMask << 4;
1047 }
1048 }
1049 return writemask;
1050 }
1051
1052 static unsigned
get_block_tessfactor_writemask(const struct tgsi_shader_info * info,struct tgsi_parse_context * parse,unsigned end_opcode)1053 get_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1054 struct tgsi_parse_context *parse,
1055 unsigned end_opcode)
1056 {
1057 struct tgsi_full_instruction *inst;
1058 unsigned writemask = 0;
1059
1060 tgsi_parse_token(parse);
1061 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1062 inst = &parse->FullToken.FullInstruction;
1063 check_no_subroutines(inst);
1064
1065 while (inst->Instruction.Opcode != end_opcode) {
1066
1067 /* Recursively process nested blocks. */
1068 switch (inst->Instruction.Opcode) {
1069 case TGSI_OPCODE_IF:
1070 case TGSI_OPCODE_UIF:
1071 writemask |=
1072 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDIF);
1073 break;
1074
1075 case TGSI_OPCODE_BGNLOOP:
1076 writemask |=
1077 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1078 break;
1079
1080 case TGSI_OPCODE_BARRIER:
1081 unreachable("nested BARRIER is illegal");
1082 break;
1083
1084 default:
1085 writemask |= get_inst_tessfactor_writemask(info, inst);
1086 }
1087
1088 tgsi_parse_token(parse);
1089 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1090 inst = &parse->FullToken.FullInstruction;
1091 check_no_subroutines(inst);
1092 }
1093
1094 return writemask;
1095 }
1096
1097 static void
get_if_block_tessfactor_writemask(const struct tgsi_shader_info * info,struct tgsi_parse_context * parse,unsigned * upper_block_tf_writemask,unsigned * cond_block_tf_writemask)1098 get_if_block_tessfactor_writemask(const struct tgsi_shader_info *info,
1099 struct tgsi_parse_context *parse,
1100 unsigned *upper_block_tf_writemask,
1101 unsigned *cond_block_tf_writemask)
1102 {
1103 struct tgsi_full_instruction *inst;
1104 unsigned then_tessfactor_writemask = 0;
1105 unsigned else_tessfactor_writemask = 0;
1106 unsigned writemask;
1107 bool is_then = true;
1108
1109 tgsi_parse_token(parse);
1110 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1111 inst = &parse->FullToken.FullInstruction;
1112 check_no_subroutines(inst);
1113
1114 while (inst->Instruction.Opcode != TGSI_OPCODE_ENDIF) {
1115
1116 switch (inst->Instruction.Opcode) {
1117 case TGSI_OPCODE_ELSE:
1118 is_then = false;
1119 break;
1120
1121 /* Recursively process nested blocks. */
1122 case TGSI_OPCODE_IF:
1123 case TGSI_OPCODE_UIF:
1124 get_if_block_tessfactor_writemask(info, parse,
1125 is_then ? &then_tessfactor_writemask :
1126 &else_tessfactor_writemask,
1127 cond_block_tf_writemask);
1128 break;
1129
1130 case TGSI_OPCODE_BGNLOOP:
1131 *cond_block_tf_writemask |=
1132 get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
1133 break;
1134
1135 case TGSI_OPCODE_BARRIER:
1136 unreachable("nested BARRIER is illegal");
1137 break;
1138 default:
1139 /* Process an instruction in the current block. */
1140 writemask = get_inst_tessfactor_writemask(info, inst);
1141
1142 if (writemask) {
1143 if (is_then)
1144 then_tessfactor_writemask |= writemask;
1145 else
1146 else_tessfactor_writemask |= writemask;
1147 }
1148 }
1149
1150 tgsi_parse_token(parse);
1151 assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
1152 inst = &parse->FullToken.FullInstruction;
1153 check_no_subroutines(inst);
1154 }
1155
1156 if (then_tessfactor_writemask || else_tessfactor_writemask) {
1157 /* If both statements write the same tess factor channels,
1158 * we can say that the upper block writes them too. */
1159 *upper_block_tf_writemask |= then_tessfactor_writemask &
1160 else_tessfactor_writemask;
1161 *cond_block_tf_writemask |= then_tessfactor_writemask |
1162 else_tessfactor_writemask;
1163 }
1164 }
1165
1166 void
tgsi_scan_tess_ctrl(const struct tgsi_token * tokens,const struct tgsi_shader_info * info,struct tgsi_tessctrl_info * out)1167 tgsi_scan_tess_ctrl(const struct tgsi_token *tokens,
1168 const struct tgsi_shader_info *info,
1169 struct tgsi_tessctrl_info *out)
1170 {
1171 memset(out, 0, sizeof(*out));
1172
1173 if (info->processor != PIPE_SHADER_TESS_CTRL)
1174 return;
1175
1176 struct tgsi_parse_context parse;
1177 if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
1178 debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
1179 return;
1180 }
1181
1182 /* The pass works as follows:
1183 * If all codepaths write tess factors, we can say that all invocations
1184 * define tess factors.
1185 *
1186 * Each tess factor channel is tracked separately.
1187 */
1188 unsigned main_block_tf_writemask = 0; /* if main block writes tess factors */
1189 unsigned cond_block_tf_writemask = 0; /* if cond block writes tess factors */
1190
1191 /* Initial value = true. Here the pass will accumulate results from multiple
1192 * segments surrounded by barriers. If tess factors aren't written at all,
1193 * it's a shader bug and we don't care if this will be true.
1194 */
1195 out->tessfactors_are_def_in_all_invocs = true;
1196
1197 while (!tgsi_parse_end_of_tokens(&parse)) {
1198 tgsi_parse_token(&parse);
1199
1200 if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
1201 continue;
1202
1203 struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1204 check_no_subroutines(inst);
1205
1206 /* Process nested blocks. */
1207 switch (inst->Instruction.Opcode) {
1208 case TGSI_OPCODE_IF:
1209 case TGSI_OPCODE_UIF:
1210 get_if_block_tessfactor_writemask(info, &parse,
1211 &main_block_tf_writemask,
1212 &cond_block_tf_writemask);
1213 continue;
1214
1215 case TGSI_OPCODE_BGNLOOP:
1216 cond_block_tf_writemask |=
1217 get_block_tessfactor_writemask(info, &parse, TGSI_OPCODE_ENDLOOP);
1218 continue;
1219
1220 case TGSI_OPCODE_BARRIER:
1221 /* The following case must be prevented:
1222 * gl_TessLevelInner = ...;
1223 * barrier();
1224 * if (gl_InvocationID == 1)
1225 * gl_TessLevelInner = ...;
1226 *
1227 * If you consider disjoint code segments separated by barriers, each
1228 * such segment that writes tess factor channels should write the same
1229 * channels in all codepaths within that segment.
1230 */
1231 if (main_block_tf_writemask || cond_block_tf_writemask) {
1232 /* Accumulate the result: */
1233 out->tessfactors_are_def_in_all_invocs &=
1234 !(cond_block_tf_writemask & ~main_block_tf_writemask);
1235
1236 /* Analyze the next code segment from scratch. */
1237 main_block_tf_writemask = 0;
1238 cond_block_tf_writemask = 0;
1239 }
1240 continue;
1241 }
1242
1243 main_block_tf_writemask |= get_inst_tessfactor_writemask(info, inst);
1244 }
1245
1246 /* Accumulate the result for the last code segment separated by a barrier. */
1247 if (main_block_tf_writemask || cond_block_tf_writemask) {
1248 out->tessfactors_are_def_in_all_invocs &=
1249 !(cond_block_tf_writemask & ~main_block_tf_writemask);
1250 }
1251
1252 tgsi_parse_free(&parse);
1253 }
1254