1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <errno.h>
24 #include <xf86drm.h>
25 #include <nouveau_drm.h>
26 #include "util/format/u_format.h"
27 #include "util/format/u_format_s3tc.h"
28 #include "util/u_screen.h"
29 #include "pipe/p_screen.h"
30
31 #include "nv50_ir_driver.h"
32
33 #include "nv50/nv50_context.h"
34 #include "nv50/nv50_screen.h"
35
36 #include "nouveau_vp3_video.h"
37
38 #include "nv_object.xml.h"
39
40 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
41 #define LOCAL_WARPS_ALLOC 32
42 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
43 #define STACK_WARPS_ALLOC 32
44
45 #define THREADS_IN_WARP 32
46
47 static bool
nv50_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)48 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
49 enum pipe_format format,
50 enum pipe_texture_target target,
51 unsigned sample_count,
52 unsigned storage_sample_count,
53 unsigned bindings)
54 {
55 if (sample_count > 8)
56 return false;
57 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
58 return false;
59 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
60 return false;
61
62 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
63 return false;
64
65 /* Short-circuit the rest of the logic -- this is used by the gallium frontend
66 * to determine valid MS levels in a no-attachments scenario.
67 */
68 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
69 return true;
70
71 switch (format) {
72 case PIPE_FORMAT_Z16_UNORM:
73 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
74 return false;
75 break;
76 default:
77 break;
78 }
79
80 if (bindings & PIPE_BIND_LINEAR)
81 if (util_format_is_depth_or_stencil(format) ||
82 (target != PIPE_TEXTURE_1D &&
83 target != PIPE_TEXTURE_2D &&
84 target != PIPE_TEXTURE_RECT) ||
85 sample_count > 1)
86 return false;
87
88 /* shared is always supported */
89 bindings &= ~(PIPE_BIND_LINEAR |
90 PIPE_BIND_SHARED);
91
92 if (bindings & PIPE_BIND_INDEX_BUFFER) {
93 if (format != PIPE_FORMAT_R8_UINT &&
94 format != PIPE_FORMAT_R16_UINT &&
95 format != PIPE_FORMAT_R32_UINT)
96 return false;
97 bindings &= ~PIPE_BIND_INDEX_BUFFER;
98 }
99
100 return (( nv50_format_table[format].usage |
101 nv50_vertex_format[format].usage) & bindings) == bindings;
102 }
103
104 static int
nv50_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)105 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
106 {
107 struct nouveau_screen *screen = nouveau_screen(pscreen);
108 const uint16_t class_3d = screen->class_3d;
109 struct nouveau_device *dev = screen->device;
110 static bool debug_cap_printed[PIPE_CAP_LAST] = {};
111
112 switch (param) {
113 /* non-boolean caps */
114 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
115 return 8192;
116 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
117 return 12;
118 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
119 return 14;
120 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
121 return 512;
122 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
123 case PIPE_CAP_MIN_TEXEL_OFFSET:
124 return -8;
125 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
126 case PIPE_CAP_MAX_TEXEL_OFFSET:
127 return 7;
128 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
129 return 128 * 1024 * 1024;
130 case PIPE_CAP_GLSL_FEATURE_LEVEL:
131 return 330;
132 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
133 return 330;
134 case PIPE_CAP_ESSL_FEATURE_LEVEL:
135 return class_3d >= NVA3_3D_CLASS ? 310 : 300;
136 case PIPE_CAP_MAX_RENDER_TARGETS:
137 return 8;
138 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
139 return 1;
140 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
141 return NV50_MAX_GLOBALS - 1;
142 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
143 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
144 return 8;
145 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
146 return 4;
147 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
148 return 64;
149 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
150 return 4;
151 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
152 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
153 return 1024;
154 case PIPE_CAP_MAX_VERTEX_STREAMS:
155 return 1;
156 case PIPE_CAP_MAX_GS_INVOCATIONS:
157 return 0;
158 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
159 return 1 << 27;
160 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
161 return 2048;
162 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
163 return 2047;
164 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
165 return 256;
166 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
167 return 16; /* 256 for binding as RT, but that's not possible in GL */
168 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
169 return 256; /* the access limit is aligned to 256 */
170 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
171 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
172 case PIPE_CAP_MAX_VIEWPORTS:
173 return NV50_MAX_VIEWPORTS;
174 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
175 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
176 case PIPE_CAP_ENDIANNESS:
177 return PIPE_ENDIAN_LITTLE;
178 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
179 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
180 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
181 return NV50_MAX_WINDOW_RECTANGLES;
182 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
183 return 16 * 1024 * 1024;
184 case PIPE_CAP_MAX_VARYINGS:
185 return 15;
186 case PIPE_CAP_MAX_VERTEX_BUFFERS:
187 return 16;
188 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
189 return 512 * 1024; /* TODO: Investigate tuning this */
190 case PIPE_CAP_MAX_TEXTURE_MB:
191 return 0; /* TODO: use 1/2 of VRAM for this? */
192
193 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
194 case PIPE_CAP_SUPPORTED_PRIM_MODES:
195 return BITFIELD_MASK(PIPE_PRIM_MAX);
196
197 /* supported caps */
198 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
199 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
200 case PIPE_CAP_TEXTURE_SWIZZLE:
201 case PIPE_CAP_TEXTURE_SHADOW_MAP:
202 case PIPE_CAP_NPOT_TEXTURES:
203 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
204 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
205 case PIPE_CAP_ANISOTROPIC_FILTER:
206 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
207 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
208 case PIPE_CAP_DEPTH_CLIP_DISABLE:
209 case PIPE_CAP_POINT_SPRITE:
210 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
211 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
212 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
213 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
214 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
215 case PIPE_CAP_QUERY_TIMESTAMP:
216 case PIPE_CAP_QUERY_TIME_ELAPSED:
217 case PIPE_CAP_OCCLUSION_QUERY:
218 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
219 case PIPE_CAP_INDEP_BLEND_ENABLE:
220 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
221 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
222 case PIPE_CAP_POINT_COORD_ORIGIN_UPPER_LEFT:
223 case PIPE_CAP_PRIMITIVE_RESTART:
224 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
225 case PIPE_CAP_VS_INSTANCEID:
226 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
227 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
228 case PIPE_CAP_CONDITIONAL_RENDER:
229 case PIPE_CAP_TEXTURE_BARRIER:
230 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
231 case PIPE_CAP_START_INSTANCE:
232 case PIPE_CAP_USER_VERTEX_BUFFERS:
233 case PIPE_CAP_TEXTURE_MULTISAMPLE:
234 case PIPE_CAP_FS_FINE_DERIVATIVE:
235 case PIPE_CAP_SAMPLER_VIEW_TARGET:
236 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
237 case PIPE_CAP_CLIP_HALFZ:
238 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
239 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
240 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
241 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
242 case PIPE_CAP_DEPTH_BOUNDS_TEST:
243 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
244 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
245 case PIPE_CAP_CLEAR_TEXTURE:
246 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
247 case PIPE_CAP_INVALIDATE_BUFFER:
248 case PIPE_CAP_STRING_MARKER:
249 case PIPE_CAP_CULL_DISTANCE:
250 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
251 case PIPE_CAP_LEGACY_MATH_RULES:
252 case PIPE_CAP_TGSI_TEX_TXF_LZ:
253 case PIPE_CAP_SHADER_CLOCK:
254 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
255 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
256 case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
257 case PIPE_CAP_TGSI_DIV:
258 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
259 case PIPE_CAP_FLATSHADE:
260 case PIPE_CAP_POINT_SIZE_FIXED:
261 case PIPE_CAP_TWO_SIDED_COLOR:
262 case PIPE_CAP_CLIP_PLANES:
263 case PIPE_CAP_PACKED_STREAM_OUTPUT:
264 case PIPE_CAP_CLEAR_SCISSORED:
265 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
266 case PIPE_CAP_COMPUTE:
267 case PIPE_CAP_GL_CLAMP:
268 case PIPE_CAP_TEXRECT:
269 case PIPE_CAP_ALLOW_DYNAMIC_VAO_FASTPATH:
270 case PIPE_CAP_SHAREABLE_SHADERS:
271 case PIPE_CAP_PREFER_BACK_BUFFER_REUSE:
272 return 1;
273
274 case PIPE_CAP_ALPHA_TEST:
275 /* nvc0 has fixed function alpha test support, but nv50 doesn't. The TGSI
276 * backend emits the conditional discard code against a driver-uploaded
277 * uniform, but with NIR we can have the st emit it for us.
278 */
279 return class_3d >= NVC0_3D_CLASS || !screen->prefer_nir;
280
281 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
282 return PIPE_TEXTURE_TRANSFER_BLIT;
283 case PIPE_CAP_SEAMLESS_CUBE_MAP:
284 return 1; /* class_3d >= NVA0_3D_CLASS; */
285 /* supported on nva0+ */
286 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
287 return class_3d >= NVA0_3D_CLASS;
288 /* supported on nva3+ */
289 case PIPE_CAP_CUBE_MAP_ARRAY:
290 case PIPE_CAP_INDEP_BLEND_FUNC:
291 case PIPE_CAP_TEXTURE_QUERY_LOD:
292 case PIPE_CAP_SAMPLE_SHADING:
293 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
294 return class_3d >= NVA3_3D_CLASS;
295
296 /* unsupported caps */
297 case PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART:
298 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
299 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
300 case PIPE_CAP_FS_COORD_ORIGIN_LOWER_LEFT:
301 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
302 case PIPE_CAP_SHADER_STENCIL_EXPORT:
303 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
304 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
305 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
306 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
307 case PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY:
308 case PIPE_CAP_TGSI_TEXCOORD:
309 case PIPE_CAP_VS_LAYER_VIEWPORT:
310 case PIPE_CAP_TEXTURE_GATHER_SM5:
311 case PIPE_CAP_FAKE_SW_MSAA:
312 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
313 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
314 case PIPE_CAP_DRAW_INDIRECT:
315 case PIPE_CAP_MULTI_DRAW_INDIRECT:
316 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
317 case PIPE_CAP_VERTEXID_NOBASE:
318 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
319 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
320 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
321 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
322 case PIPE_CAP_DRAW_PARAMETERS:
323 case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
324 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
325 case PIPE_CAP_FS_POINT_IS_SYSVAL:
326 case PIPE_CAP_GENERATE_MIPMAP:
327 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
328 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
329 case PIPE_CAP_QUERY_BUFFER_OBJECT:
330 case PIPE_CAP_QUERY_MEMORY_INFO:
331 case PIPE_CAP_PCI_GROUP:
332 case PIPE_CAP_PCI_BUS:
333 case PIPE_CAP_PCI_DEVICE:
334 case PIPE_CAP_PCI_FUNCTION:
335 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
336 case PIPE_CAP_SHADER_GROUP_VOTE:
337 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
338 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
339 case PIPE_CAP_SHADER_CAN_READ_OUTPUTS:
340 case PIPE_CAP_NATIVE_FENCE_FD:
341 case PIPE_CAP_FBFETCH:
342 case PIPE_CAP_DOUBLES:
343 case PIPE_CAP_INT64:
344 case PIPE_CAP_INT64_DIVMOD:
345 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
346 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
347 case PIPE_CAP_SHADER_BALLOT:
348 case PIPE_CAP_TES_LAYER_VIEWPORT:
349 case PIPE_CAP_POST_DEPTH_COVERAGE:
350 case PIPE_CAP_BINDLESS_TEXTURE:
351 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
352 case PIPE_CAP_QUERY_SO_OVERFLOW:
353 case PIPE_CAP_MEMOBJ:
354 case PIPE_CAP_LOAD_CONSTBUF:
355 case PIPE_CAP_TILE_RASTER_ORDER:
356 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
357 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
358 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
359 case PIPE_CAP_FENCE_SIGNAL:
360 case PIPE_CAP_CONSTBUF0_FLAGS:
361 case PIPE_CAP_PACKED_UNIFORMS:
362 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
363 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
364 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
365 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
366 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
367 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
368 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
369 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
370 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
371 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
372 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
373 case PIPE_CAP_IMAGE_ATOMIC_FLOAT_ADD:
374 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
375 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
376 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
377 case PIPE_CAP_NIR_COMPACT_ARRAYS:
378 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
379 case PIPE_CAP_IMAGE_STORE_FORMATTED:
380 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
381 case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
382 case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
383 case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
384 case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
385 case PIPE_CAP_FBFETCH_COHERENT:
386 case PIPE_CAP_IMAGE_ATOMIC_INC_WRAP:
387 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
388 case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
389 case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
390 case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
391 case PIPE_CAP_FRONTEND_NOOP:
392 case PIPE_CAP_GL_SPIRV:
393 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
394 case PIPE_CAP_TEXTURE_SHADOW_LOD:
395 case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
396 case PIPE_CAP_PSIZ_CLAMPED:
397 case PIPE_CAP_VIEWPORT_SWIZZLE:
398 case PIPE_CAP_VIEWPORT_MASK:
399 case PIPE_CAP_TEXTURE_BUFFER_SAMPLER:
400 case PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0:
401 case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE: /* when we fix MT stuff */
402 case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
403 case PIPE_CAP_SHADER_ATOMIC_INT64:
404 case PIPE_CAP_GLSL_ZERO_INIT:
405 case PIPE_CAP_BLEND_EQUATION_ADVANCED:
406 case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
407 case PIPE_CAP_DEVICE_PROTECTED_CONTENT:
408 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
409 case PIPE_CAP_SAMPLER_REDUCTION_MINMAX:
410 case PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB:
411 case PIPE_CAP_DRAW_VERTEX_STATE:
412 case PIPE_CAP_PREFER_POT_ALIGNED_VARYINGS:
413 case PIPE_CAP_MAX_SPARSE_TEXTURE_SIZE:
414 case PIPE_CAP_MAX_SPARSE_3D_TEXTURE_SIZE:
415 case PIPE_CAP_MAX_SPARSE_ARRAY_TEXTURE_LAYERS:
416 case PIPE_CAP_SPARSE_TEXTURE_FULL_ARRAY_CUBE_MIPMAPS:
417 case PIPE_CAP_QUERY_SPARSE_TEXTURE_RESIDENCY:
418 case PIPE_CAP_CLAMP_SPARSE_TEXTURE_LOD:
419 case PIPE_CAP_HARDWARE_GL_SELECT:
420 return 0;
421
422 case PIPE_CAP_VENDOR_ID:
423 return 0x10de;
424 case PIPE_CAP_DEVICE_ID: {
425 uint64_t device_id;
426 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
427 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
428 return -1;
429 }
430 return device_id;
431 }
432 case PIPE_CAP_ACCELERATED:
433 return 1;
434 case PIPE_CAP_VIDEO_MEMORY:
435 return dev->vram_size >> 20;
436 case PIPE_CAP_UMA:
437 return 0;
438
439 default:
440 if (!debug_cap_printed[param]) {
441 debug_printf("%s: unhandled cap %d\n", __func__, param);
442 debug_cap_printed[param] = true;
443 }
444 FALLTHROUGH;
445 /* caps where we want the default value */
446 case PIPE_CAP_DMABUF:
447 case PIPE_CAP_THROTTLE:
448 return u_pipe_screen_get_param_defaults(pscreen, param);
449 }
450 }
451
452 static int
nv50_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)453 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
454 enum pipe_shader_type shader,
455 enum pipe_shader_cap param)
456 {
457 const struct nouveau_screen *screen = nouveau_screen(pscreen);
458
459 switch (shader) {
460 case PIPE_SHADER_VERTEX:
461 case PIPE_SHADER_GEOMETRY:
462 case PIPE_SHADER_FRAGMENT:
463 case PIPE_SHADER_COMPUTE:
464 break;
465 default:
466 return 0;
467 }
468
469 switch (param) {
470 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
471 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
472 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
473 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
474 return 16384;
475 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
476 return 4;
477 case PIPE_SHADER_CAP_MAX_INPUTS:
478 if (shader == PIPE_SHADER_VERTEX)
479 return 32;
480 return 15;
481 case PIPE_SHADER_CAP_MAX_OUTPUTS:
482 return 16;
483 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
484 return 65536;
485 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
486 return NV50_MAX_PIPE_CONSTBUFS;
487 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
488 return shader != PIPE_SHADER_FRAGMENT;
489 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
490 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
491 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
492 return 1;
493 case PIPE_SHADER_CAP_MAX_TEMPS:
494 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
495 case PIPE_SHADER_CAP_CONT_SUPPORTED:
496 return 1;
497 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
498 return 1;
499 case PIPE_SHADER_CAP_INT64_ATOMICS:
500 case PIPE_SHADER_CAP_FP16:
501 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
502 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
503 case PIPE_SHADER_CAP_INT16:
504 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
505 case PIPE_SHADER_CAP_SUBROUTINES:
506 return 0; /* please inline, or provide function declarations */
507 case PIPE_SHADER_CAP_INTEGERS:
508 return 1;
509 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
510 /* The chip could handle more sampler views than samplers */
511 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
512 return MIN2(16, PIPE_MAX_SAMPLERS);
513 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
514 return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
515 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
516 return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
517 case PIPE_SHADER_CAP_PREFERRED_IR:
518 return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
519 case PIPE_SHADER_CAP_SUPPORTED_IRS:
520 return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
521 case PIPE_SHADER_CAP_DROUND_SUPPORTED:
522 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
523 case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
524 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
525 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
526 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
527 return 0;
528 default:
529 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
530 return 0;
531 }
532 }
533
534 static float
nv50_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)535 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
536 {
537 switch (param) {
538 case PIPE_CAPF_MIN_LINE_WIDTH:
539 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
540 case PIPE_CAPF_MIN_POINT_SIZE:
541 case PIPE_CAPF_MIN_POINT_SIZE_AA:
542 return 1;
543 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
544 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
545 return 0.1;
546 case PIPE_CAPF_MAX_LINE_WIDTH:
547 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
548 return 10.0f;
549 case PIPE_CAPF_MAX_POINT_SIZE:
550 case PIPE_CAPF_MAX_POINT_SIZE_AA:
551 return 64.0f;
552 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
553 return 16.0f;
554 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
555 return 15.0f;
556 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
557 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
558 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
559 return 0.0f;
560 }
561
562 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
563 return 0.0f;
564 }
565
566 static int
nv50_screen_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * data)567 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
568 enum pipe_shader_ir ir_type,
569 enum pipe_compute_cap param, void *data)
570 {
571 struct nv50_screen *screen = nv50_screen(pscreen);
572
573 #define RET(x) do { \
574 if (data) \
575 memcpy(data, x, sizeof(x)); \
576 return sizeof(x); \
577 } while (0)
578
579 switch (param) {
580 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
581 RET((uint64_t []) { 3 });
582 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
583 RET(((uint64_t []) { 65535, 65535, 65535 }));
584 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
585 RET(((uint64_t []) { 512, 512, 64 }));
586 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
587 RET((uint64_t []) { 512 });
588 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
589 RET((uint64_t []) { 1ULL << 32 });
590 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
591 RET((uint64_t []) { 16 << 10 });
592 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
593 RET((uint64_t []) { 16 << 10 });
594 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
595 RET((uint64_t []) { 4096 });
596 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
597 RET((uint32_t []) { 32 });
598 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
599 RET((uint64_t []) { 1ULL << 40 });
600 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
601 RET((uint32_t []) { 0 });
602 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
603 RET((uint32_t []) { screen->mp_count });
604 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
605 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
606 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
607 RET((uint32_t []) { 32 });
608 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
609 RET((uint64_t []) { 0 });
610 default:
611 return 0;
612 }
613
614 #undef RET
615 }
616
617 static void
nv50_screen_destroy(struct pipe_screen * pscreen)618 nv50_screen_destroy(struct pipe_screen *pscreen)
619 {
620 struct nv50_screen *screen = nv50_screen(pscreen);
621
622 if (!nouveau_drm_screen_unref(&screen->base))
623 return;
624
625 nouveau_fence_cleanup(&screen->base);
626
627 if (screen->base.pushbuf)
628 screen->base.pushbuf->user_priv = NULL;
629
630 if (screen->blitter)
631 nv50_blitter_destroy(screen);
632 if (screen->pm.prog) {
633 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
634 nv50_program_destroy(NULL, screen->pm.prog);
635 FREE(screen->pm.prog);
636 }
637
638 nouveau_bo_ref(NULL, &screen->code);
639 nouveau_bo_ref(NULL, &screen->tls_bo);
640 nouveau_bo_ref(NULL, &screen->stack_bo);
641 nouveau_bo_ref(NULL, &screen->txc);
642 nouveau_bo_ref(NULL, &screen->uniforms);
643 nouveau_bo_ref(NULL, &screen->fence.bo);
644
645 nouveau_heap_destroy(&screen->vp_code_heap);
646 nouveau_heap_destroy(&screen->gp_code_heap);
647 nouveau_heap_destroy(&screen->fp_code_heap);
648
649 FREE(screen->tic.entries);
650
651 nouveau_object_del(&screen->tesla);
652 nouveau_object_del(&screen->eng2d);
653 nouveau_object_del(&screen->m2mf);
654 nouveau_object_del(&screen->compute);
655 nouveau_object_del(&screen->sync);
656
657 nouveau_screen_fini(&screen->base);
658
659 FREE(screen);
660 }
661
662 static void
nv50_screen_fence_emit(struct pipe_screen * pscreen,u32 * sequence)663 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
664 {
665 struct nv50_screen *screen = nv50_screen(pscreen);
666 struct nouveau_pushbuf *push = screen->base.pushbuf;
667
668 /* we need to do it after possible flush in MARK_RING */
669 *sequence = ++screen->base.fence.sequence;
670
671 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
672 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
673 PUSH_DATAh(push, screen->fence.bo->offset);
674 PUSH_DATA (push, screen->fence.bo->offset);
675 PUSH_DATA (push, *sequence);
676 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
677 NV50_3D_QUERY_GET_UNK4 |
678 NV50_3D_QUERY_GET_UNIT_CROP |
679 NV50_3D_QUERY_GET_TYPE_QUERY |
680 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
681 NV50_3D_QUERY_GET_SHORT);
682 }
683
684 static u32
nv50_screen_fence_update(struct pipe_screen * pscreen)685 nv50_screen_fence_update(struct pipe_screen *pscreen)
686 {
687 return nv50_screen(pscreen)->fence.map[0];
688 }
689
690 static void
nv50_screen_init_hwctx(struct nv50_screen * screen)691 nv50_screen_init_hwctx(struct nv50_screen *screen)
692 {
693 struct nouveau_pushbuf *push = screen->base.pushbuf;
694 struct nv04_fifo *fifo;
695 unsigned i;
696
697 fifo = (struct nv04_fifo *)screen->base.channel->data;
698
699 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
700 PUSH_DATA (push, screen->m2mf->handle);
701 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
702 PUSH_DATA (push, screen->sync->handle);
703 PUSH_DATA (push, fifo->vram);
704 PUSH_DATA (push, fifo->vram);
705
706 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
707 PUSH_DATA (push, screen->eng2d->handle);
708 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
709 PUSH_DATA (push, screen->sync->handle);
710 PUSH_DATA (push, fifo->vram);
711 PUSH_DATA (push, fifo->vram);
712 PUSH_DATA (push, fifo->vram);
713 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
714 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
715 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
716 PUSH_DATA (push, 0);
717 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
718 PUSH_DATA (push, 0);
719 BEGIN_NV04(push, NV50_2D(SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP), 1);
720 PUSH_DATA (push, 1);
721 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
722 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
723
724 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
725 PUSH_DATA (push, screen->tesla->handle);
726
727 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
728 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
729
730 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
731 PUSH_DATA (push, screen->sync->handle);
732 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
733 for (i = 0; i < 11; ++i)
734 PUSH_DATA(push, fifo->vram);
735 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
736 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
737 PUSH_DATA(push, fifo->vram);
738
739 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
740 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
741 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
742 PUSH_DATA (push, 0xf);
743
744 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
745 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
746 PUSH_DATA (push, 0x18);
747 }
748
749 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
750 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
751
752 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
753 for (i = 0; i < 8; ++i)
754 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
755
756 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
757 PUSH_DATA (push, 1);
758
759 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
760 PUSH_DATA (push, 0);
761 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
762 PUSH_DATA (push, 0);
763 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
764 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
765 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
766 PUSH_DATA (push, 0);
767 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
768 PUSH_DATA (push, 1);
769 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
770 PUSH_DATA (push, 1);
771
772 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
773 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
774 PUSH_DATA (push, 0);
775 }
776
777 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
778 PUSH_DATA (push, 0);
779 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
780 PUSH_DATA (push, 0);
781 PUSH_DATA (push, 0);
782 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
783 PUSH_DATA (push, 0x3f);
784
785 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
786 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
787 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
788
789 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
790 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
791 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
792
793 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
794 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
795 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
796
797 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
798 PUSH_DATAh(push, screen->tls_bo->offset);
799 PUSH_DATA (push, screen->tls_bo->offset);
800 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
801
802 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
803 PUSH_DATAh(push, screen->stack_bo->offset);
804 PUSH_DATA (push, screen->stack_bo->offset);
805 PUSH_DATA (push, 4);
806
807 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
808 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
809 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
810 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
811
812 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
813 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
814 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
815 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
816
817 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
818 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
819 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
820 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
821
822 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
823 PUSH_DATAh(push, screen->uniforms->offset + (4 << 16));
824 PUSH_DATA (push, screen->uniforms->offset + (4 << 16));
825 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
826
827 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
828 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
829 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
830 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
831
832 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
833 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
834 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
835 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
836 PUSH_DATAf(push, 0.0f);
837 PUSH_DATAf(push, 0.0f);
838 PUSH_DATAf(push, 0.0f);
839 PUSH_DATAf(push, 0.0f);
840 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
841 PUSH_DATAh(push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
842 PUSH_DATA (push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
843
844 /* set the membar offset */
845 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
846 PUSH_DATA (push, (NV50_CB_AUX_MEMBAR_OFFSET << (8 - 2)) | NV50_CB_AUX);
847 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 1);
848 PUSH_DATA (push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_MEMBAR_OFFSET);
849
850 nv50_upload_ms_info(push);
851
852 /* max TIC (bits 4:8) & TSC bindings, per program type */
853 for (i = 0; i < NV50_MAX_3D_SHADER_STAGES; ++i) {
854 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
855 PUSH_DATA (push, 0x54);
856 }
857
858 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
859 PUSH_DATAh(push, screen->txc->offset);
860 PUSH_DATA (push, screen->txc->offset);
861 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
862
863 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
864 PUSH_DATAh(push, screen->txc->offset + 65536);
865 PUSH_DATA (push, screen->txc->offset + 65536);
866 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
867
868 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
869 PUSH_DATA (push, 0);
870
871 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
872 PUSH_DATA (push, 0);
873 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
874 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
875 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
876 for (i = 0; i < 8 * 2; ++i)
877 PUSH_DATA(push, 0);
878 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
879 PUSH_DATA (push, 0);
880
881 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
882 PUSH_DATA (push, 1);
883 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
884 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
885 PUSH_DATAf(push, 0.0f);
886 PUSH_DATAf(push, 1.0f);
887 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
888 PUSH_DATA (push, 8192 << 16);
889 PUSH_DATA (push, 8192 << 16);
890 }
891
892 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
893 #ifdef NV50_SCISSORS_CLIPPING
894 PUSH_DATA (push, 0x0000);
895 #else
896 PUSH_DATA (push, 0x1080);
897 #endif
898
899 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
900 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
901
902 /* We use scissors instead of exact view volume clipping,
903 * so they're always enabled.
904 */
905 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
906 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
907 PUSH_DATA (push, 1);
908 PUSH_DATA (push, 8192 << 16);
909 PUSH_DATA (push, 8192 << 16);
910 }
911
912 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
913 PUSH_DATA (push, 1);
914 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
915 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
916 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
917 PUSH_DATA (push, 0x11111111);
918 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
919 PUSH_DATA (push, 1);
920
921 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
922 PUSH_DATA (push, 0);
923 if (screen->base.class_3d >= NV84_3D_CLASS) {
924 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
925 PUSH_DATA (push, 0);
926 }
927
928 BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
929 PUSH_DATA (push, 1);
930 BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
931 PUSH_DATA (push, 1);
932
933 PUSH_KICK (push);
934 }
935
nv50_tls_alloc(struct nv50_screen * screen,unsigned tls_space,uint64_t * tls_size)936 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
937 uint64_t *tls_size)
938 {
939 struct nouveau_device *dev = screen->base.device;
940 int ret;
941
942 assert(tls_space % ONE_TEMP_SIZE == 0);
943 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
944 ONE_TEMP_SIZE;
945 if (nouveau_mesa_debug)
946 debug_printf("allocating space for %u temps\n",
947 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
948 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
949 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
950
951 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
952 *tls_size, NULL, &screen->tls_bo);
953 if (ret) {
954 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
955 return ret;
956 }
957
958 return 0;
959 }
960
nv50_tls_realloc(struct nv50_screen * screen,unsigned tls_space)961 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
962 {
963 struct nouveau_pushbuf *push = screen->base.pushbuf;
964 int ret;
965 uint64_t tls_size;
966
967 if (tls_space < screen->cur_tls_space)
968 return 0;
969 if (tls_space > screen->max_tls_space) {
970 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
971 * LOCAL_WARPS_NO_CLAMP) */
972 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
973 (unsigned)(tls_space / ONE_TEMP_SIZE),
974 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
975 return -ENOMEM;
976 }
977
978 nouveau_bo_ref(NULL, &screen->tls_bo);
979 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
980 if (ret)
981 return ret;
982
983 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
984 PUSH_DATAh(push, screen->tls_bo->offset);
985 PUSH_DATA (push, screen->tls_bo->offset);
986 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
987
988 return 1;
989 }
990
991 static const void *
nv50_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)992 nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
993 enum pipe_shader_ir ir,
994 enum pipe_shader_type shader)
995 {
996 if (ir == PIPE_SHADER_IR_NIR)
997 return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader);
998 return NULL;
999 }
1000
1001 struct nouveau_screen *
nv50_screen_create(struct nouveau_device * dev)1002 nv50_screen_create(struct nouveau_device *dev)
1003 {
1004 struct nv50_screen *screen;
1005 struct pipe_screen *pscreen;
1006 struct nouveau_object *chan;
1007 uint64_t value;
1008 uint32_t tesla_class;
1009 unsigned stack_size;
1010 int ret;
1011
1012 screen = CALLOC_STRUCT(nv50_screen);
1013 if (!screen)
1014 return NULL;
1015 pscreen = &screen->base.base;
1016 pscreen->destroy = nv50_screen_destroy;
1017
1018 ret = nouveau_screen_init(&screen->base, dev);
1019 if (ret) {
1020 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
1021 goto fail;
1022 }
1023
1024 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
1025 * admit them to VRAM.
1026 */
1027 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1028 PIPE_BIND_VERTEX_BUFFER;
1029 screen->base.sysmem_bindings |=
1030 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1031
1032 screen->base.pushbuf->user_priv = screen;
1033 screen->base.pushbuf->rsvd_kick = 5;
1034
1035 chan = screen->base.channel;
1036
1037 pscreen->context_create = nv50_create;
1038 pscreen->is_format_supported = nv50_screen_is_format_supported;
1039 pscreen->get_param = nv50_screen_get_param;
1040 pscreen->get_shader_param = nv50_screen_get_shader_param;
1041 pscreen->get_paramf = nv50_screen_get_paramf;
1042 pscreen->get_compute_param = nv50_screen_get_compute_param;
1043 pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
1044 pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
1045
1046 /* nir stuff */
1047 pscreen->get_compiler_options = nv50_screen_get_compiler_options;
1048
1049 nv50_screen_init_resource_functions(pscreen);
1050
1051 if (screen->base.device->chipset < 0x84 ||
1052 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
1053 /* PMPEG */
1054 nouveau_screen_init_vdec(&screen->base);
1055 } else if (screen->base.device->chipset < 0x98 ||
1056 screen->base.device->chipset == 0xa0) {
1057 /* VP2 */
1058 screen->base.base.get_video_param = nv84_screen_get_video_param;
1059 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
1060 } else {
1061 /* VP3/4 */
1062 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1063 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1064 }
1065
1066 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
1067 NULL, &screen->fence.bo);
1068 if (ret) {
1069 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
1070 goto fail;
1071 }
1072
1073 nouveau_bo_map(screen->fence.bo, 0, NULL);
1074 screen->fence.map = screen->fence.bo->map;
1075 screen->base.fence.emit = nv50_screen_fence_emit;
1076 screen->base.fence.update = nv50_screen_fence_update;
1077
1078 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
1079 &(struct nv04_notify){ .length = 32 },
1080 sizeof(struct nv04_notify), &screen->sync);
1081 if (ret) {
1082 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
1083 goto fail;
1084 }
1085
1086 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
1087 NULL, 0, &screen->m2mf);
1088 if (ret) {
1089 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
1090 goto fail;
1091 }
1092
1093 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
1094 NULL, 0, &screen->eng2d);
1095 if (ret) {
1096 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
1097 goto fail;
1098 }
1099
1100 switch (dev->chipset & 0xf0) {
1101 case 0x50:
1102 tesla_class = NV50_3D_CLASS;
1103 break;
1104 case 0x80:
1105 case 0x90:
1106 tesla_class = NV84_3D_CLASS;
1107 break;
1108 case 0xa0:
1109 switch (dev->chipset) {
1110 case 0xa0:
1111 case 0xaa:
1112 case 0xac:
1113 tesla_class = NVA0_3D_CLASS;
1114 break;
1115 case 0xaf:
1116 tesla_class = NVAF_3D_CLASS;
1117 break;
1118 default:
1119 tesla_class = NVA3_3D_CLASS;
1120 break;
1121 }
1122 break;
1123 default:
1124 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
1125 goto fail;
1126 }
1127 screen->base.class_3d = tesla_class;
1128
1129 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
1130 NULL, 0, &screen->tesla);
1131 if (ret) {
1132 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
1133 goto fail;
1134 }
1135
1136 /* This over-allocates by a page. The GP, which would execute at the end of
1137 * the last page, would trigger faults. The going theory is that it
1138 * prefetches up to a certain amount.
1139 */
1140 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
1141 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
1142 NULL, &screen->code);
1143 if (ret) {
1144 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
1145 goto fail;
1146 }
1147
1148 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1149 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1150 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1151
1152 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1153
1154 screen->TPs = util_bitcount(value & 0xffff);
1155 screen->MPsInTP = util_bitcount(value & 0x0f000000);
1156
1157 screen->mp_count = screen->TPs * screen->MPsInTP;
1158
1159 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1160 STACK_WARPS_ALLOC * 64 * 8;
1161
1162 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1163 &screen->stack_bo);
1164 if (ret) {
1165 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1166 goto fail;
1167 }
1168
1169 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1170 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
1171 ONE_TEMP_SIZE;
1172 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1173 screen->max_tls_space /= 2; /* half of vram */
1174
1175 /* hw can address max 64 KiB */
1176 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1177
1178 uint64_t tls_size;
1179 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1180 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1181 if (ret)
1182 goto fail;
1183
1184 if (nouveau_mesa_debug)
1185 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1186 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1187
1188 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 5 << 16, NULL,
1189 &screen->uniforms);
1190 if (ret) {
1191 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1192 goto fail;
1193 }
1194
1195 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1196 &screen->txc);
1197 if (ret) {
1198 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1199 goto fail;
1200 }
1201
1202 screen->tic.entries = CALLOC(4096, sizeof(void *));
1203 screen->tsc.entries = screen->tic.entries + 2048;
1204
1205 if (!nv50_blitter_create(screen))
1206 goto fail;
1207
1208 nv50_screen_init_hwctx(screen);
1209
1210 ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1211 if (ret) {
1212 NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1213 goto fail;
1214 }
1215
1216 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1217
1218 return &screen->base;
1219
1220 fail:
1221 screen->base.base.context_create = NULL;
1222 return &screen->base;
1223 }
1224
1225 int
nv50_screen_tic_alloc(struct nv50_screen * screen,void * entry)1226 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1227 {
1228 int i = screen->tic.next;
1229
1230 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1231 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1232
1233 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1234
1235 if (screen->tic.entries[i])
1236 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1237
1238 screen->tic.entries[i] = entry;
1239 return i;
1240 }
1241
1242 int
nv50_screen_tsc_alloc(struct nv50_screen * screen,void * entry)1243 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1244 {
1245 int i = screen->tsc.next;
1246
1247 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1248 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1249
1250 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1251
1252 if (screen->tsc.entries[i])
1253 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1254
1255 screen->tsc.entries[i] = entry;
1256 return i;
1257 }
1258