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Searched defs:qword (Results 1 – 11 of 11) sorted by relevance

/third_party/skia/third_party/externals/oboe/samples/RhythmGame/third_party/glm/gtx/
Draw_data.hpp42 typedef detail::uint64 qword; typedef
/third_party/mesa3d/src/gallium/drivers/virgl/
Dvirgl_encode.h64 uint64_t qword) in virgl_encoder_write_qword()
Dvirgl_encode.c621 uint64_t qword; in virgl_encode_clear() local
/third_party/libdrm/radeon/
Dradeon_cs.h123 static inline void radeon_cs_write_qword(struct radeon_cs *cs, uint64_t qword) in radeon_cs_write_qword()
/third_party/skia/third_party/externals/swiftshader/src/Common/
DTypes.hpp51 typedef ALIGN(8, uint64_t) qword; typedef
/third_party/mesa3d/src/panfrost/midgard/
Dmir_promote_uniforms.c292 unsigned qword = ins->constants.u32[0] / 16; in midgard_promote_uniforms() local
/third_party/skia/third_party/externals/swiftshader/src/System/
DTypes.hpp79 typedef ALIGN(8, uint64_t) qword; typedef
/third_party/mesa3d/src/freedreno/decode/
Dcffdec.c404 reg_dump_gpuaddr64(const char *name, uint64_t qword, int level) in reg_dump_gpuaddr64()
474 reg_disasm_gpuaddr64(const char *name, uint64_t qword, int level) in reg_disasm_gpuaddr64()
878 uint64_t qword = (((uint64_t)reg_val(regbase + 1)) << 32) | dword; in dump_register() local
/third_party/mesa3d/src/intel/vulkan/
DgenX_query.c675 for (uint32_t qword = 1; qword < (pool->stride / 8); qword++) { in emit_zero_queries() local
/third_party/skia/third_party/externals/swiftshader/src/Renderer/
DSurface.hpp365 typedef uint64_t qword; typedef in sw::Surface
/third_party/mesa3d/src/gallium/drivers/zink/nir_to_spirv/
Dnir_to_spirv.c2443 bool qword = nir_src_bit_size(intr->src[0]) == 64; in emit_store_shared() local