1 /******************************************************************************
2 * @file arm_math_memory.h
3 * @brief Public header file for CMSIS DSP Library
4 * @version V1.10.0
5 * @date 08 July 2021
6 * Target Processor: Cortex-M and Cortex-A cores
7 ******************************************************************************/
8 /*
9 * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
10 *
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26 #ifndef _ARM_MATH_MEMORY_H_
27
28 #define _ARM_MATH_MEMORY_H_
29
30 #include "arm_math_types.h"
31
32
33 #ifdef __cplusplus
34 extern "C"
35 {
36 #endif
37
38 /**
39 @brief definition to read/write two 16 bit values.
40 @deprecated
41 */
42 #if defined ( __CC_ARM )
43 #define __SIMD32_TYPE int32_t __packed
44 #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
45 #define __SIMD32_TYPE int32_t
46 #elif defined ( __GNUC__ )
47 #define __SIMD32_TYPE int32_t
48 #elif defined ( __ICCARM__ )
49 #define __SIMD32_TYPE int32_t __packed
50 #elif defined ( __TI_ARM__ )
51 #define __SIMD32_TYPE int32_t
52 #elif defined ( __CSMC__ )
53 #define __SIMD32_TYPE int32_t
54 #elif defined ( __TASKING__ )
55 #define __SIMD32_TYPE __un(aligned) int32_t
56 #elif defined(_MSC_VER )
57 #define __SIMD32_TYPE int32_t
58 #else
59 #error Unknown compiler
60 #endif
61
62 #define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
63 #define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
64 #define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
65 #define __SIMD64(addr) (*( int64_t **) & (addr))
66
67
68 /* SIMD replacement */
69
70
71 /**
72 @brief Read 2 Q15 from Q15 pointer.
73 @param[in] pQ15 points to input value
74 @return Q31 value
75 */
read_q15x2(q15_t const * pQ15)76 __STATIC_FORCEINLINE q31_t read_q15x2 (
77 q15_t const * pQ15)
78 {
79 q31_t val;
80
81 #ifdef __ARM_FEATURE_UNALIGNED
82 memcpy (&val, pQ15, 4);
83 #else
84 val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
85 #endif
86
87 return (val);
88 }
89
90 /**
91 @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
92 @param[in] pQ15 points to input value
93 @return Q31 value
94 */
95 #define read_q15x2_ia(pQ15) read_q15x2((*(pQ15) += 2) - 2)
96
97 /**
98 @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
99 @param[in] pQ15 points to input value
100 @return Q31 value
101 */
102 #define read_q15x2_da(pQ15) read_q15x2((*(pQ15) -= 2) + 2)
103
104 /**
105 @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
106 @param[in] pQ15 points to input value
107 @param[in] value Q31 value
108 @return none
109 */
write_q15x2_ia(q15_t ** pQ15,q31_t value)110 __STATIC_FORCEINLINE void write_q15x2_ia (
111 q15_t ** pQ15,
112 q31_t value)
113 {
114 q31_t val = value;
115 #ifdef __ARM_FEATURE_UNALIGNED
116 memcpy (*pQ15, &val, 4);
117 #else
118 (*pQ15)[0] = (q15_t)(val & 0x0FFFF);
119 (*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF);
120 #endif
121
122 *pQ15 += 2;
123 }
124
125 /**
126 @brief Write 2 Q15 to Q15 pointer.
127 @param[in] pQ15 points to input value
128 @param[in] value Q31 value
129 @return none
130 */
write_q15x2(q15_t * pQ15,q31_t value)131 __STATIC_FORCEINLINE void write_q15x2 (
132 q15_t * pQ15,
133 q31_t value)
134 {
135 q31_t val = value;
136
137 #ifdef __ARM_FEATURE_UNALIGNED
138 memcpy (pQ15, &val, 4);
139 #else
140 pQ15[0] = (q15_t)(val & 0x0FFFF);
141 pQ15[1] = (q15_t)(val >> 16);
142 #endif
143 }
144
145
146 /**
147 @brief Read 4 Q7 from Q7 pointer
148 @param[in] pQ7 points to input value
149 @return Q31 value
150 */
read_q7x4(q7_t const * pQ7)151 __STATIC_FORCEINLINE q31_t read_q7x4 (
152 q7_t const * pQ7)
153 {
154 q31_t val;
155
156 #ifdef __ARM_FEATURE_UNALIGNED
157 memcpy (&val, pQ7, 4);
158 #else
159 val =((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | (pQ7[0] & 0x0FF);
160 #endif
161 return (val);
162 }
163
164 /**
165 @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
166 @param[in] pQ7 points to input value
167 @return Q31 value
168 */
169 #define read_q7x4_ia(pQ7) read_q7x4((*(pQ7) += 4) - 4)
170
171 /**
172 @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
173 @param[in] pQ7 points to input value
174 @return Q31 value
175 */
176 #define read_q7x4_da(pQ7) read_q7x4((*(pQ7) -= 4) + 4)
177
178 /**
179 @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
180 @param[in] pQ7 points to input value
181 @param[in] value Q31 value
182 @return none
183 */
write_q7x4_ia(q7_t ** pQ7,q31_t value)184 __STATIC_FORCEINLINE void write_q7x4_ia (
185 q7_t ** pQ7,
186 q31_t value)
187 {
188 q31_t val = value;
189 #ifdef __ARM_FEATURE_UNALIGNED
190 memcpy (*pQ7, &val, 4);
191 #else
192 (*pQ7)[0] = (q7_t)(val & 0x0FF);
193 (*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF);
194 (*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF);
195 (*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF);
196
197 #endif
198 *pQ7 += 4;
199 }
200
201
202 #ifdef __cplusplus
203 }
204 #endif
205
206 #endif /*ifndef _ARM_MATH_MEMORY_H_ */
207