| /third_party/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc | 75 ShiftType ror; member
5135 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-assembler-cond-rd-operand-rn-ror-amount-t32.cc | 74 ShiftType ror; member
1233 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-assembler-cond-rd-operand-rn-ror-amount-a32.cc | 74 ShiftType ror; member
1345 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc | 75 ShiftType ror; member
5135 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 139 ShiftType ror; member
597 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 139 ShiftType ror; member
597 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 140 ShiftType ror; member
1131 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 140 ShiftType ror; member
1131 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| /third_party/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 639 static inline uint32_t ror(uint32_t x, int i) { in ror() function
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| D | assembler-aarch32.h | 2897 void ror(Register rd, Register rm, const Operand& operand) { in ror() function
2900 void ror(Condition cond, Register rd, Register rm, const Operand& operand) { in ror() function
2903 void ror(EncodingSize size, in ror() function
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| D | assembler-aarch32.cc | 8963 void Assembler::ror(Condition cond, in ror() function in vixl::aarch32::Assembler
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| D | disasm-aarch32.cc | 2288 void Disassembler::ror(Condition cond, in ror() function in vixl::aarch32::Disassembler
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| /third_party/ffmpeg/libavutil/ |
| D | sha512.c | 91 #define ror(value, bits) (((value) >> (bits)) | ((value) << (64 - (bits)))) macro
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| /third_party/musl/src/crypt/ |
| D | crypt_sha256.c | 24 static uint32_t ror(uint32_t n, int k) { return (n >> k) | (n << (32-k)); } in ror() function
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| D | crypt_sha512.c | 25 static uint64_t ror(uint64_t n, int k) { return (n >> k) | (n << (64-k)); } in ror() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 32 ror, enumerator
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | assembler-arm64.h | 719 void ror(const Register& rd, const Register& rs, unsigned shift) { in ror() function
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| /third_party/mesa3d/src/intel/isl/ |
| D | isl_tiled_memcpy.c | 62 ror(uint32_t n, uint32_t d) in ror() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 205 static inline uint64_t ror(uint64_t elt, unsigned size) { in ror() function
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| /third_party/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 943 void ror(const Register& rd, const Register& rs, unsigned shift) { in ror() function
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| D | logic-aarch64.cc | 2472 LogicVRegister Simulator::ror(VectorFormat vform, in ror() function in vixl::aarch64::Simulator
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| /third_party/node/deps/v8/src/codegen/ia32/ |
| D | assembler-ia32.h | 659 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); } in ror() function
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| D | assembler-ia32.cc | 1182 void Assembler::ror(Operand dst, uint8_t imm8) { in ror() function in v8::internal::Assembler
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| /third_party/node/deps/v8/src/compiler/backend/ia32/ |
| D | code-generator-ia32.cc | 1247 __ ror(i.OutputOperand(), i.InputInt5(1)); in AssembleArchInstruction() local
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