| /third_party/node/deps/v8/src/codegen/riscv64/ |
| D | assembler-riscv64.cc | 818 Register rd, Register rs1, Register rs2) { in GenInstrR()
828 FPURegister rd, FPURegister rs1, FPURegister rs2) { in GenInstrR()
838 Register rd, FPURegister rs1, Register rs2) { in GenInstrR()
848 FPURegister rd, Register rs1, Register rs2) { in GenInstrR()
858 FPURegister rd, FPURegister rs1, Register rs2) { in GenInstrR()
868 Register rd, FPURegister rs1, FPURegister rs2) { in GenInstrR()
878 Register rs1, Register rs2, Register rs3, in GenInstrR4()
889 FPURegister rs1, FPURegister rs2, FPURegister rs3, in GenInstrR4()
900 uint8_t funct3, Register rd, Register rs1, in GenInstrRAtomic()
911 Register rs1, Register rs2, RoundingMode frm) { in GenInstrRFrm()
[all …]
|
| D | assembler-riscv64.h | 394 inline void beq(Register rs1, Register rs2, Label* L) { in beq()
398 inline void bne(Register rs1, Register rs2, Label* L) { in bne()
402 inline void blt(Register rs1, Register rs2, Label* L) { in blt()
406 inline void bge(Register rs1, Register rs2, Label* L) { in bge()
410 inline void bltu(Register rs1, Register rs2, Label* L) { in bltu()
414 inline void bgeu(Register rs1, Register rs2, Label* L) { in bgeu()
652 inline void c_bnez(Register rs1, Label* L) { c_bnez(rs1, branch_offset(L)); } in c_bnez()
654 inline void c_beqz(Register rs1, Label* L) { c_beqz(rs1, branch_offset(L)); } in c_beqz()
1080 inline void beqz(Register rs1, Label* L) { beqz(rs1, branch_offset(L)); } in beqz()
1082 inline void bnez(Register rs1, Label* L) { bnez(rs1, branch_offset(L)); } in bnez()
[all …]
|
| D | macro-assembler-riscv64.h | 949 void CmpTagged(const Register& rd, const Register& rs1, const Register& rs2) { in CmpTagged()
|
| /third_party/gstreamer/gstplugins_good/gst/goom/ |
| D | xmmx.h | 385 #define mmx_r2ir(op, rs1, rs2) \ argument
442 #define paddsiw_r2ir(rs1, rs2) mmx_r2ir(paddsiw, rs1, rs2) argument
450 #define psubsiw_r2ir(rs1, rs2) mmx_r2ir(psubsiw, rs1, rs2) argument
466 #define pmulhriw_r2ir(rs1, rs2) mmx_r2ir(pmulhriw, rs1, rs2) argument
474 #define pmachriw_r2ir(rs1, rs2) mmx_r2ir(pmachriw, rs1, rs2) argument
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 374 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeMem() local
531 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeJMPL() local
564 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeReturn() local
593 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeSWAP() local
632 unsigned rs1 = fieldFromInstruction(insn, 14, 5); in DecodeTRAP() local
|
| /third_party/node/test/parallel/ |
| D | test-webstreams-abort-controller.js | 65 const rs1 = createTestReadableStream(); constant
|
| /third_party/elfutils/libcpu/ |
| D | riscv_disasm.c | 181 uint16_t rs1; in riscv_disasm() local
549 uint32_t rs1; in riscv_disasm() local
|
| /third_party/mbedtls/library/ |
| D | poly1305.c | 84 uint32_t rs1, rs2, rs3; in poly1305_process() local
|
| /third_party/node/deps/v8/src/execution/riscv64/ |
| D | simulator-riscv64.h | 132 inline float fsgnj32(float rs1, float rs2, bool n, bool x) { in fsgnj32()
147 inline double fsgnj64(double rs1, double rs2, bool n, bool x) { in fsgnj64()
560 inline int64_t rs1() const { return get_register(rs1_reg()); } in rs1() function
|
| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeRISCV_common.c | 66 #define RS1(rs1) ((sljit_ins)reg_map[rs1] << 15) argument
69 #define FRS1(rs1) ((sljit_ins)freg_map[rs1] << 15) argument
|
| /third_party/selinux/libsepol/src/ |
| D | module_to_cil.c | 917 struct role_set *rs1 = NULL, *rs2; in search_attr_list() local
|