1 /*
2 * Copyright(c) 2015 - 2018 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48 #include <linux/spinlock.h>
49 #include <linux/seqlock.h>
50 #include <linux/netdevice.h>
51 #include <linux/moduleparam.h>
52 #include <linux/bitops.h>
53 #include <linux/timer.h>
54 #include <linux/vmalloc.h>
55 #include <linux/highmem.h>
56
57 #include "hfi.h"
58 #include "common.h"
59 #include "qp.h"
60 #include "sdma.h"
61 #include "iowait.h"
62 #include "trace.h"
63
64 /* must be a power of 2 >= 64 <= 32768 */
65 #define SDMA_DESCQ_CNT 2048
66 #define SDMA_DESC_INTR 64
67 #define INVALID_TAIL 0xffff
68 #define SDMA_PAD max_t(size_t, MAX_16B_PADDING, sizeof(u32))
69
70 static uint sdma_descq_cnt = SDMA_DESCQ_CNT;
71 module_param(sdma_descq_cnt, uint, S_IRUGO);
72 MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries");
73
74 static uint sdma_idle_cnt = 250;
75 module_param(sdma_idle_cnt, uint, S_IRUGO);
76 MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)");
77
78 uint mod_num_sdma;
79 module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO);
80 MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");
81
82 static uint sdma_desct_intr = SDMA_DESC_INTR;
83 module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR);
84 MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt");
85
86 #define SDMA_WAIT_BATCH_SIZE 20
87 /* max wait time for a SDMA engine to indicate it has halted */
88 #define SDMA_ERR_HALT_TIMEOUT 10 /* ms */
89 /* all SDMA engine errors that cause a halt */
90
91 #define SD(name) SEND_DMA_##name
92 #define ALL_SDMA_ENG_HALT_ERRS \
93 (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \
94 | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \
95 | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \
96 | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \
97 | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \
98 | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \
99 | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \
100 | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \
101 | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \
102 | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \
103 | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \
104 | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \
105 | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \
106 | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \
107 | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \
108 | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \
109 | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \
110 | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK))
111
112 /* sdma_sendctrl operations */
113 #define SDMA_SENDCTRL_OP_ENABLE BIT(0)
114 #define SDMA_SENDCTRL_OP_INTENABLE BIT(1)
115 #define SDMA_SENDCTRL_OP_HALT BIT(2)
116 #define SDMA_SENDCTRL_OP_CLEANUP BIT(3)
117
118 /* handle long defines */
119 #define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \
120 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK
121 #define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \
122 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT
123
124 static const char * const sdma_state_names[] = {
125 [sdma_state_s00_hw_down] = "s00_HwDown",
126 [sdma_state_s10_hw_start_up_halt_wait] = "s10_HwStartUpHaltWait",
127 [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait",
128 [sdma_state_s20_idle] = "s20_Idle",
129 [sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait",
130 [sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait",
131 [sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait",
132 [sdma_state_s60_idle_halt_wait] = "s60_IdleHaltWait",
133 [sdma_state_s80_hw_freeze] = "s80_HwFreeze",
134 [sdma_state_s82_freeze_sw_clean] = "s82_FreezeSwClean",
135 [sdma_state_s99_running] = "s99_Running",
136 };
137
138 #ifdef CONFIG_SDMA_VERBOSITY
139 static const char * const sdma_event_names[] = {
140 [sdma_event_e00_go_hw_down] = "e00_GoHwDown",
141 [sdma_event_e10_go_hw_start] = "e10_GoHwStart",
142 [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone",
143 [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone",
144 [sdma_event_e30_go_running] = "e30_GoRunning",
145 [sdma_event_e40_sw_cleaned] = "e40_SwCleaned",
146 [sdma_event_e50_hw_cleaned] = "e50_HwCleaned",
147 [sdma_event_e60_hw_halted] = "e60_HwHalted",
148 [sdma_event_e70_go_idle] = "e70_GoIdle",
149 [sdma_event_e80_hw_freeze] = "e80_HwFreeze",
150 [sdma_event_e81_hw_frozen] = "e81_HwFrozen",
151 [sdma_event_e82_hw_unfreeze] = "e82_HwUnfreeze",
152 [sdma_event_e85_link_down] = "e85_LinkDown",
153 [sdma_event_e90_sw_halted] = "e90_SwHalted",
154 };
155 #endif
156
157 static const struct sdma_set_state_action sdma_action_table[] = {
158 [sdma_state_s00_hw_down] = {
159 .go_s99_running_tofalse = 1,
160 .op_enable = 0,
161 .op_intenable = 0,
162 .op_halt = 0,
163 .op_cleanup = 0,
164 },
165 [sdma_state_s10_hw_start_up_halt_wait] = {
166 .op_enable = 0,
167 .op_intenable = 0,
168 .op_halt = 1,
169 .op_cleanup = 0,
170 },
171 [sdma_state_s15_hw_start_up_clean_wait] = {
172 .op_enable = 0,
173 .op_intenable = 1,
174 .op_halt = 0,
175 .op_cleanup = 1,
176 },
177 [sdma_state_s20_idle] = {
178 .op_enable = 0,
179 .op_intenable = 1,
180 .op_halt = 0,
181 .op_cleanup = 0,
182 },
183 [sdma_state_s30_sw_clean_up_wait] = {
184 .op_enable = 0,
185 .op_intenable = 0,
186 .op_halt = 0,
187 .op_cleanup = 0,
188 },
189 [sdma_state_s40_hw_clean_up_wait] = {
190 .op_enable = 0,
191 .op_intenable = 0,
192 .op_halt = 0,
193 .op_cleanup = 1,
194 },
195 [sdma_state_s50_hw_halt_wait] = {
196 .op_enable = 0,
197 .op_intenable = 0,
198 .op_halt = 0,
199 .op_cleanup = 0,
200 },
201 [sdma_state_s60_idle_halt_wait] = {
202 .go_s99_running_tofalse = 1,
203 .op_enable = 0,
204 .op_intenable = 0,
205 .op_halt = 1,
206 .op_cleanup = 0,
207 },
208 [sdma_state_s80_hw_freeze] = {
209 .op_enable = 0,
210 .op_intenable = 0,
211 .op_halt = 0,
212 .op_cleanup = 0,
213 },
214 [sdma_state_s82_freeze_sw_clean] = {
215 .op_enable = 0,
216 .op_intenable = 0,
217 .op_halt = 0,
218 .op_cleanup = 0,
219 },
220 [sdma_state_s99_running] = {
221 .op_enable = 1,
222 .op_intenable = 1,
223 .op_halt = 0,
224 .op_cleanup = 0,
225 .go_s99_running_totrue = 1,
226 },
227 };
228
229 #define SDMA_TAIL_UPDATE_THRESH 0x1F
230
231 /* declare all statics here rather than keep sorting */
232 static void sdma_complete(struct kref *);
233 static void sdma_finalput(struct sdma_state *);
234 static void sdma_get(struct sdma_state *);
235 static void sdma_hw_clean_up_task(struct tasklet_struct *);
236 static void sdma_put(struct sdma_state *);
237 static void sdma_set_state(struct sdma_engine *, enum sdma_states);
238 static void sdma_start_hw_clean_up(struct sdma_engine *);
239 static void sdma_sw_clean_up_task(struct tasklet_struct *);
240 static void sdma_sendctrl(struct sdma_engine *, unsigned);
241 static void init_sdma_regs(struct sdma_engine *, u32, uint);
242 static void sdma_process_event(
243 struct sdma_engine *sde,
244 enum sdma_events event);
245 static void __sdma_process_event(
246 struct sdma_engine *sde,
247 enum sdma_events event);
248 static void dump_sdma_state(struct sdma_engine *sde);
249 static void sdma_make_progress(struct sdma_engine *sde, u64 status);
250 static void sdma_desc_avail(struct sdma_engine *sde, uint avail);
251 static void sdma_flush_descq(struct sdma_engine *sde);
252
253 /**
254 * sdma_state_name() - return state string from enum
255 * @state: state
256 */
sdma_state_name(enum sdma_states state)257 static const char *sdma_state_name(enum sdma_states state)
258 {
259 return sdma_state_names[state];
260 }
261
sdma_get(struct sdma_state * ss)262 static void sdma_get(struct sdma_state *ss)
263 {
264 kref_get(&ss->kref);
265 }
266
sdma_complete(struct kref * kref)267 static void sdma_complete(struct kref *kref)
268 {
269 struct sdma_state *ss =
270 container_of(kref, struct sdma_state, kref);
271
272 complete(&ss->comp);
273 }
274
sdma_put(struct sdma_state * ss)275 static void sdma_put(struct sdma_state *ss)
276 {
277 kref_put(&ss->kref, sdma_complete);
278 }
279
sdma_finalput(struct sdma_state * ss)280 static void sdma_finalput(struct sdma_state *ss)
281 {
282 sdma_put(ss);
283 wait_for_completion(&ss->comp);
284 }
285
write_sde_csr(struct sdma_engine * sde,u32 offset0,u64 value)286 static inline void write_sde_csr(
287 struct sdma_engine *sde,
288 u32 offset0,
289 u64 value)
290 {
291 write_kctxt_csr(sde->dd, sde->this_idx, offset0, value);
292 }
293
read_sde_csr(struct sdma_engine * sde,u32 offset0)294 static inline u64 read_sde_csr(
295 struct sdma_engine *sde,
296 u32 offset0)
297 {
298 return read_kctxt_csr(sde->dd, sde->this_idx, offset0);
299 }
300
301 /*
302 * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for
303 * sdma engine 'sde' to drop to 0.
304 */
sdma_wait_for_packet_egress(struct sdma_engine * sde,int pause)305 static void sdma_wait_for_packet_egress(struct sdma_engine *sde,
306 int pause)
307 {
308 u64 off = 8 * sde->this_idx;
309 struct hfi1_devdata *dd = sde->dd;
310 int lcnt = 0;
311 u64 reg_prev;
312 u64 reg = 0;
313
314 while (1) {
315 reg_prev = reg;
316 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS);
317
318 reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK;
319 reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT;
320 if (reg == 0)
321 break;
322 /* counter is reest if accupancy count changes */
323 if (reg != reg_prev)
324 lcnt = 0;
325 if (lcnt++ > 500) {
326 /* timed out - bounce the link */
327 dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n",
328 __func__, sde->this_idx, (u32)reg);
329 queue_work(dd->pport->link_wq,
330 &dd->pport->link_bounce_work);
331 break;
332 }
333 udelay(1);
334 }
335 }
336
337 /*
338 * sdma_wait() - wait for packet egress to complete for all SDMA engines,
339 * and pause for credit return.
340 */
sdma_wait(struct hfi1_devdata * dd)341 void sdma_wait(struct hfi1_devdata *dd)
342 {
343 int i;
344
345 for (i = 0; i < dd->num_sdma; i++) {
346 struct sdma_engine *sde = &dd->per_sdma[i];
347
348 sdma_wait_for_packet_egress(sde, 0);
349 }
350 }
351
sdma_set_desc_cnt(struct sdma_engine * sde,unsigned cnt)352 static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt)
353 {
354 u64 reg;
355
356 if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT))
357 return;
358 reg = cnt;
359 reg &= SD(DESC_CNT_CNT_MASK);
360 reg <<= SD(DESC_CNT_CNT_SHIFT);
361 write_sde_csr(sde, SD(DESC_CNT), reg);
362 }
363
complete_tx(struct sdma_engine * sde,struct sdma_txreq * tx,int res)364 static inline void complete_tx(struct sdma_engine *sde,
365 struct sdma_txreq *tx,
366 int res)
367 {
368 /* protect against complete modifying */
369 struct iowait *wait = tx->wait;
370 callback_t complete = tx->complete;
371
372 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
373 trace_hfi1_sdma_out_sn(sde, tx->sn);
374 if (WARN_ON_ONCE(sde->head_sn != tx->sn))
375 dd_dev_err(sde->dd, "expected %llu got %llu\n",
376 sde->head_sn, tx->sn);
377 sde->head_sn++;
378 #endif
379 __sdma_txclean(sde->dd, tx);
380 if (complete)
381 (*complete)(tx, res);
382 if (iowait_sdma_dec(wait))
383 iowait_drain_wakeup(wait);
384 }
385
386 /*
387 * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status
388 *
389 * Depending on timing there can be txreqs in two places:
390 * - in the descq ring
391 * - in the flush list
392 *
393 * To avoid ordering issues the descq ring needs to be flushed
394 * first followed by the flush list.
395 *
396 * This routine is called from two places
397 * - From a work queue item
398 * - Directly from the state machine just before setting the
399 * state to running
400 *
401 * Must be called with head_lock held
402 *
403 */
sdma_flush(struct sdma_engine * sde)404 static void sdma_flush(struct sdma_engine *sde)
405 {
406 struct sdma_txreq *txp, *txp_next;
407 LIST_HEAD(flushlist);
408 unsigned long flags;
409 uint seq;
410
411 /* flush from head to tail */
412 sdma_flush_descq(sde);
413 spin_lock_irqsave(&sde->flushlist_lock, flags);
414 /* copy flush list */
415 list_splice_init(&sde->flushlist, &flushlist);
416 spin_unlock_irqrestore(&sde->flushlist_lock, flags);
417 /* flush from flush list */
418 list_for_each_entry_safe(txp, txp_next, &flushlist, list)
419 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
420 /* wakeup QPs orphaned on the dmawait list */
421 do {
422 struct iowait *w, *nw;
423
424 seq = read_seqbegin(&sde->waitlock);
425 if (!list_empty(&sde->dmawait)) {
426 write_seqlock(&sde->waitlock);
427 list_for_each_entry_safe(w, nw, &sde->dmawait, list) {
428 if (w->wakeup) {
429 w->wakeup(w, SDMA_AVAIL_REASON);
430 list_del_init(&w->list);
431 }
432 }
433 write_sequnlock(&sde->waitlock);
434 }
435 } while (read_seqretry(&sde->waitlock, seq));
436 }
437
438 /*
439 * Fields a work request for flushing the descq ring
440 * and the flush list
441 *
442 * If the engine has been brought to running during
443 * the scheduling delay, the flush is ignored, assuming
444 * that the process of bringing the engine to running
445 * would have done this flush prior to going to running.
446 *
447 */
sdma_field_flush(struct work_struct * work)448 static void sdma_field_flush(struct work_struct *work)
449 {
450 unsigned long flags;
451 struct sdma_engine *sde =
452 container_of(work, struct sdma_engine, flush_worker);
453
454 write_seqlock_irqsave(&sde->head_lock, flags);
455 if (!__sdma_running(sde))
456 sdma_flush(sde);
457 write_sequnlock_irqrestore(&sde->head_lock, flags);
458 }
459
sdma_err_halt_wait(struct work_struct * work)460 static void sdma_err_halt_wait(struct work_struct *work)
461 {
462 struct sdma_engine *sde = container_of(work, struct sdma_engine,
463 err_halt_worker);
464 u64 statuscsr;
465 unsigned long timeout;
466
467 timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT);
468 while (1) {
469 statuscsr = read_sde_csr(sde, SD(STATUS));
470 statuscsr &= SD(STATUS_ENG_HALTED_SMASK);
471 if (statuscsr)
472 break;
473 if (time_after(jiffies, timeout)) {
474 dd_dev_err(sde->dd,
475 "SDMA engine %d - timeout waiting for engine to halt\n",
476 sde->this_idx);
477 /*
478 * Continue anyway. This could happen if there was
479 * an uncorrectable error in the wrong spot.
480 */
481 break;
482 }
483 usleep_range(80, 120);
484 }
485
486 sdma_process_event(sde, sdma_event_e15_hw_halt_done);
487 }
488
sdma_err_progress_check_schedule(struct sdma_engine * sde)489 static void sdma_err_progress_check_schedule(struct sdma_engine *sde)
490 {
491 if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) {
492 unsigned index;
493 struct hfi1_devdata *dd = sde->dd;
494
495 for (index = 0; index < dd->num_sdma; index++) {
496 struct sdma_engine *curr_sdma = &dd->per_sdma[index];
497
498 if (curr_sdma != sde)
499 curr_sdma->progress_check_head =
500 curr_sdma->descq_head;
501 }
502 dd_dev_err(sde->dd,
503 "SDMA engine %d - check scheduled\n",
504 sde->this_idx);
505 mod_timer(&sde->err_progress_check_timer, jiffies + 10);
506 }
507 }
508
sdma_err_progress_check(struct timer_list * t)509 static void sdma_err_progress_check(struct timer_list *t)
510 {
511 unsigned index;
512 struct sdma_engine *sde = from_timer(sde, t, err_progress_check_timer);
513
514 dd_dev_err(sde->dd, "SDE progress check event\n");
515 for (index = 0; index < sde->dd->num_sdma; index++) {
516 struct sdma_engine *curr_sde = &sde->dd->per_sdma[index];
517 unsigned long flags;
518
519 /* check progress on each engine except the current one */
520 if (curr_sde == sde)
521 continue;
522 /*
523 * We must lock interrupts when acquiring sde->lock,
524 * to avoid a deadlock if interrupt triggers and spins on
525 * the same lock on same CPU
526 */
527 spin_lock_irqsave(&curr_sde->tail_lock, flags);
528 write_seqlock(&curr_sde->head_lock);
529
530 /* skip non-running queues */
531 if (curr_sde->state.current_state != sdma_state_s99_running) {
532 write_sequnlock(&curr_sde->head_lock);
533 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
534 continue;
535 }
536
537 if ((curr_sde->descq_head != curr_sde->descq_tail) &&
538 (curr_sde->descq_head ==
539 curr_sde->progress_check_head))
540 __sdma_process_event(curr_sde,
541 sdma_event_e90_sw_halted);
542 write_sequnlock(&curr_sde->head_lock);
543 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
544 }
545 schedule_work(&sde->err_halt_worker);
546 }
547
sdma_hw_clean_up_task(struct tasklet_struct * t)548 static void sdma_hw_clean_up_task(struct tasklet_struct *t)
549 {
550 struct sdma_engine *sde = from_tasklet(sde, t,
551 sdma_hw_clean_up_task);
552 u64 statuscsr;
553
554 while (1) {
555 #ifdef CONFIG_SDMA_VERBOSITY
556 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
557 sde->this_idx, slashstrip(__FILE__), __LINE__,
558 __func__);
559 #endif
560 statuscsr = read_sde_csr(sde, SD(STATUS));
561 statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK);
562 if (statuscsr)
563 break;
564 udelay(10);
565 }
566
567 sdma_process_event(sde, sdma_event_e25_hw_clean_up_done);
568 }
569
get_txhead(struct sdma_engine * sde)570 static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde)
571 {
572 return sde->tx_ring[sde->tx_head & sde->sdma_mask];
573 }
574
575 /*
576 * flush ring for recovery
577 */
sdma_flush_descq(struct sdma_engine * sde)578 static void sdma_flush_descq(struct sdma_engine *sde)
579 {
580 u16 head, tail;
581 int progress = 0;
582 struct sdma_txreq *txp = get_txhead(sde);
583
584 /* The reason for some of the complexity of this code is that
585 * not all descriptors have corresponding txps. So, we have to
586 * be able to skip over descs until we wander into the range of
587 * the next txp on the list.
588 */
589 head = sde->descq_head & sde->sdma_mask;
590 tail = sde->descq_tail & sde->sdma_mask;
591 while (head != tail) {
592 /* advance head, wrap if needed */
593 head = ++sde->descq_head & sde->sdma_mask;
594 /* if now past this txp's descs, do the callback */
595 if (txp && txp->next_descq_idx == head) {
596 /* remove from list */
597 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
598 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
599 trace_hfi1_sdma_progress(sde, head, tail, txp);
600 txp = get_txhead(sde);
601 }
602 progress++;
603 }
604 if (progress)
605 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
606 }
607
sdma_sw_clean_up_task(struct tasklet_struct * t)608 static void sdma_sw_clean_up_task(struct tasklet_struct *t)
609 {
610 struct sdma_engine *sde = from_tasklet(sde, t, sdma_sw_clean_up_task);
611 unsigned long flags;
612
613 spin_lock_irqsave(&sde->tail_lock, flags);
614 write_seqlock(&sde->head_lock);
615
616 /*
617 * At this point, the following should always be true:
618 * - We are halted, so no more descriptors are getting retired.
619 * - We are not running, so no one is submitting new work.
620 * - Only we can send the e40_sw_cleaned, so we can't start
621 * running again until we say so. So, the active list and
622 * descq are ours to play with.
623 */
624
625 /*
626 * In the error clean up sequence, software clean must be called
627 * before the hardware clean so we can use the hardware head in
628 * the progress routine. A hardware clean or SPC unfreeze will
629 * reset the hardware head.
630 *
631 * Process all retired requests. The progress routine will use the
632 * latest physical hardware head - we are not running so speed does
633 * not matter.
634 */
635 sdma_make_progress(sde, 0);
636
637 sdma_flush(sde);
638
639 /*
640 * Reset our notion of head and tail.
641 * Note that the HW registers have been reset via an earlier
642 * clean up.
643 */
644 sde->descq_tail = 0;
645 sde->descq_head = 0;
646 sde->desc_avail = sdma_descq_freecnt(sde);
647 *sde->head_dma = 0;
648
649 __sdma_process_event(sde, sdma_event_e40_sw_cleaned);
650
651 write_sequnlock(&sde->head_lock);
652 spin_unlock_irqrestore(&sde->tail_lock, flags);
653 }
654
sdma_sw_tear_down(struct sdma_engine * sde)655 static void sdma_sw_tear_down(struct sdma_engine *sde)
656 {
657 struct sdma_state *ss = &sde->state;
658
659 /* Releasing this reference means the state machine has stopped. */
660 sdma_put(ss);
661
662 /* stop waiting for all unfreeze events to complete */
663 atomic_set(&sde->dd->sdma_unfreeze_count, -1);
664 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
665 }
666
sdma_start_hw_clean_up(struct sdma_engine * sde)667 static void sdma_start_hw_clean_up(struct sdma_engine *sde)
668 {
669 tasklet_hi_schedule(&sde->sdma_hw_clean_up_task);
670 }
671
sdma_set_state(struct sdma_engine * sde,enum sdma_states next_state)672 static void sdma_set_state(struct sdma_engine *sde,
673 enum sdma_states next_state)
674 {
675 struct sdma_state *ss = &sde->state;
676 const struct sdma_set_state_action *action = sdma_action_table;
677 unsigned op = 0;
678
679 trace_hfi1_sdma_state(
680 sde,
681 sdma_state_names[ss->current_state],
682 sdma_state_names[next_state]);
683
684 /* debugging bookkeeping */
685 ss->previous_state = ss->current_state;
686 ss->previous_op = ss->current_op;
687 ss->current_state = next_state;
688
689 if (ss->previous_state != sdma_state_s99_running &&
690 next_state == sdma_state_s99_running)
691 sdma_flush(sde);
692
693 if (action[next_state].op_enable)
694 op |= SDMA_SENDCTRL_OP_ENABLE;
695
696 if (action[next_state].op_intenable)
697 op |= SDMA_SENDCTRL_OP_INTENABLE;
698
699 if (action[next_state].op_halt)
700 op |= SDMA_SENDCTRL_OP_HALT;
701
702 if (action[next_state].op_cleanup)
703 op |= SDMA_SENDCTRL_OP_CLEANUP;
704
705 if (action[next_state].go_s99_running_tofalse)
706 ss->go_s99_running = 0;
707
708 if (action[next_state].go_s99_running_totrue)
709 ss->go_s99_running = 1;
710
711 ss->current_op = op;
712 sdma_sendctrl(sde, ss->current_op);
713 }
714
715 /**
716 * sdma_get_descq_cnt() - called when device probed
717 *
718 * Return a validated descq count.
719 *
720 * This is currently only used in the verbs initialization to build the tx
721 * list.
722 *
723 * This will probably be deleted in favor of a more scalable approach to
724 * alloc tx's.
725 *
726 */
sdma_get_descq_cnt(void)727 u16 sdma_get_descq_cnt(void)
728 {
729 u16 count = sdma_descq_cnt;
730
731 if (!count)
732 return SDMA_DESCQ_CNT;
733 /* count must be a power of 2 greater than 64 and less than
734 * 32768. Otherwise return default.
735 */
736 if (!is_power_of_2(count))
737 return SDMA_DESCQ_CNT;
738 if (count < 64 || count > 32768)
739 return SDMA_DESCQ_CNT;
740 return count;
741 }
742
743 /**
744 * sdma_engine_get_vl() - return vl for a given sdma engine
745 * @sde: sdma engine
746 *
747 * This function returns the vl mapped to a given engine, or an error if
748 * the mapping can't be found. The mapping fields are protected by RCU.
749 */
sdma_engine_get_vl(struct sdma_engine * sde)750 int sdma_engine_get_vl(struct sdma_engine *sde)
751 {
752 struct hfi1_devdata *dd = sde->dd;
753 struct sdma_vl_map *m;
754 u8 vl;
755
756 if (sde->this_idx >= TXE_NUM_SDMA_ENGINES)
757 return -EINVAL;
758
759 rcu_read_lock();
760 m = rcu_dereference(dd->sdma_map);
761 if (unlikely(!m)) {
762 rcu_read_unlock();
763 return -EINVAL;
764 }
765 vl = m->engine_to_vl[sde->this_idx];
766 rcu_read_unlock();
767
768 return vl;
769 }
770
771 /**
772 * sdma_select_engine_vl() - select sdma engine
773 * @dd: devdata
774 * @selector: a spreading factor
775 * @vl: this vl
776 *
777 *
778 * This function returns an engine based on the selector and a vl. The
779 * mapping fields are protected by RCU.
780 */
sdma_select_engine_vl(struct hfi1_devdata * dd,u32 selector,u8 vl)781 struct sdma_engine *sdma_select_engine_vl(
782 struct hfi1_devdata *dd,
783 u32 selector,
784 u8 vl)
785 {
786 struct sdma_vl_map *m;
787 struct sdma_map_elem *e;
788 struct sdma_engine *rval;
789
790 /* NOTE This should only happen if SC->VL changed after the initial
791 * checks on the QP/AH
792 * Default will return engine 0 below
793 */
794 if (vl >= num_vls) {
795 rval = NULL;
796 goto done;
797 }
798
799 rcu_read_lock();
800 m = rcu_dereference(dd->sdma_map);
801 if (unlikely(!m)) {
802 rcu_read_unlock();
803 return &dd->per_sdma[0];
804 }
805 e = m->map[vl & m->mask];
806 rval = e->sde[selector & e->mask];
807 rcu_read_unlock();
808
809 done:
810 rval = !rval ? &dd->per_sdma[0] : rval;
811 trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx);
812 return rval;
813 }
814
815 /**
816 * sdma_select_engine_sc() - select sdma engine
817 * @dd: devdata
818 * @selector: a spreading factor
819 * @sc5: the 5 bit sc
820 *
821 *
822 * This function returns an engine based on the selector and an sc.
823 */
sdma_select_engine_sc(struct hfi1_devdata * dd,u32 selector,u8 sc5)824 struct sdma_engine *sdma_select_engine_sc(
825 struct hfi1_devdata *dd,
826 u32 selector,
827 u8 sc5)
828 {
829 u8 vl = sc_to_vlt(dd, sc5);
830
831 return sdma_select_engine_vl(dd, selector, vl);
832 }
833
834 struct sdma_rht_map_elem {
835 u32 mask;
836 u8 ctr;
837 struct sdma_engine *sde[];
838 };
839
840 struct sdma_rht_node {
841 unsigned long cpu_id;
842 struct sdma_rht_map_elem *map[HFI1_MAX_VLS_SUPPORTED];
843 struct rhash_head node;
844 };
845
846 #define NR_CPUS_HINT 192
847
848 static const struct rhashtable_params sdma_rht_params = {
849 .nelem_hint = NR_CPUS_HINT,
850 .head_offset = offsetof(struct sdma_rht_node, node),
851 .key_offset = offsetof(struct sdma_rht_node, cpu_id),
852 .key_len = sizeof_field(struct sdma_rht_node, cpu_id),
853 .max_size = NR_CPUS,
854 .min_size = 8,
855 .automatic_shrinking = true,
856 };
857
858 /*
859 * sdma_select_user_engine() - select sdma engine based on user setup
860 * @dd: devdata
861 * @selector: a spreading factor
862 * @vl: this vl
863 *
864 * This function returns an sdma engine for a user sdma request.
865 * User defined sdma engine affinity setting is honored when applicable,
866 * otherwise system default sdma engine mapping is used. To ensure correct
867 * ordering, the mapping from <selector, vl> to sde must remain unchanged.
868 */
sdma_select_user_engine(struct hfi1_devdata * dd,u32 selector,u8 vl)869 struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd,
870 u32 selector, u8 vl)
871 {
872 struct sdma_rht_node *rht_node;
873 struct sdma_engine *sde = NULL;
874 unsigned long cpu_id;
875
876 /*
877 * To ensure that always the same sdma engine(s) will be
878 * selected make sure the process is pinned to this CPU only.
879 */
880 if (current->nr_cpus_allowed != 1)
881 goto out;
882
883 rcu_read_lock();
884 cpu_id = smp_processor_id();
885 rht_node = rhashtable_lookup(dd->sdma_rht, &cpu_id,
886 sdma_rht_params);
887
888 if (rht_node && rht_node->map[vl]) {
889 struct sdma_rht_map_elem *map = rht_node->map[vl];
890
891 sde = map->sde[selector & map->mask];
892 }
893 rcu_read_unlock();
894
895 if (sde)
896 return sde;
897
898 out:
899 return sdma_select_engine_vl(dd, selector, vl);
900 }
901
sdma_populate_sde_map(struct sdma_rht_map_elem * map)902 static void sdma_populate_sde_map(struct sdma_rht_map_elem *map)
903 {
904 int i;
905
906 for (i = 0; i < roundup_pow_of_two(map->ctr ? : 1) - map->ctr; i++)
907 map->sde[map->ctr + i] = map->sde[i];
908 }
909
sdma_cleanup_sde_map(struct sdma_rht_map_elem * map,struct sdma_engine * sde)910 static void sdma_cleanup_sde_map(struct sdma_rht_map_elem *map,
911 struct sdma_engine *sde)
912 {
913 unsigned int i, pow;
914
915 /* only need to check the first ctr entries for a match */
916 for (i = 0; i < map->ctr; i++) {
917 if (map->sde[i] == sde) {
918 memmove(&map->sde[i], &map->sde[i + 1],
919 (map->ctr - i - 1) * sizeof(map->sde[0]));
920 map->ctr--;
921 pow = roundup_pow_of_two(map->ctr ? : 1);
922 map->mask = pow - 1;
923 sdma_populate_sde_map(map);
924 break;
925 }
926 }
927 }
928
929 /*
930 * Prevents concurrent reads and writes of the sdma engine cpu_mask
931 */
932 static DEFINE_MUTEX(process_to_sde_mutex);
933
sdma_set_cpu_to_sde_map(struct sdma_engine * sde,const char * buf,size_t count)934 ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf,
935 size_t count)
936 {
937 struct hfi1_devdata *dd = sde->dd;
938 cpumask_var_t mask, new_mask;
939 unsigned long cpu;
940 int ret, vl, sz;
941 struct sdma_rht_node *rht_node;
942
943 vl = sdma_engine_get_vl(sde);
944 if (unlikely(vl < 0 || vl >= ARRAY_SIZE(rht_node->map)))
945 return -EINVAL;
946
947 ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
948 if (!ret)
949 return -ENOMEM;
950
951 ret = zalloc_cpumask_var(&new_mask, GFP_KERNEL);
952 if (!ret) {
953 free_cpumask_var(mask);
954 return -ENOMEM;
955 }
956 ret = cpulist_parse(buf, mask);
957 if (ret)
958 goto out_free;
959
960 if (!cpumask_subset(mask, cpu_online_mask)) {
961 dd_dev_warn(sde->dd, "Invalid CPU mask\n");
962 ret = -EINVAL;
963 goto out_free;
964 }
965
966 sz = sizeof(struct sdma_rht_map_elem) +
967 (TXE_NUM_SDMA_ENGINES * sizeof(struct sdma_engine *));
968
969 mutex_lock(&process_to_sde_mutex);
970
971 for_each_cpu(cpu, mask) {
972 /* Check if we have this already mapped */
973 if (cpumask_test_cpu(cpu, &sde->cpu_mask)) {
974 cpumask_set_cpu(cpu, new_mask);
975 continue;
976 }
977
978 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu,
979 sdma_rht_params);
980 if (!rht_node) {
981 rht_node = kzalloc(sizeof(*rht_node), GFP_KERNEL);
982 if (!rht_node) {
983 ret = -ENOMEM;
984 goto out;
985 }
986
987 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL);
988 if (!rht_node->map[vl]) {
989 kfree(rht_node);
990 ret = -ENOMEM;
991 goto out;
992 }
993 rht_node->cpu_id = cpu;
994 rht_node->map[vl]->mask = 0;
995 rht_node->map[vl]->ctr = 1;
996 rht_node->map[vl]->sde[0] = sde;
997
998 ret = rhashtable_insert_fast(dd->sdma_rht,
999 &rht_node->node,
1000 sdma_rht_params);
1001 if (ret) {
1002 kfree(rht_node->map[vl]);
1003 kfree(rht_node);
1004 dd_dev_err(sde->dd, "Failed to set process to sde affinity for cpu %lu\n",
1005 cpu);
1006 goto out;
1007 }
1008
1009 } else {
1010 int ctr, pow;
1011
1012 /* Add new user mappings */
1013 if (!rht_node->map[vl])
1014 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL);
1015
1016 if (!rht_node->map[vl]) {
1017 ret = -ENOMEM;
1018 goto out;
1019 }
1020
1021 rht_node->map[vl]->ctr++;
1022 ctr = rht_node->map[vl]->ctr;
1023 rht_node->map[vl]->sde[ctr - 1] = sde;
1024 pow = roundup_pow_of_two(ctr);
1025 rht_node->map[vl]->mask = pow - 1;
1026
1027 /* Populate the sde map table */
1028 sdma_populate_sde_map(rht_node->map[vl]);
1029 }
1030 cpumask_set_cpu(cpu, new_mask);
1031 }
1032
1033 /* Clean up old mappings */
1034 for_each_cpu(cpu, cpu_online_mask) {
1035 struct sdma_rht_node *rht_node;
1036
1037 /* Don't cleanup sdes that are set in the new mask */
1038 if (cpumask_test_cpu(cpu, mask))
1039 continue;
1040
1041 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu,
1042 sdma_rht_params);
1043 if (rht_node) {
1044 bool empty = true;
1045 int i;
1046
1047 /* Remove mappings for old sde */
1048 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1049 if (rht_node->map[i])
1050 sdma_cleanup_sde_map(rht_node->map[i],
1051 sde);
1052
1053 /* Free empty hash table entries */
1054 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) {
1055 if (!rht_node->map[i])
1056 continue;
1057
1058 if (rht_node->map[i]->ctr) {
1059 empty = false;
1060 break;
1061 }
1062 }
1063
1064 if (empty) {
1065 ret = rhashtable_remove_fast(dd->sdma_rht,
1066 &rht_node->node,
1067 sdma_rht_params);
1068 WARN_ON(ret);
1069
1070 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1071 kfree(rht_node->map[i]);
1072
1073 kfree(rht_node);
1074 }
1075 }
1076 }
1077
1078 cpumask_copy(&sde->cpu_mask, new_mask);
1079 out:
1080 mutex_unlock(&process_to_sde_mutex);
1081 out_free:
1082 free_cpumask_var(mask);
1083 free_cpumask_var(new_mask);
1084 return ret ? : strnlen(buf, PAGE_SIZE);
1085 }
1086
sdma_get_cpu_to_sde_map(struct sdma_engine * sde,char * buf)1087 ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf)
1088 {
1089 mutex_lock(&process_to_sde_mutex);
1090 if (cpumask_empty(&sde->cpu_mask))
1091 snprintf(buf, PAGE_SIZE, "%s\n", "empty");
1092 else
1093 cpumap_print_to_pagebuf(true, buf, &sde->cpu_mask);
1094 mutex_unlock(&process_to_sde_mutex);
1095 return strnlen(buf, PAGE_SIZE);
1096 }
1097
sdma_rht_free(void * ptr,void * arg)1098 static void sdma_rht_free(void *ptr, void *arg)
1099 {
1100 struct sdma_rht_node *rht_node = ptr;
1101 int i;
1102
1103 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1104 kfree(rht_node->map[i]);
1105
1106 kfree(rht_node);
1107 }
1108
1109 /**
1110 * sdma_seqfile_dump_cpu_list() - debugfs dump the cpu to sdma mappings
1111 * @s: seq file
1112 * @dd: hfi1_devdata
1113 * @cpuid: cpu id
1114 *
1115 * This routine dumps the process to sde mappings per cpu
1116 */
sdma_seqfile_dump_cpu_list(struct seq_file * s,struct hfi1_devdata * dd,unsigned long cpuid)1117 void sdma_seqfile_dump_cpu_list(struct seq_file *s,
1118 struct hfi1_devdata *dd,
1119 unsigned long cpuid)
1120 {
1121 struct sdma_rht_node *rht_node;
1122 int i, j;
1123
1124 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpuid,
1125 sdma_rht_params);
1126 if (!rht_node)
1127 return;
1128
1129 seq_printf(s, "cpu%3lu: ", cpuid);
1130 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) {
1131 if (!rht_node->map[i] || !rht_node->map[i]->ctr)
1132 continue;
1133
1134 seq_printf(s, " vl%d: [", i);
1135
1136 for (j = 0; j < rht_node->map[i]->ctr; j++) {
1137 if (!rht_node->map[i]->sde[j])
1138 continue;
1139
1140 if (j > 0)
1141 seq_puts(s, ",");
1142
1143 seq_printf(s, " sdma%2d",
1144 rht_node->map[i]->sde[j]->this_idx);
1145 }
1146 seq_puts(s, " ]");
1147 }
1148
1149 seq_puts(s, "\n");
1150 }
1151
1152 /*
1153 * Free the indicated map struct
1154 */
sdma_map_free(struct sdma_vl_map * m)1155 static void sdma_map_free(struct sdma_vl_map *m)
1156 {
1157 int i;
1158
1159 for (i = 0; m && i < m->actual_vls; i++)
1160 kfree(m->map[i]);
1161 kfree(m);
1162 }
1163
1164 /*
1165 * Handle RCU callback
1166 */
sdma_map_rcu_callback(struct rcu_head * list)1167 static void sdma_map_rcu_callback(struct rcu_head *list)
1168 {
1169 struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list);
1170
1171 sdma_map_free(m);
1172 }
1173
1174 /**
1175 * sdma_map_init - called when # vls change
1176 * @dd: hfi1_devdata
1177 * @port: port number
1178 * @num_vls: number of vls
1179 * @vl_engines: per vl engine mapping (optional)
1180 *
1181 * This routine changes the mapping based on the number of vls.
1182 *
1183 * vl_engines is used to specify a non-uniform vl/engine loading. NULL
1184 * implies auto computing the loading and giving each VLs a uniform
1185 * distribution of engines per VL.
1186 *
1187 * The auto algorithm computes the sde_per_vl and the number of extra
1188 * engines. Any extra engines are added from the last VL on down.
1189 *
1190 * rcu locking is used here to control access to the mapping fields.
1191 *
1192 * If either the num_vls or num_sdma are non-power of 2, the array sizes
1193 * in the struct sdma_vl_map and the struct sdma_map_elem are rounded
1194 * up to the next highest power of 2 and the first entry is reused
1195 * in a round robin fashion.
1196 *
1197 * If an error occurs the map change is not done and the mapping is
1198 * not changed.
1199 *
1200 */
sdma_map_init(struct hfi1_devdata * dd,u8 port,u8 num_vls,u8 * vl_engines)1201 int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines)
1202 {
1203 int i, j;
1204 int extra, sde_per_vl;
1205 int engine = 0;
1206 u8 lvl_engines[OPA_MAX_VLS];
1207 struct sdma_vl_map *oldmap, *newmap;
1208
1209 if (!(dd->flags & HFI1_HAS_SEND_DMA))
1210 return 0;
1211
1212 if (!vl_engines) {
1213 /* truncate divide */
1214 sde_per_vl = dd->num_sdma / num_vls;
1215 /* extras */
1216 extra = dd->num_sdma % num_vls;
1217 vl_engines = lvl_engines;
1218 /* add extras from last vl down */
1219 for (i = num_vls - 1; i >= 0; i--, extra--)
1220 vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0);
1221 }
1222 /* build new map */
1223 newmap = kzalloc(
1224 sizeof(struct sdma_vl_map) +
1225 roundup_pow_of_two(num_vls) *
1226 sizeof(struct sdma_map_elem *),
1227 GFP_KERNEL);
1228 if (!newmap)
1229 goto bail;
1230 newmap->actual_vls = num_vls;
1231 newmap->vls = roundup_pow_of_two(num_vls);
1232 newmap->mask = (1 << ilog2(newmap->vls)) - 1;
1233 /* initialize back-map */
1234 for (i = 0; i < TXE_NUM_SDMA_ENGINES; i++)
1235 newmap->engine_to_vl[i] = -1;
1236 for (i = 0; i < newmap->vls; i++) {
1237 /* save for wrap around */
1238 int first_engine = engine;
1239
1240 if (i < newmap->actual_vls) {
1241 int sz = roundup_pow_of_two(vl_engines[i]);
1242
1243 /* only allocate once */
1244 newmap->map[i] = kzalloc(
1245 sizeof(struct sdma_map_elem) +
1246 sz * sizeof(struct sdma_engine *),
1247 GFP_KERNEL);
1248 if (!newmap->map[i])
1249 goto bail;
1250 newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
1251 /* assign engines */
1252 for (j = 0; j < sz; j++) {
1253 newmap->map[i]->sde[j] =
1254 &dd->per_sdma[engine];
1255 if (++engine >= first_engine + vl_engines[i])
1256 /* wrap back to first engine */
1257 engine = first_engine;
1258 }
1259 /* assign back-map */
1260 for (j = 0; j < vl_engines[i]; j++)
1261 newmap->engine_to_vl[first_engine + j] = i;
1262 } else {
1263 /* just re-use entry without allocating */
1264 newmap->map[i] = newmap->map[i % num_vls];
1265 }
1266 engine = first_engine + vl_engines[i];
1267 }
1268 /* newmap in hand, save old map */
1269 spin_lock_irq(&dd->sde_map_lock);
1270 oldmap = rcu_dereference_protected(dd->sdma_map,
1271 lockdep_is_held(&dd->sde_map_lock));
1272
1273 /* publish newmap */
1274 rcu_assign_pointer(dd->sdma_map, newmap);
1275
1276 spin_unlock_irq(&dd->sde_map_lock);
1277 /* success, free any old map after grace period */
1278 if (oldmap)
1279 call_rcu(&oldmap->list, sdma_map_rcu_callback);
1280 return 0;
1281 bail:
1282 /* free any partial allocation */
1283 sdma_map_free(newmap);
1284 return -ENOMEM;
1285 }
1286
1287 /**
1288 * sdma_clean() Clean up allocated memory
1289 * @dd: struct hfi1_devdata
1290 * @num_engines: num sdma engines
1291 *
1292 * This routine can be called regardless of the success of
1293 * sdma_init()
1294 */
sdma_clean(struct hfi1_devdata * dd,size_t num_engines)1295 void sdma_clean(struct hfi1_devdata *dd, size_t num_engines)
1296 {
1297 size_t i;
1298 struct sdma_engine *sde;
1299
1300 if (dd->sdma_pad_dma) {
1301 dma_free_coherent(&dd->pcidev->dev, SDMA_PAD,
1302 (void *)dd->sdma_pad_dma,
1303 dd->sdma_pad_phys);
1304 dd->sdma_pad_dma = NULL;
1305 dd->sdma_pad_phys = 0;
1306 }
1307 if (dd->sdma_heads_dma) {
1308 dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size,
1309 (void *)dd->sdma_heads_dma,
1310 dd->sdma_heads_phys);
1311 dd->sdma_heads_dma = NULL;
1312 dd->sdma_heads_phys = 0;
1313 }
1314 for (i = 0; dd->per_sdma && i < num_engines; ++i) {
1315 sde = &dd->per_sdma[i];
1316
1317 sde->head_dma = NULL;
1318 sde->head_phys = 0;
1319
1320 if (sde->descq) {
1321 dma_free_coherent(
1322 &dd->pcidev->dev,
1323 sde->descq_cnt * sizeof(u64[2]),
1324 sde->descq,
1325 sde->descq_phys
1326 );
1327 sde->descq = NULL;
1328 sde->descq_phys = 0;
1329 }
1330 kvfree(sde->tx_ring);
1331 sde->tx_ring = NULL;
1332 }
1333 if (rcu_access_pointer(dd->sdma_map)) {
1334 spin_lock_irq(&dd->sde_map_lock);
1335 sdma_map_free(rcu_access_pointer(dd->sdma_map));
1336 RCU_INIT_POINTER(dd->sdma_map, NULL);
1337 spin_unlock_irq(&dd->sde_map_lock);
1338 synchronize_rcu();
1339 }
1340 kfree(dd->per_sdma);
1341 dd->per_sdma = NULL;
1342
1343 if (dd->sdma_rht) {
1344 rhashtable_free_and_destroy(dd->sdma_rht, sdma_rht_free, NULL);
1345 kfree(dd->sdma_rht);
1346 dd->sdma_rht = NULL;
1347 }
1348 }
1349
1350 /**
1351 * sdma_init() - called when device probed
1352 * @dd: hfi1_devdata
1353 * @port: port number (currently only zero)
1354 *
1355 * Initializes each sde and its csrs.
1356 * Interrupts are not required to be enabled.
1357 *
1358 * Returns:
1359 * 0 - success, -errno on failure
1360 */
sdma_init(struct hfi1_devdata * dd,u8 port)1361 int sdma_init(struct hfi1_devdata *dd, u8 port)
1362 {
1363 unsigned this_idx;
1364 struct sdma_engine *sde;
1365 struct rhashtable *tmp_sdma_rht;
1366 u16 descq_cnt;
1367 void *curr_head;
1368 struct hfi1_pportdata *ppd = dd->pport + port;
1369 u32 per_sdma_credits;
1370 uint idle_cnt = sdma_idle_cnt;
1371 size_t num_engines = chip_sdma_engines(dd);
1372 int ret = -ENOMEM;
1373
1374 if (!HFI1_CAP_IS_KSET(SDMA)) {
1375 HFI1_CAP_CLEAR(SDMA_AHG);
1376 return 0;
1377 }
1378 if (mod_num_sdma &&
1379 /* can't exceed chip support */
1380 mod_num_sdma <= chip_sdma_engines(dd) &&
1381 /* count must be >= vls */
1382 mod_num_sdma >= num_vls)
1383 num_engines = mod_num_sdma;
1384
1385 dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma);
1386 dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", chip_sdma_engines(dd));
1387 dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n",
1388 chip_sdma_mem_size(dd));
1389
1390 per_sdma_credits =
1391 chip_sdma_mem_size(dd) / (num_engines * SDMA_BLOCK_SIZE);
1392
1393 /* set up freeze waitqueue */
1394 init_waitqueue_head(&dd->sdma_unfreeze_wq);
1395 atomic_set(&dd->sdma_unfreeze_count, 0);
1396
1397 descq_cnt = sdma_get_descq_cnt();
1398 dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n",
1399 num_engines, descq_cnt);
1400
1401 /* alloc memory for array of send engines */
1402 dd->per_sdma = kcalloc_node(num_engines, sizeof(*dd->per_sdma),
1403 GFP_KERNEL, dd->node);
1404 if (!dd->per_sdma)
1405 return ret;
1406
1407 idle_cnt = ns_to_cclock(dd, idle_cnt);
1408 if (idle_cnt)
1409 dd->default_desc1 =
1410 SDMA_DESC1_HEAD_TO_HOST_FLAG;
1411 else
1412 dd->default_desc1 =
1413 SDMA_DESC1_INT_REQ_FLAG;
1414
1415 if (!sdma_desct_intr)
1416 sdma_desct_intr = SDMA_DESC_INTR;
1417
1418 /* Allocate memory for SendDMA descriptor FIFOs */
1419 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1420 sde = &dd->per_sdma[this_idx];
1421 sde->dd = dd;
1422 sde->ppd = ppd;
1423 sde->this_idx = this_idx;
1424 sde->descq_cnt = descq_cnt;
1425 sde->desc_avail = sdma_descq_freecnt(sde);
1426 sde->sdma_shift = ilog2(descq_cnt);
1427 sde->sdma_mask = (1 << sde->sdma_shift) - 1;
1428
1429 /* Create a mask specifically for each interrupt source */
1430 sde->int_mask = (u64)1 << (0 * TXE_NUM_SDMA_ENGINES +
1431 this_idx);
1432 sde->progress_mask = (u64)1 << (1 * TXE_NUM_SDMA_ENGINES +
1433 this_idx);
1434 sde->idle_mask = (u64)1 << (2 * TXE_NUM_SDMA_ENGINES +
1435 this_idx);
1436 /* Create a combined mask to cover all 3 interrupt sources */
1437 sde->imask = sde->int_mask | sde->progress_mask |
1438 sde->idle_mask;
1439
1440 spin_lock_init(&sde->tail_lock);
1441 seqlock_init(&sde->head_lock);
1442 spin_lock_init(&sde->senddmactrl_lock);
1443 spin_lock_init(&sde->flushlist_lock);
1444 seqlock_init(&sde->waitlock);
1445 /* insure there is always a zero bit */
1446 sde->ahg_bits = 0xfffffffe00000000ULL;
1447
1448 sdma_set_state(sde, sdma_state_s00_hw_down);
1449
1450 /* set up reference counting */
1451 kref_init(&sde->state.kref);
1452 init_completion(&sde->state.comp);
1453
1454 INIT_LIST_HEAD(&sde->flushlist);
1455 INIT_LIST_HEAD(&sde->dmawait);
1456
1457 sde->tail_csr =
1458 get_kctxt_csr_addr(dd, this_idx, SD(TAIL));
1459
1460 tasklet_setup(&sde->sdma_hw_clean_up_task,
1461 sdma_hw_clean_up_task);
1462 tasklet_setup(&sde->sdma_sw_clean_up_task,
1463 sdma_sw_clean_up_task);
1464 INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait);
1465 INIT_WORK(&sde->flush_worker, sdma_field_flush);
1466
1467 sde->progress_check_head = 0;
1468
1469 timer_setup(&sde->err_progress_check_timer,
1470 sdma_err_progress_check, 0);
1471
1472 sde->descq = dma_alloc_coherent(&dd->pcidev->dev,
1473 descq_cnt * sizeof(u64[2]),
1474 &sde->descq_phys, GFP_KERNEL);
1475 if (!sde->descq)
1476 goto bail;
1477 sde->tx_ring =
1478 kvzalloc_node(array_size(descq_cnt,
1479 sizeof(struct sdma_txreq *)),
1480 GFP_KERNEL, dd->node);
1481 if (!sde->tx_ring)
1482 goto bail;
1483 }
1484
1485 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines;
1486 /* Allocate memory for DMA of head registers to memory */
1487 dd->sdma_heads_dma = dma_alloc_coherent(&dd->pcidev->dev,
1488 dd->sdma_heads_size,
1489 &dd->sdma_heads_phys,
1490 GFP_KERNEL);
1491 if (!dd->sdma_heads_dma) {
1492 dd_dev_err(dd, "failed to allocate SendDMA head memory\n");
1493 goto bail;
1494 }
1495
1496 /* Allocate memory for pad */
1497 dd->sdma_pad_dma = dma_alloc_coherent(&dd->pcidev->dev, SDMA_PAD,
1498 &dd->sdma_pad_phys, GFP_KERNEL);
1499 if (!dd->sdma_pad_dma) {
1500 dd_dev_err(dd, "failed to allocate SendDMA pad memory\n");
1501 goto bail;
1502 }
1503
1504 /* assign each engine to different cacheline and init registers */
1505 curr_head = (void *)dd->sdma_heads_dma;
1506 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1507 unsigned long phys_offset;
1508
1509 sde = &dd->per_sdma[this_idx];
1510
1511 sde->head_dma = curr_head;
1512 curr_head += L1_CACHE_BYTES;
1513 phys_offset = (unsigned long)sde->head_dma -
1514 (unsigned long)dd->sdma_heads_dma;
1515 sde->head_phys = dd->sdma_heads_phys + phys_offset;
1516 init_sdma_regs(sde, per_sdma_credits, idle_cnt);
1517 }
1518 dd->flags |= HFI1_HAS_SEND_DMA;
1519 dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0;
1520 dd->num_sdma = num_engines;
1521 ret = sdma_map_init(dd, port, ppd->vls_operational, NULL);
1522 if (ret < 0)
1523 goto bail;
1524
1525 tmp_sdma_rht = kzalloc(sizeof(*tmp_sdma_rht), GFP_KERNEL);
1526 if (!tmp_sdma_rht) {
1527 ret = -ENOMEM;
1528 goto bail;
1529 }
1530
1531 ret = rhashtable_init(tmp_sdma_rht, &sdma_rht_params);
1532 if (ret < 0) {
1533 kfree(tmp_sdma_rht);
1534 goto bail;
1535 }
1536
1537 dd->sdma_rht = tmp_sdma_rht;
1538
1539 dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma);
1540 return 0;
1541
1542 bail:
1543 sdma_clean(dd, num_engines);
1544 return ret;
1545 }
1546
1547 /**
1548 * sdma_all_running() - called when the link goes up
1549 * @dd: hfi1_devdata
1550 *
1551 * This routine moves all engines to the running state.
1552 */
sdma_all_running(struct hfi1_devdata * dd)1553 void sdma_all_running(struct hfi1_devdata *dd)
1554 {
1555 struct sdma_engine *sde;
1556 unsigned int i;
1557
1558 /* move all engines to running */
1559 for (i = 0; i < dd->num_sdma; ++i) {
1560 sde = &dd->per_sdma[i];
1561 sdma_process_event(sde, sdma_event_e30_go_running);
1562 }
1563 }
1564
1565 /**
1566 * sdma_all_idle() - called when the link goes down
1567 * @dd: hfi1_devdata
1568 *
1569 * This routine moves all engines to the idle state.
1570 */
sdma_all_idle(struct hfi1_devdata * dd)1571 void sdma_all_idle(struct hfi1_devdata *dd)
1572 {
1573 struct sdma_engine *sde;
1574 unsigned int i;
1575
1576 /* idle all engines */
1577 for (i = 0; i < dd->num_sdma; ++i) {
1578 sde = &dd->per_sdma[i];
1579 sdma_process_event(sde, sdma_event_e70_go_idle);
1580 }
1581 }
1582
1583 /**
1584 * sdma_start() - called to kick off state processing for all engines
1585 * @dd: hfi1_devdata
1586 *
1587 * This routine is for kicking off the state processing for all required
1588 * sdma engines. Interrupts need to be working at this point.
1589 *
1590 */
sdma_start(struct hfi1_devdata * dd)1591 void sdma_start(struct hfi1_devdata *dd)
1592 {
1593 unsigned i;
1594 struct sdma_engine *sde;
1595
1596 /* kick off the engines state processing */
1597 for (i = 0; i < dd->num_sdma; ++i) {
1598 sde = &dd->per_sdma[i];
1599 sdma_process_event(sde, sdma_event_e10_go_hw_start);
1600 }
1601 }
1602
1603 /**
1604 * sdma_exit() - used when module is removed
1605 * @dd: hfi1_devdata
1606 */
sdma_exit(struct hfi1_devdata * dd)1607 void sdma_exit(struct hfi1_devdata *dd)
1608 {
1609 unsigned this_idx;
1610 struct sdma_engine *sde;
1611
1612 for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma;
1613 ++this_idx) {
1614 sde = &dd->per_sdma[this_idx];
1615 if (!list_empty(&sde->dmawait))
1616 dd_dev_err(dd, "sde %u: dmawait list not empty!\n",
1617 sde->this_idx);
1618 sdma_process_event(sde, sdma_event_e00_go_hw_down);
1619
1620 del_timer_sync(&sde->err_progress_check_timer);
1621
1622 /*
1623 * This waits for the state machine to exit so it is not
1624 * necessary to kill the sdma_sw_clean_up_task to make sure
1625 * it is not running.
1626 */
1627 sdma_finalput(&sde->state);
1628 }
1629 }
1630
1631 /*
1632 * unmap the indicated descriptor
1633 */
sdma_unmap_desc(struct hfi1_devdata * dd,struct sdma_desc * descp)1634 static inline void sdma_unmap_desc(
1635 struct hfi1_devdata *dd,
1636 struct sdma_desc *descp)
1637 {
1638 system_descriptor_complete(dd, descp);
1639 }
1640
1641 /*
1642 * return the mode as indicated by the first
1643 * descriptor in the tx.
1644 */
ahg_mode(struct sdma_txreq * tx)1645 static inline u8 ahg_mode(struct sdma_txreq *tx)
1646 {
1647 return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1648 >> SDMA_DESC1_HEADER_MODE_SHIFT;
1649 }
1650
1651 /**
1652 * __sdma_txclean() - clean tx of mappings, descp *kmalloc's
1653 * @dd: hfi1_devdata for unmapping
1654 * @tx: tx request to clean
1655 *
1656 * This is used in the progress routine to clean the tx or
1657 * by the ULP to toss an in-process tx build.
1658 *
1659 * The code can be called multiple times without issue.
1660 *
1661 */
__sdma_txclean(struct hfi1_devdata * dd,struct sdma_txreq * tx)1662 void __sdma_txclean(
1663 struct hfi1_devdata *dd,
1664 struct sdma_txreq *tx)
1665 {
1666 u16 i;
1667
1668 if (tx->num_desc) {
1669 u8 skip = 0, mode = ahg_mode(tx);
1670
1671 /* unmap first */
1672 sdma_unmap_desc(dd, &tx->descp[0]);
1673 /* determine number of AHG descriptors to skip */
1674 if (mode > SDMA_AHG_APPLY_UPDATE1)
1675 skip = mode >> 1;
1676 for (i = 1 + skip; i < tx->num_desc; i++)
1677 sdma_unmap_desc(dd, &tx->descp[i]);
1678 tx->num_desc = 0;
1679 }
1680 kfree(tx->coalesce_buf);
1681 tx->coalesce_buf = NULL;
1682 /* kmalloc'ed descp */
1683 if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) {
1684 tx->desc_limit = ARRAY_SIZE(tx->descs);
1685 kfree(tx->descp);
1686 }
1687 }
1688
sdma_gethead(struct sdma_engine * sde)1689 static inline u16 sdma_gethead(struct sdma_engine *sde)
1690 {
1691 struct hfi1_devdata *dd = sde->dd;
1692 int use_dmahead;
1693 u16 hwhead;
1694
1695 #ifdef CONFIG_SDMA_VERBOSITY
1696 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1697 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1698 #endif
1699
1700 retry:
1701 use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) &&
1702 (dd->flags & HFI1_HAS_SDMA_TIMEOUT);
1703 hwhead = use_dmahead ?
1704 (u16)le64_to_cpu(*sde->head_dma) :
1705 (u16)read_sde_csr(sde, SD(HEAD));
1706
1707 if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) {
1708 u16 cnt;
1709 u16 swtail;
1710 u16 swhead;
1711 int sane;
1712
1713 swhead = sde->descq_head & sde->sdma_mask;
1714 /* this code is really bad for cache line trading */
1715 swtail = READ_ONCE(sde->descq_tail) & sde->sdma_mask;
1716 cnt = sde->descq_cnt;
1717
1718 if (swhead < swtail)
1719 /* not wrapped */
1720 sane = (hwhead >= swhead) & (hwhead <= swtail);
1721 else if (swhead > swtail)
1722 /* wrapped around */
1723 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
1724 (hwhead <= swtail);
1725 else
1726 /* empty */
1727 sane = (hwhead == swhead);
1728
1729 if (unlikely(!sane)) {
1730 dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n",
1731 sde->this_idx,
1732 use_dmahead ? "dma" : "kreg",
1733 hwhead, swhead, swtail, cnt);
1734 if (use_dmahead) {
1735 /* try one more time, using csr */
1736 use_dmahead = 0;
1737 goto retry;
1738 }
1739 /* proceed as if no progress */
1740 hwhead = swhead;
1741 }
1742 }
1743 return hwhead;
1744 }
1745
1746 /*
1747 * This is called when there are send DMA descriptors that might be
1748 * available.
1749 *
1750 * This is called with head_lock held.
1751 */
sdma_desc_avail(struct sdma_engine * sde,uint avail)1752 static void sdma_desc_avail(struct sdma_engine *sde, uint avail)
1753 {
1754 struct iowait *wait, *nw, *twait;
1755 struct iowait *waits[SDMA_WAIT_BATCH_SIZE];
1756 uint i, n = 0, seq, tidx = 0;
1757
1758 #ifdef CONFIG_SDMA_VERBOSITY
1759 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
1760 slashstrip(__FILE__), __LINE__, __func__);
1761 dd_dev_err(sde->dd, "avail: %u\n", avail);
1762 #endif
1763
1764 do {
1765 seq = read_seqbegin(&sde->waitlock);
1766 if (!list_empty(&sde->dmawait)) {
1767 /* at least one item */
1768 write_seqlock(&sde->waitlock);
1769 /* Harvest waiters wanting DMA descriptors */
1770 list_for_each_entry_safe(
1771 wait,
1772 nw,
1773 &sde->dmawait,
1774 list) {
1775 u32 num_desc;
1776
1777 if (!wait->wakeup)
1778 continue;
1779 if (n == ARRAY_SIZE(waits))
1780 break;
1781 iowait_init_priority(wait);
1782 num_desc = iowait_get_all_desc(wait);
1783 if (num_desc > avail)
1784 break;
1785 avail -= num_desc;
1786 /* Find the top-priority wait memeber */
1787 if (n) {
1788 twait = waits[tidx];
1789 tidx =
1790 iowait_priority_update_top(wait,
1791 twait,
1792 n,
1793 tidx);
1794 }
1795 list_del_init(&wait->list);
1796 waits[n++] = wait;
1797 }
1798 write_sequnlock(&sde->waitlock);
1799 break;
1800 }
1801 } while (read_seqretry(&sde->waitlock, seq));
1802
1803 /* Schedule the top-priority entry first */
1804 if (n)
1805 waits[tidx]->wakeup(waits[tidx], SDMA_AVAIL_REASON);
1806
1807 for (i = 0; i < n; i++)
1808 if (i != tidx)
1809 waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON);
1810 }
1811
1812 /* head_lock must be held */
sdma_make_progress(struct sdma_engine * sde,u64 status)1813 static void sdma_make_progress(struct sdma_engine *sde, u64 status)
1814 {
1815 struct sdma_txreq *txp = NULL;
1816 int progress = 0;
1817 u16 hwhead, swhead;
1818 int idle_check_done = 0;
1819
1820 hwhead = sdma_gethead(sde);
1821
1822 /* The reason for some of the complexity of this code is that
1823 * not all descriptors have corresponding txps. So, we have to
1824 * be able to skip over descs until we wander into the range of
1825 * the next txp on the list.
1826 */
1827
1828 retry:
1829 txp = get_txhead(sde);
1830 swhead = sde->descq_head & sde->sdma_mask;
1831 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1832 while (swhead != hwhead) {
1833 /* advance head, wrap if needed */
1834 swhead = ++sde->descq_head & sde->sdma_mask;
1835
1836 /* if now past this txp's descs, do the callback */
1837 if (txp && txp->next_descq_idx == swhead) {
1838 /* remove from list */
1839 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
1840 complete_tx(sde, txp, SDMA_TXREQ_S_OK);
1841 /* see if there is another txp */
1842 txp = get_txhead(sde);
1843 }
1844 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1845 progress++;
1846 }
1847
1848 /*
1849 * The SDMA idle interrupt is not guaranteed to be ordered with respect
1850 * to updates to the the dma_head location in host memory. The head
1851 * value read might not be fully up to date. If there are pending
1852 * descriptors and the SDMA idle interrupt fired then read from the
1853 * CSR SDMA head instead to get the latest value from the hardware.
1854 * The hardware SDMA head should be read at most once in this invocation
1855 * of sdma_make_progress(..) which is ensured by idle_check_done flag
1856 */
1857 if ((status & sde->idle_mask) && !idle_check_done) {
1858 u16 swtail;
1859
1860 swtail = READ_ONCE(sde->descq_tail) & sde->sdma_mask;
1861 if (swtail != hwhead) {
1862 hwhead = (u16)read_sde_csr(sde, SD(HEAD));
1863 idle_check_done = 1;
1864 goto retry;
1865 }
1866 }
1867
1868 sde->last_status = status;
1869 if (progress)
1870 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
1871 }
1872
1873 /*
1874 * sdma_engine_interrupt() - interrupt handler for engine
1875 * @sde: sdma engine
1876 * @status: sdma interrupt reason
1877 *
1878 * Status is a mask of the 3 possible interrupts for this engine. It will
1879 * contain bits _only_ for this SDMA engine. It will contain at least one
1880 * bit, it may contain more.
1881 */
sdma_engine_interrupt(struct sdma_engine * sde,u64 status)1882 void sdma_engine_interrupt(struct sdma_engine *sde, u64 status)
1883 {
1884 trace_hfi1_sdma_engine_interrupt(sde, status);
1885 write_seqlock(&sde->head_lock);
1886 sdma_set_desc_cnt(sde, sdma_desct_intr);
1887 if (status & sde->idle_mask)
1888 sde->idle_int_cnt++;
1889 else if (status & sde->progress_mask)
1890 sde->progress_int_cnt++;
1891 else if (status & sde->int_mask)
1892 sde->sdma_int_cnt++;
1893 sdma_make_progress(sde, status);
1894 write_sequnlock(&sde->head_lock);
1895 }
1896
1897 /**
1898 * sdma_engine_error() - error handler for engine
1899 * @sde: sdma engine
1900 * @status: sdma interrupt reason
1901 */
sdma_engine_error(struct sdma_engine * sde,u64 status)1902 void sdma_engine_error(struct sdma_engine *sde, u64 status)
1903 {
1904 unsigned long flags;
1905
1906 #ifdef CONFIG_SDMA_VERBOSITY
1907 dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n",
1908 sde->this_idx,
1909 (unsigned long long)status,
1910 sdma_state_names[sde->state.current_state]);
1911 #endif
1912 spin_lock_irqsave(&sde->tail_lock, flags);
1913 write_seqlock(&sde->head_lock);
1914 if (status & ALL_SDMA_ENG_HALT_ERRS)
1915 __sdma_process_event(sde, sdma_event_e60_hw_halted);
1916 if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) {
1917 dd_dev_err(sde->dd,
1918 "SDMA (%u) engine error: 0x%llx state %s\n",
1919 sde->this_idx,
1920 (unsigned long long)status,
1921 sdma_state_names[sde->state.current_state]);
1922 dump_sdma_state(sde);
1923 }
1924 write_sequnlock(&sde->head_lock);
1925 spin_unlock_irqrestore(&sde->tail_lock, flags);
1926 }
1927
sdma_sendctrl(struct sdma_engine * sde,unsigned op)1928 static void sdma_sendctrl(struct sdma_engine *sde, unsigned op)
1929 {
1930 u64 set_senddmactrl = 0;
1931 u64 clr_senddmactrl = 0;
1932 unsigned long flags;
1933
1934 #ifdef CONFIG_SDMA_VERBOSITY
1935 dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n",
1936 sde->this_idx,
1937 (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0,
1938 (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0,
1939 (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0,
1940 (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0);
1941 #endif
1942
1943 if (op & SDMA_SENDCTRL_OP_ENABLE)
1944 set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1945 else
1946 clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1947
1948 if (op & SDMA_SENDCTRL_OP_INTENABLE)
1949 set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1950 else
1951 clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1952
1953 if (op & SDMA_SENDCTRL_OP_HALT)
1954 set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1955 else
1956 clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1957
1958 spin_lock_irqsave(&sde->senddmactrl_lock, flags);
1959
1960 sde->p_senddmactrl |= set_senddmactrl;
1961 sde->p_senddmactrl &= ~clr_senddmactrl;
1962
1963 if (op & SDMA_SENDCTRL_OP_CLEANUP)
1964 write_sde_csr(sde, SD(CTRL),
1965 sde->p_senddmactrl |
1966 SD(CTRL_SDMA_CLEANUP_SMASK));
1967 else
1968 write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl);
1969
1970 spin_unlock_irqrestore(&sde->senddmactrl_lock, flags);
1971
1972 #ifdef CONFIG_SDMA_VERBOSITY
1973 sdma_dumpstate(sde);
1974 #endif
1975 }
1976
sdma_setlengen(struct sdma_engine * sde)1977 static void sdma_setlengen(struct sdma_engine *sde)
1978 {
1979 #ifdef CONFIG_SDMA_VERBOSITY
1980 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1981 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1982 #endif
1983
1984 /*
1985 * Set SendDmaLenGen and clear-then-set the MSB of the generation
1986 * count to enable generation checking and load the internal
1987 * generation counter.
1988 */
1989 write_sde_csr(sde, SD(LEN_GEN),
1990 (sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT));
1991 write_sde_csr(sde, SD(LEN_GEN),
1992 ((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)) |
1993 (4ULL << SD(LEN_GEN_GENERATION_SHIFT)));
1994 }
1995
sdma_update_tail(struct sdma_engine * sde,u16 tail)1996 static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail)
1997 {
1998 /* Commit writes to memory and advance the tail on the chip */
1999 smp_wmb(); /* see get_txhead() */
2000 writeq(tail, sde->tail_csr);
2001 }
2002
2003 /*
2004 * This is called when changing to state s10_hw_start_up_halt_wait as
2005 * a result of send buffer errors or send DMA descriptor errors.
2006 */
sdma_hw_start_up(struct sdma_engine * sde)2007 static void sdma_hw_start_up(struct sdma_engine *sde)
2008 {
2009 u64 reg;
2010
2011 #ifdef CONFIG_SDMA_VERBOSITY
2012 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
2013 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
2014 #endif
2015
2016 sdma_setlengen(sde);
2017 sdma_update_tail(sde, 0); /* Set SendDmaTail */
2018 *sde->head_dma = 0;
2019
2020 reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) <<
2021 SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT);
2022 write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg);
2023 }
2024
2025 /*
2026 * set_sdma_integrity
2027 *
2028 * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'.
2029 */
set_sdma_integrity(struct sdma_engine * sde)2030 static void set_sdma_integrity(struct sdma_engine *sde)
2031 {
2032 struct hfi1_devdata *dd = sde->dd;
2033
2034 write_sde_csr(sde, SD(CHECK_ENABLE),
2035 hfi1_pkt_base_sdma_integrity(dd));
2036 }
2037
init_sdma_regs(struct sdma_engine * sde,u32 credits,uint idle_cnt)2038 static void init_sdma_regs(
2039 struct sdma_engine *sde,
2040 u32 credits,
2041 uint idle_cnt)
2042 {
2043 u8 opval, opmask;
2044 #ifdef CONFIG_SDMA_VERBOSITY
2045 struct hfi1_devdata *dd = sde->dd;
2046
2047 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n",
2048 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
2049 #endif
2050
2051 write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys);
2052 sdma_setlengen(sde);
2053 sdma_update_tail(sde, 0); /* Set SendDmaTail */
2054 write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt);
2055 write_sde_csr(sde, SD(DESC_CNT), 0);
2056 write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys);
2057 write_sde_csr(sde, SD(MEMORY),
2058 ((u64)credits << SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) |
2059 ((u64)(credits * sde->this_idx) <<
2060 SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT)));
2061 write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull);
2062 set_sdma_integrity(sde);
2063 opmask = OPCODE_CHECK_MASK_DISABLED;
2064 opval = OPCODE_CHECK_VAL_DISABLED;
2065 write_sde_csr(sde, SD(CHECK_OPCODE),
2066 (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) |
2067 (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT));
2068 }
2069
2070 #ifdef CONFIG_SDMA_VERBOSITY
2071
2072 #define sdma_dumpstate_helper0(reg) do { \
2073 csr = read_csr(sde->dd, reg); \
2074 dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \
2075 } while (0)
2076
2077 #define sdma_dumpstate_helper(reg) do { \
2078 csr = read_sde_csr(sde, reg); \
2079 dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \
2080 #reg, sde->this_idx, csr); \
2081 } while (0)
2082
2083 #define sdma_dumpstate_helper2(reg) do { \
2084 csr = read_csr(sde->dd, reg + (8 * i)); \
2085 dd_dev_err(sde->dd, "%33s_%02u 0x%016llx\n", \
2086 #reg, i, csr); \
2087 } while (0)
2088
sdma_dumpstate(struct sdma_engine * sde)2089 void sdma_dumpstate(struct sdma_engine *sde)
2090 {
2091 u64 csr;
2092 unsigned i;
2093
2094 sdma_dumpstate_helper(SD(CTRL));
2095 sdma_dumpstate_helper(SD(STATUS));
2096 sdma_dumpstate_helper0(SD(ERR_STATUS));
2097 sdma_dumpstate_helper0(SD(ERR_MASK));
2098 sdma_dumpstate_helper(SD(ENG_ERR_STATUS));
2099 sdma_dumpstate_helper(SD(ENG_ERR_MASK));
2100
2101 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) {
2102 sdma_dumpstate_helper2(CCE_INT_STATUS);
2103 sdma_dumpstate_helper2(CCE_INT_MASK);
2104 sdma_dumpstate_helper2(CCE_INT_BLOCKED);
2105 }
2106
2107 sdma_dumpstate_helper(SD(TAIL));
2108 sdma_dumpstate_helper(SD(HEAD));
2109 sdma_dumpstate_helper(SD(PRIORITY_THLD));
2110 sdma_dumpstate_helper(SD(IDLE_CNT));
2111 sdma_dumpstate_helper(SD(RELOAD_CNT));
2112 sdma_dumpstate_helper(SD(DESC_CNT));
2113 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT));
2114 sdma_dumpstate_helper(SD(MEMORY));
2115 sdma_dumpstate_helper0(SD(ENGINES));
2116 sdma_dumpstate_helper0(SD(MEM_SIZE));
2117 /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS); */
2118 sdma_dumpstate_helper(SD(BASE_ADDR));
2119 sdma_dumpstate_helper(SD(LEN_GEN));
2120 sdma_dumpstate_helper(SD(HEAD_ADDR));
2121 sdma_dumpstate_helper(SD(CHECK_ENABLE));
2122 sdma_dumpstate_helper(SD(CHECK_VL));
2123 sdma_dumpstate_helper(SD(CHECK_JOB_KEY));
2124 sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY));
2125 sdma_dumpstate_helper(SD(CHECK_SLID));
2126 sdma_dumpstate_helper(SD(CHECK_OPCODE));
2127 }
2128 #endif
2129
dump_sdma_state(struct sdma_engine * sde)2130 static void dump_sdma_state(struct sdma_engine *sde)
2131 {
2132 struct hw_sdma_desc *descqp;
2133 u64 desc[2];
2134 u64 addr;
2135 u8 gen;
2136 u16 len;
2137 u16 head, tail, cnt;
2138
2139 head = sde->descq_head & sde->sdma_mask;
2140 tail = sde->descq_tail & sde->sdma_mask;
2141 cnt = sdma_descq_freecnt(sde);
2142
2143 dd_dev_err(sde->dd,
2144 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n",
2145 sde->this_idx, head, tail, cnt,
2146 !list_empty(&sde->flushlist));
2147
2148 /* print info for each entry in the descriptor queue */
2149 while (head != tail) {
2150 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
2151
2152 descqp = &sde->descq[head];
2153 desc[0] = le64_to_cpu(descqp->qw[0]);
2154 desc[1] = le64_to_cpu(descqp->qw[1]);
2155 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
2156 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
2157 'H' : '-';
2158 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
2159 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
2160 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
2161 & SDMA_DESC0_PHY_ADDR_MASK;
2162 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
2163 & SDMA_DESC1_GENERATION_MASK;
2164 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
2165 & SDMA_DESC0_BYTE_COUNT_MASK;
2166 dd_dev_err(sde->dd,
2167 "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
2168 head, flags, addr, gen, len);
2169 dd_dev_err(sde->dd,
2170 "\tdesc0:0x%016llx desc1 0x%016llx\n",
2171 desc[0], desc[1]);
2172 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
2173 dd_dev_err(sde->dd,
2174 "\taidx: %u amode: %u alen: %u\n",
2175 (u8)((desc[1] &
2176 SDMA_DESC1_HEADER_INDEX_SMASK) >>
2177 SDMA_DESC1_HEADER_INDEX_SHIFT),
2178 (u8)((desc[1] &
2179 SDMA_DESC1_HEADER_MODE_SMASK) >>
2180 SDMA_DESC1_HEADER_MODE_SHIFT),
2181 (u8)((desc[1] &
2182 SDMA_DESC1_HEADER_DWS_SMASK) >>
2183 SDMA_DESC1_HEADER_DWS_SHIFT));
2184 head++;
2185 head &= sde->sdma_mask;
2186 }
2187 }
2188
2189 #define SDE_FMT \
2190 "SDE %u CPU %d STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n"
2191 /**
2192 * sdma_seqfile_dump_sde() - debugfs dump of sde
2193 * @s: seq file
2194 * @sde: send dma engine to dump
2195 *
2196 * This routine dumps the sde to the indicated seq file.
2197 */
sdma_seqfile_dump_sde(struct seq_file * s,struct sdma_engine * sde)2198 void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde)
2199 {
2200 u16 head, tail;
2201 struct hw_sdma_desc *descqp;
2202 u64 desc[2];
2203 u64 addr;
2204 u8 gen;
2205 u16 len;
2206
2207 head = sde->descq_head & sde->sdma_mask;
2208 tail = READ_ONCE(sde->descq_tail) & sde->sdma_mask;
2209 seq_printf(s, SDE_FMT, sde->this_idx,
2210 sde->cpu,
2211 sdma_state_name(sde->state.current_state),
2212 (unsigned long long)read_sde_csr(sde, SD(CTRL)),
2213 (unsigned long long)read_sde_csr(sde, SD(STATUS)),
2214 (unsigned long long)read_sde_csr(sde, SD(ENG_ERR_STATUS)),
2215 (unsigned long long)read_sde_csr(sde, SD(TAIL)), tail,
2216 (unsigned long long)read_sde_csr(sde, SD(HEAD)), head,
2217 (unsigned long long)le64_to_cpu(*sde->head_dma),
2218 (unsigned long long)read_sde_csr(sde, SD(MEMORY)),
2219 (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)),
2220 (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)),
2221 (unsigned long long)sde->last_status,
2222 (unsigned long long)sde->ahg_bits,
2223 sde->tx_tail,
2224 sde->tx_head,
2225 sde->descq_tail,
2226 sde->descq_head,
2227 !list_empty(&sde->flushlist),
2228 sde->descq_full_count,
2229 (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID));
2230
2231 /* print info for each entry in the descriptor queue */
2232 while (head != tail) {
2233 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
2234
2235 descqp = &sde->descq[head];
2236 desc[0] = le64_to_cpu(descqp->qw[0]);
2237 desc[1] = le64_to_cpu(descqp->qw[1]);
2238 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
2239 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
2240 'H' : '-';
2241 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
2242 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
2243 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
2244 & SDMA_DESC0_PHY_ADDR_MASK;
2245 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
2246 & SDMA_DESC1_GENERATION_MASK;
2247 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
2248 & SDMA_DESC0_BYTE_COUNT_MASK;
2249 seq_printf(s,
2250 "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
2251 head, flags, addr, gen, len);
2252 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
2253 seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n",
2254 (u8)((desc[1] &
2255 SDMA_DESC1_HEADER_INDEX_SMASK) >>
2256 SDMA_DESC1_HEADER_INDEX_SHIFT),
2257 (u8)((desc[1] &
2258 SDMA_DESC1_HEADER_MODE_SMASK) >>
2259 SDMA_DESC1_HEADER_MODE_SHIFT));
2260 head = (head + 1) & sde->sdma_mask;
2261 }
2262 }
2263
2264 /*
2265 * add the generation number into
2266 * the qw1 and return
2267 */
add_gen(struct sdma_engine * sde,u64 qw1)2268 static inline u64 add_gen(struct sdma_engine *sde, u64 qw1)
2269 {
2270 u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3;
2271
2272 qw1 &= ~SDMA_DESC1_GENERATION_SMASK;
2273 qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK)
2274 << SDMA_DESC1_GENERATION_SHIFT;
2275 return qw1;
2276 }
2277
2278 /*
2279 * This routine submits the indicated tx
2280 *
2281 * Space has already been guaranteed and
2282 * tail side of ring is locked.
2283 *
2284 * The hardware tail update is done
2285 * in the caller and that is facilitated
2286 * by returning the new tail.
2287 *
2288 * There is special case logic for ahg
2289 * to not add the generation number for
2290 * up to 2 descriptors that follow the
2291 * first descriptor.
2292 *
2293 */
submit_tx(struct sdma_engine * sde,struct sdma_txreq * tx)2294 static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx)
2295 {
2296 int i;
2297 u16 tail;
2298 struct sdma_desc *descp = tx->descp;
2299 u8 skip = 0, mode = ahg_mode(tx);
2300
2301 tail = sde->descq_tail & sde->sdma_mask;
2302 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2303 sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1]));
2304 trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1],
2305 tail, &sde->descq[tail]);
2306 tail = ++sde->descq_tail & sde->sdma_mask;
2307 descp++;
2308 if (mode > SDMA_AHG_APPLY_UPDATE1)
2309 skip = mode >> 1;
2310 for (i = 1; i < tx->num_desc; i++, descp++) {
2311 u64 qw1;
2312
2313 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2314 if (skip) {
2315 /* edits don't have generation */
2316 qw1 = descp->qw[1];
2317 skip--;
2318 } else {
2319 /* replace generation with real one for non-edits */
2320 qw1 = add_gen(sde, descp->qw[1]);
2321 }
2322 sde->descq[tail].qw[1] = cpu_to_le64(qw1);
2323 trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1,
2324 tail, &sde->descq[tail]);
2325 tail = ++sde->descq_tail & sde->sdma_mask;
2326 }
2327 tx->next_descq_idx = tail;
2328 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2329 tx->sn = sde->tail_sn++;
2330 trace_hfi1_sdma_in_sn(sde, tx->sn);
2331 WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]);
2332 #endif
2333 sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx;
2334 sde->desc_avail -= tx->num_desc;
2335 return tail;
2336 }
2337
2338 /*
2339 * Check for progress
2340 */
sdma_check_progress(struct sdma_engine * sde,struct iowait_work * wait,struct sdma_txreq * tx,bool pkts_sent)2341 static int sdma_check_progress(
2342 struct sdma_engine *sde,
2343 struct iowait_work *wait,
2344 struct sdma_txreq *tx,
2345 bool pkts_sent)
2346 {
2347 int ret;
2348
2349 sde->desc_avail = sdma_descq_freecnt(sde);
2350 if (tx->num_desc <= sde->desc_avail)
2351 return -EAGAIN;
2352 /* pulse the head_lock */
2353 if (wait && iowait_ioww_to_iow(wait)->sleep) {
2354 unsigned seq;
2355
2356 seq = raw_seqcount_begin(
2357 (const seqcount_t *)&sde->head_lock.seqcount);
2358 ret = wait->iow->sleep(sde, wait, tx, seq, pkts_sent);
2359 if (ret == -EAGAIN)
2360 sde->desc_avail = sdma_descq_freecnt(sde);
2361 } else {
2362 ret = -EBUSY;
2363 }
2364 return ret;
2365 }
2366
2367 /**
2368 * sdma_send_txreq() - submit a tx req to ring
2369 * @sde: sdma engine to use
2370 * @wait: SE wait structure to use when full (may be NULL)
2371 * @tx: sdma_txreq to submit
2372 * @pkts_sent: has any packet been sent yet?
2373 *
2374 * The call submits the tx into the ring. If a iowait structure is non-NULL
2375 * the packet will be queued to the list in wait.
2376 *
2377 * Return:
2378 * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in
2379 * ring (wait == NULL)
2380 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2381 */
sdma_send_txreq(struct sdma_engine * sde,struct iowait_work * wait,struct sdma_txreq * tx,bool pkts_sent)2382 int sdma_send_txreq(struct sdma_engine *sde,
2383 struct iowait_work *wait,
2384 struct sdma_txreq *tx,
2385 bool pkts_sent)
2386 {
2387 int ret = 0;
2388 u16 tail;
2389 unsigned long flags;
2390
2391 /* user should have supplied entire packet */
2392 if (unlikely(tx->tlen))
2393 return -EINVAL;
2394 tx->wait = iowait_ioww_to_iow(wait);
2395 spin_lock_irqsave(&sde->tail_lock, flags);
2396 retry:
2397 if (unlikely(!__sdma_running(sde)))
2398 goto unlock_noconn;
2399 if (unlikely(tx->num_desc > sde->desc_avail))
2400 goto nodesc;
2401 tail = submit_tx(sde, tx);
2402 if (wait)
2403 iowait_sdma_inc(iowait_ioww_to_iow(wait));
2404 sdma_update_tail(sde, tail);
2405 unlock:
2406 spin_unlock_irqrestore(&sde->tail_lock, flags);
2407 return ret;
2408 unlock_noconn:
2409 if (wait)
2410 iowait_sdma_inc(iowait_ioww_to_iow(wait));
2411 tx->next_descq_idx = 0;
2412 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2413 tx->sn = sde->tail_sn++;
2414 trace_hfi1_sdma_in_sn(sde, tx->sn);
2415 #endif
2416 spin_lock(&sde->flushlist_lock);
2417 list_add_tail(&tx->list, &sde->flushlist);
2418 spin_unlock(&sde->flushlist_lock);
2419 iowait_inc_wait_count(wait, tx->num_desc);
2420 queue_work_on(sde->cpu, system_highpri_wq, &sde->flush_worker);
2421 ret = -ECOMM;
2422 goto unlock;
2423 nodesc:
2424 ret = sdma_check_progress(sde, wait, tx, pkts_sent);
2425 if (ret == -EAGAIN) {
2426 ret = 0;
2427 goto retry;
2428 }
2429 sde->descq_full_count++;
2430 goto unlock;
2431 }
2432
2433 /**
2434 * sdma_send_txlist() - submit a list of tx req to ring
2435 * @sde: sdma engine to use
2436 * @wait: SE wait structure to use when full (may be NULL)
2437 * @tx_list: list of sdma_txreqs to submit
2438 * @count: pointer to a u16 which, after return will contain the total number of
2439 * sdma_txreqs removed from the tx_list. This will include sdma_txreqs
2440 * whose SDMA descriptors are submitted to the ring and the sdma_txreqs
2441 * which are added to SDMA engine flush list if the SDMA engine state is
2442 * not running.
2443 *
2444 * The call submits the list into the ring.
2445 *
2446 * If the iowait structure is non-NULL and not equal to the iowait list
2447 * the unprocessed part of the list will be appended to the list in wait.
2448 *
2449 * In all cases, the tx_list will be updated so the head of the tx_list is
2450 * the list of descriptors that have yet to be transmitted.
2451 *
2452 * The intent of this call is to provide a more efficient
2453 * way of submitting multiple packets to SDMA while holding the tail
2454 * side locking.
2455 *
2456 * Return:
2457 * 0 - Success,
2458 * -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring (wait == NULL)
2459 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2460 */
sdma_send_txlist(struct sdma_engine * sde,struct iowait_work * wait,struct list_head * tx_list,u16 * count_out)2461 int sdma_send_txlist(struct sdma_engine *sde, struct iowait_work *wait,
2462 struct list_head *tx_list, u16 *count_out)
2463 {
2464 struct sdma_txreq *tx, *tx_next;
2465 int ret = 0;
2466 unsigned long flags;
2467 u16 tail = INVALID_TAIL;
2468 u32 submit_count = 0, flush_count = 0, total_count;
2469
2470 spin_lock_irqsave(&sde->tail_lock, flags);
2471 retry:
2472 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2473 tx->wait = iowait_ioww_to_iow(wait);
2474 if (unlikely(!__sdma_running(sde)))
2475 goto unlock_noconn;
2476 if (unlikely(tx->num_desc > sde->desc_avail))
2477 goto nodesc;
2478 if (unlikely(tx->tlen)) {
2479 ret = -EINVAL;
2480 goto update_tail;
2481 }
2482 list_del_init(&tx->list);
2483 tail = submit_tx(sde, tx);
2484 submit_count++;
2485 if (tail != INVALID_TAIL &&
2486 (submit_count & SDMA_TAIL_UPDATE_THRESH) == 0) {
2487 sdma_update_tail(sde, tail);
2488 tail = INVALID_TAIL;
2489 }
2490 }
2491 update_tail:
2492 total_count = submit_count + flush_count;
2493 if (wait) {
2494 iowait_sdma_add(iowait_ioww_to_iow(wait), total_count);
2495 iowait_starve_clear(submit_count > 0,
2496 iowait_ioww_to_iow(wait));
2497 }
2498 if (tail != INVALID_TAIL)
2499 sdma_update_tail(sde, tail);
2500 spin_unlock_irqrestore(&sde->tail_lock, flags);
2501 *count_out = total_count;
2502 return ret;
2503 unlock_noconn:
2504 spin_lock(&sde->flushlist_lock);
2505 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2506 tx->wait = iowait_ioww_to_iow(wait);
2507 list_del_init(&tx->list);
2508 tx->next_descq_idx = 0;
2509 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2510 tx->sn = sde->tail_sn++;
2511 trace_hfi1_sdma_in_sn(sde, tx->sn);
2512 #endif
2513 list_add_tail(&tx->list, &sde->flushlist);
2514 flush_count++;
2515 iowait_inc_wait_count(wait, tx->num_desc);
2516 }
2517 spin_unlock(&sde->flushlist_lock);
2518 queue_work_on(sde->cpu, system_highpri_wq, &sde->flush_worker);
2519 ret = -ECOMM;
2520 goto update_tail;
2521 nodesc:
2522 ret = sdma_check_progress(sde, wait, tx, submit_count > 0);
2523 if (ret == -EAGAIN) {
2524 ret = 0;
2525 goto retry;
2526 }
2527 sde->descq_full_count++;
2528 goto update_tail;
2529 }
2530
sdma_process_event(struct sdma_engine * sde,enum sdma_events event)2531 static void sdma_process_event(struct sdma_engine *sde, enum sdma_events event)
2532 {
2533 unsigned long flags;
2534
2535 spin_lock_irqsave(&sde->tail_lock, flags);
2536 write_seqlock(&sde->head_lock);
2537
2538 __sdma_process_event(sde, event);
2539
2540 if (sde->state.current_state == sdma_state_s99_running)
2541 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
2542
2543 write_sequnlock(&sde->head_lock);
2544 spin_unlock_irqrestore(&sde->tail_lock, flags);
2545 }
2546
__sdma_process_event(struct sdma_engine * sde,enum sdma_events event)2547 static void __sdma_process_event(struct sdma_engine *sde,
2548 enum sdma_events event)
2549 {
2550 struct sdma_state *ss = &sde->state;
2551 int need_progress = 0;
2552
2553 /* CONFIG SDMA temporary */
2554 #ifdef CONFIG_SDMA_VERBOSITY
2555 dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx,
2556 sdma_state_names[ss->current_state],
2557 sdma_event_names[event]);
2558 #endif
2559
2560 switch (ss->current_state) {
2561 case sdma_state_s00_hw_down:
2562 switch (event) {
2563 case sdma_event_e00_go_hw_down:
2564 break;
2565 case sdma_event_e30_go_running:
2566 /*
2567 * If down, but running requested (usually result
2568 * of link up, then we need to start up.
2569 * This can happen when hw down is requested while
2570 * bringing the link up with traffic active on
2571 * 7220, e.g.
2572 */
2573 ss->go_s99_running = 1;
2574 fallthrough; /* and start dma engine */
2575 case sdma_event_e10_go_hw_start:
2576 /* This reference means the state machine is started */
2577 sdma_get(&sde->state);
2578 sdma_set_state(sde,
2579 sdma_state_s10_hw_start_up_halt_wait);
2580 break;
2581 case sdma_event_e15_hw_halt_done:
2582 break;
2583 case sdma_event_e25_hw_clean_up_done:
2584 break;
2585 case sdma_event_e40_sw_cleaned:
2586 sdma_sw_tear_down(sde);
2587 break;
2588 case sdma_event_e50_hw_cleaned:
2589 break;
2590 case sdma_event_e60_hw_halted:
2591 break;
2592 case sdma_event_e70_go_idle:
2593 break;
2594 case sdma_event_e80_hw_freeze:
2595 break;
2596 case sdma_event_e81_hw_frozen:
2597 break;
2598 case sdma_event_e82_hw_unfreeze:
2599 break;
2600 case sdma_event_e85_link_down:
2601 break;
2602 case sdma_event_e90_sw_halted:
2603 break;
2604 }
2605 break;
2606
2607 case sdma_state_s10_hw_start_up_halt_wait:
2608 switch (event) {
2609 case sdma_event_e00_go_hw_down:
2610 sdma_set_state(sde, sdma_state_s00_hw_down);
2611 sdma_sw_tear_down(sde);
2612 break;
2613 case sdma_event_e10_go_hw_start:
2614 break;
2615 case sdma_event_e15_hw_halt_done:
2616 sdma_set_state(sde,
2617 sdma_state_s15_hw_start_up_clean_wait);
2618 sdma_start_hw_clean_up(sde);
2619 break;
2620 case sdma_event_e25_hw_clean_up_done:
2621 break;
2622 case sdma_event_e30_go_running:
2623 ss->go_s99_running = 1;
2624 break;
2625 case sdma_event_e40_sw_cleaned:
2626 break;
2627 case sdma_event_e50_hw_cleaned:
2628 break;
2629 case sdma_event_e60_hw_halted:
2630 schedule_work(&sde->err_halt_worker);
2631 break;
2632 case sdma_event_e70_go_idle:
2633 ss->go_s99_running = 0;
2634 break;
2635 case sdma_event_e80_hw_freeze:
2636 break;
2637 case sdma_event_e81_hw_frozen:
2638 break;
2639 case sdma_event_e82_hw_unfreeze:
2640 break;
2641 case sdma_event_e85_link_down:
2642 break;
2643 case sdma_event_e90_sw_halted:
2644 break;
2645 }
2646 break;
2647
2648 case sdma_state_s15_hw_start_up_clean_wait:
2649 switch (event) {
2650 case sdma_event_e00_go_hw_down:
2651 sdma_set_state(sde, sdma_state_s00_hw_down);
2652 sdma_sw_tear_down(sde);
2653 break;
2654 case sdma_event_e10_go_hw_start:
2655 break;
2656 case sdma_event_e15_hw_halt_done:
2657 break;
2658 case sdma_event_e25_hw_clean_up_done:
2659 sdma_hw_start_up(sde);
2660 sdma_set_state(sde, ss->go_s99_running ?
2661 sdma_state_s99_running :
2662 sdma_state_s20_idle);
2663 break;
2664 case sdma_event_e30_go_running:
2665 ss->go_s99_running = 1;
2666 break;
2667 case sdma_event_e40_sw_cleaned:
2668 break;
2669 case sdma_event_e50_hw_cleaned:
2670 break;
2671 case sdma_event_e60_hw_halted:
2672 break;
2673 case sdma_event_e70_go_idle:
2674 ss->go_s99_running = 0;
2675 break;
2676 case sdma_event_e80_hw_freeze:
2677 break;
2678 case sdma_event_e81_hw_frozen:
2679 break;
2680 case sdma_event_e82_hw_unfreeze:
2681 break;
2682 case sdma_event_e85_link_down:
2683 break;
2684 case sdma_event_e90_sw_halted:
2685 break;
2686 }
2687 break;
2688
2689 case sdma_state_s20_idle:
2690 switch (event) {
2691 case sdma_event_e00_go_hw_down:
2692 sdma_set_state(sde, sdma_state_s00_hw_down);
2693 sdma_sw_tear_down(sde);
2694 break;
2695 case sdma_event_e10_go_hw_start:
2696 break;
2697 case sdma_event_e15_hw_halt_done:
2698 break;
2699 case sdma_event_e25_hw_clean_up_done:
2700 break;
2701 case sdma_event_e30_go_running:
2702 sdma_set_state(sde, sdma_state_s99_running);
2703 ss->go_s99_running = 1;
2704 break;
2705 case sdma_event_e40_sw_cleaned:
2706 break;
2707 case sdma_event_e50_hw_cleaned:
2708 break;
2709 case sdma_event_e60_hw_halted:
2710 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
2711 schedule_work(&sde->err_halt_worker);
2712 break;
2713 case sdma_event_e70_go_idle:
2714 break;
2715 case sdma_event_e85_link_down:
2716 case sdma_event_e80_hw_freeze:
2717 sdma_set_state(sde, sdma_state_s80_hw_freeze);
2718 atomic_dec(&sde->dd->sdma_unfreeze_count);
2719 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2720 break;
2721 case sdma_event_e81_hw_frozen:
2722 break;
2723 case sdma_event_e82_hw_unfreeze:
2724 break;
2725 case sdma_event_e90_sw_halted:
2726 break;
2727 }
2728 break;
2729
2730 case sdma_state_s30_sw_clean_up_wait:
2731 switch (event) {
2732 case sdma_event_e00_go_hw_down:
2733 sdma_set_state(sde, sdma_state_s00_hw_down);
2734 break;
2735 case sdma_event_e10_go_hw_start:
2736 break;
2737 case sdma_event_e15_hw_halt_done:
2738 break;
2739 case sdma_event_e25_hw_clean_up_done:
2740 break;
2741 case sdma_event_e30_go_running:
2742 ss->go_s99_running = 1;
2743 break;
2744 case sdma_event_e40_sw_cleaned:
2745 sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait);
2746 sdma_start_hw_clean_up(sde);
2747 break;
2748 case sdma_event_e50_hw_cleaned:
2749 break;
2750 case sdma_event_e60_hw_halted:
2751 break;
2752 case sdma_event_e70_go_idle:
2753 ss->go_s99_running = 0;
2754 break;
2755 case sdma_event_e80_hw_freeze:
2756 break;
2757 case sdma_event_e81_hw_frozen:
2758 break;
2759 case sdma_event_e82_hw_unfreeze:
2760 break;
2761 case sdma_event_e85_link_down:
2762 ss->go_s99_running = 0;
2763 break;
2764 case sdma_event_e90_sw_halted:
2765 break;
2766 }
2767 break;
2768
2769 case sdma_state_s40_hw_clean_up_wait:
2770 switch (event) {
2771 case sdma_event_e00_go_hw_down:
2772 sdma_set_state(sde, sdma_state_s00_hw_down);
2773 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2774 break;
2775 case sdma_event_e10_go_hw_start:
2776 break;
2777 case sdma_event_e15_hw_halt_done:
2778 break;
2779 case sdma_event_e25_hw_clean_up_done:
2780 sdma_hw_start_up(sde);
2781 sdma_set_state(sde, ss->go_s99_running ?
2782 sdma_state_s99_running :
2783 sdma_state_s20_idle);
2784 break;
2785 case sdma_event_e30_go_running:
2786 ss->go_s99_running = 1;
2787 break;
2788 case sdma_event_e40_sw_cleaned:
2789 break;
2790 case sdma_event_e50_hw_cleaned:
2791 break;
2792 case sdma_event_e60_hw_halted:
2793 break;
2794 case sdma_event_e70_go_idle:
2795 ss->go_s99_running = 0;
2796 break;
2797 case sdma_event_e80_hw_freeze:
2798 break;
2799 case sdma_event_e81_hw_frozen:
2800 break;
2801 case sdma_event_e82_hw_unfreeze:
2802 break;
2803 case sdma_event_e85_link_down:
2804 ss->go_s99_running = 0;
2805 break;
2806 case sdma_event_e90_sw_halted:
2807 break;
2808 }
2809 break;
2810
2811 case sdma_state_s50_hw_halt_wait:
2812 switch (event) {
2813 case sdma_event_e00_go_hw_down:
2814 sdma_set_state(sde, sdma_state_s00_hw_down);
2815 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2816 break;
2817 case sdma_event_e10_go_hw_start:
2818 break;
2819 case sdma_event_e15_hw_halt_done:
2820 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
2821 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2822 break;
2823 case sdma_event_e25_hw_clean_up_done:
2824 break;
2825 case sdma_event_e30_go_running:
2826 ss->go_s99_running = 1;
2827 break;
2828 case sdma_event_e40_sw_cleaned:
2829 break;
2830 case sdma_event_e50_hw_cleaned:
2831 break;
2832 case sdma_event_e60_hw_halted:
2833 schedule_work(&sde->err_halt_worker);
2834 break;
2835 case sdma_event_e70_go_idle:
2836 ss->go_s99_running = 0;
2837 break;
2838 case sdma_event_e80_hw_freeze:
2839 break;
2840 case sdma_event_e81_hw_frozen:
2841 break;
2842 case sdma_event_e82_hw_unfreeze:
2843 break;
2844 case sdma_event_e85_link_down:
2845 ss->go_s99_running = 0;
2846 break;
2847 case sdma_event_e90_sw_halted:
2848 break;
2849 }
2850 break;
2851
2852 case sdma_state_s60_idle_halt_wait:
2853 switch (event) {
2854 case sdma_event_e00_go_hw_down:
2855 sdma_set_state(sde, sdma_state_s00_hw_down);
2856 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2857 break;
2858 case sdma_event_e10_go_hw_start:
2859 break;
2860 case sdma_event_e15_hw_halt_done:
2861 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
2862 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2863 break;
2864 case sdma_event_e25_hw_clean_up_done:
2865 break;
2866 case sdma_event_e30_go_running:
2867 ss->go_s99_running = 1;
2868 break;
2869 case sdma_event_e40_sw_cleaned:
2870 break;
2871 case sdma_event_e50_hw_cleaned:
2872 break;
2873 case sdma_event_e60_hw_halted:
2874 schedule_work(&sde->err_halt_worker);
2875 break;
2876 case sdma_event_e70_go_idle:
2877 ss->go_s99_running = 0;
2878 break;
2879 case sdma_event_e80_hw_freeze:
2880 break;
2881 case sdma_event_e81_hw_frozen:
2882 break;
2883 case sdma_event_e82_hw_unfreeze:
2884 break;
2885 case sdma_event_e85_link_down:
2886 break;
2887 case sdma_event_e90_sw_halted:
2888 break;
2889 }
2890 break;
2891
2892 case sdma_state_s80_hw_freeze:
2893 switch (event) {
2894 case sdma_event_e00_go_hw_down:
2895 sdma_set_state(sde, sdma_state_s00_hw_down);
2896 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2897 break;
2898 case sdma_event_e10_go_hw_start:
2899 break;
2900 case sdma_event_e15_hw_halt_done:
2901 break;
2902 case sdma_event_e25_hw_clean_up_done:
2903 break;
2904 case sdma_event_e30_go_running:
2905 ss->go_s99_running = 1;
2906 break;
2907 case sdma_event_e40_sw_cleaned:
2908 break;
2909 case sdma_event_e50_hw_cleaned:
2910 break;
2911 case sdma_event_e60_hw_halted:
2912 break;
2913 case sdma_event_e70_go_idle:
2914 ss->go_s99_running = 0;
2915 break;
2916 case sdma_event_e80_hw_freeze:
2917 break;
2918 case sdma_event_e81_hw_frozen:
2919 sdma_set_state(sde, sdma_state_s82_freeze_sw_clean);
2920 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2921 break;
2922 case sdma_event_e82_hw_unfreeze:
2923 break;
2924 case sdma_event_e85_link_down:
2925 break;
2926 case sdma_event_e90_sw_halted:
2927 break;
2928 }
2929 break;
2930
2931 case sdma_state_s82_freeze_sw_clean:
2932 switch (event) {
2933 case sdma_event_e00_go_hw_down:
2934 sdma_set_state(sde, sdma_state_s00_hw_down);
2935 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2936 break;
2937 case sdma_event_e10_go_hw_start:
2938 break;
2939 case sdma_event_e15_hw_halt_done:
2940 break;
2941 case sdma_event_e25_hw_clean_up_done:
2942 break;
2943 case sdma_event_e30_go_running:
2944 ss->go_s99_running = 1;
2945 break;
2946 case sdma_event_e40_sw_cleaned:
2947 /* notify caller this engine is done cleaning */
2948 atomic_dec(&sde->dd->sdma_unfreeze_count);
2949 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2950 break;
2951 case sdma_event_e50_hw_cleaned:
2952 break;
2953 case sdma_event_e60_hw_halted:
2954 break;
2955 case sdma_event_e70_go_idle:
2956 ss->go_s99_running = 0;
2957 break;
2958 case sdma_event_e80_hw_freeze:
2959 break;
2960 case sdma_event_e81_hw_frozen:
2961 break;
2962 case sdma_event_e82_hw_unfreeze:
2963 sdma_hw_start_up(sde);
2964 sdma_set_state(sde, ss->go_s99_running ?
2965 sdma_state_s99_running :
2966 sdma_state_s20_idle);
2967 break;
2968 case sdma_event_e85_link_down:
2969 break;
2970 case sdma_event_e90_sw_halted:
2971 break;
2972 }
2973 break;
2974
2975 case sdma_state_s99_running:
2976 switch (event) {
2977 case sdma_event_e00_go_hw_down:
2978 sdma_set_state(sde, sdma_state_s00_hw_down);
2979 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2980 break;
2981 case sdma_event_e10_go_hw_start:
2982 break;
2983 case sdma_event_e15_hw_halt_done:
2984 break;
2985 case sdma_event_e25_hw_clean_up_done:
2986 break;
2987 case sdma_event_e30_go_running:
2988 break;
2989 case sdma_event_e40_sw_cleaned:
2990 break;
2991 case sdma_event_e50_hw_cleaned:
2992 break;
2993 case sdma_event_e60_hw_halted:
2994 need_progress = 1;
2995 sdma_err_progress_check_schedule(sde);
2996 fallthrough;
2997 case sdma_event_e90_sw_halted:
2998 /*
2999 * SW initiated halt does not perform engines
3000 * progress check
3001 */
3002 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
3003 schedule_work(&sde->err_halt_worker);
3004 break;
3005 case sdma_event_e70_go_idle:
3006 sdma_set_state(sde, sdma_state_s60_idle_halt_wait);
3007 break;
3008 case sdma_event_e85_link_down:
3009 ss->go_s99_running = 0;
3010 fallthrough;
3011 case sdma_event_e80_hw_freeze:
3012 sdma_set_state(sde, sdma_state_s80_hw_freeze);
3013 atomic_dec(&sde->dd->sdma_unfreeze_count);
3014 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
3015 break;
3016 case sdma_event_e81_hw_frozen:
3017 break;
3018 case sdma_event_e82_hw_unfreeze:
3019 break;
3020 }
3021 break;
3022 }
3023
3024 ss->last_event = event;
3025 if (need_progress)
3026 sdma_make_progress(sde, 0);
3027 }
3028
3029 /*
3030 * _extend_sdma_tx_descs() - helper to extend txreq
3031 *
3032 * This is called once the initial nominal allocation
3033 * of descriptors in the sdma_txreq is exhausted.
3034 *
3035 * The code will bump the allocation up to the max
3036 * of MAX_DESC (64) descriptors. There doesn't seem
3037 * much point in an interim step. The last descriptor
3038 * is reserved for coalesce buffer in order to support
3039 * cases where input packet has >MAX_DESC iovecs.
3040 *
3041 */
_extend_sdma_tx_descs(struct hfi1_devdata * dd,struct sdma_txreq * tx)3042 static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3043 {
3044 int i;
3045 struct sdma_desc *descp;
3046
3047 /* Handle last descriptor */
3048 if (unlikely((tx->num_desc == (MAX_DESC - 1)))) {
3049 /* if tlen is 0, it is for padding, release last descriptor */
3050 if (!tx->tlen) {
3051 tx->desc_limit = MAX_DESC;
3052 } else if (!tx->coalesce_buf) {
3053 /* allocate coalesce buffer with space for padding */
3054 tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32),
3055 GFP_ATOMIC);
3056 if (!tx->coalesce_buf)
3057 goto enomem;
3058 tx->coalesce_idx = 0;
3059 }
3060 return 0;
3061 }
3062
3063 if (unlikely(tx->num_desc == MAX_DESC))
3064 goto enomem;
3065
3066 descp = kmalloc_array(MAX_DESC, sizeof(struct sdma_desc), GFP_ATOMIC);
3067 if (!descp)
3068 goto enomem;
3069 tx->descp = descp;
3070
3071 /* reserve last descriptor for coalescing */
3072 tx->desc_limit = MAX_DESC - 1;
3073 /* copy ones already built */
3074 for (i = 0; i < tx->num_desc; i++)
3075 tx->descp[i] = tx->descs[i];
3076 return 0;
3077 enomem:
3078 __sdma_txclean(dd, tx);
3079 return -ENOMEM;
3080 }
3081
3082 /*
3083 * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors
3084 *
3085 * This is called once the initial nominal allocation of descriptors
3086 * in the sdma_txreq is exhausted.
3087 *
3088 * This function calls _extend_sdma_tx_descs to extend or allocate
3089 * coalesce buffer. If there is a allocated coalesce buffer, it will
3090 * copy the input packet data into the coalesce buffer. It also adds
3091 * coalesce buffer descriptor once when whole packet is received.
3092 *
3093 * Return:
3094 * <0 - error
3095 * 0 - coalescing, don't populate descriptor
3096 * 1 - continue with populating descriptor
3097 */
ext_coal_sdma_tx_descs(struct hfi1_devdata * dd,struct sdma_txreq * tx,int type,void * kvaddr,struct page * page,unsigned long offset,u16 len)3098 int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
3099 int type, void *kvaddr, struct page *page,
3100 unsigned long offset, u16 len)
3101 {
3102 int pad_len, rval;
3103 dma_addr_t addr;
3104
3105 rval = _extend_sdma_tx_descs(dd, tx);
3106 if (rval) {
3107 __sdma_txclean(dd, tx);
3108 return rval;
3109 }
3110
3111 /* If coalesce buffer is allocated, copy data into it */
3112 if (tx->coalesce_buf) {
3113 if (type == SDMA_MAP_NONE) {
3114 __sdma_txclean(dd, tx);
3115 return -EINVAL;
3116 }
3117
3118 if (type == SDMA_MAP_PAGE) {
3119 kvaddr = kmap(page);
3120 kvaddr += offset;
3121 } else if (WARN_ON(!kvaddr)) {
3122 __sdma_txclean(dd, tx);
3123 return -EINVAL;
3124 }
3125
3126 memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len);
3127 tx->coalesce_idx += len;
3128 if (type == SDMA_MAP_PAGE)
3129 kunmap(page);
3130
3131 /* If there is more data, return */
3132 if (tx->tlen - tx->coalesce_idx)
3133 return 0;
3134
3135 /* Whole packet is received; add any padding */
3136 pad_len = tx->packet_len & (sizeof(u32) - 1);
3137 if (pad_len) {
3138 pad_len = sizeof(u32) - pad_len;
3139 memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len);
3140 /* padding is taken care of for coalescing case */
3141 tx->packet_len += pad_len;
3142 tx->tlen += pad_len;
3143 }
3144
3145 /* dma map the coalesce buffer */
3146 addr = dma_map_single(&dd->pcidev->dev,
3147 tx->coalesce_buf,
3148 tx->tlen,
3149 DMA_TO_DEVICE);
3150
3151 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
3152 __sdma_txclean(dd, tx);
3153 return -ENOSPC;
3154 }
3155
3156 /* Add descriptor for coalesce buffer */
3157 tx->desc_limit = MAX_DESC;
3158 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, NULL, tx,
3159 addr, tx->tlen);
3160 }
3161
3162 return 1;
3163 }
3164
3165 /* Update sdes when the lmc changes */
sdma_update_lmc(struct hfi1_devdata * dd,u64 mask,u32 lid)3166 void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid)
3167 {
3168 struct sdma_engine *sde;
3169 int i;
3170 u64 sreg;
3171
3172 sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) <<
3173 SD(CHECK_SLID_MASK_SHIFT)) |
3174 (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) <<
3175 SD(CHECK_SLID_VALUE_SHIFT));
3176
3177 for (i = 0; i < dd->num_sdma; i++) {
3178 hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x",
3179 i, (u32)sreg);
3180 sde = &dd->per_sdma[i];
3181 write_sde_csr(sde, SD(CHECK_SLID), sreg);
3182 }
3183 }
3184
3185 /* tx not dword sized - pad */
_pad_sdma_tx_descs(struct hfi1_devdata * dd,struct sdma_txreq * tx)3186 int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3187 {
3188 int rval = 0;
3189
3190 tx->num_desc++;
3191 if ((unlikely(tx->num_desc == tx->desc_limit))) {
3192 rval = _extend_sdma_tx_descs(dd, tx);
3193 if (rval) {
3194 __sdma_txclean(dd, tx);
3195 return rval;
3196 }
3197 }
3198
3199 /* finish the one just added */
3200 make_tx_sdma_desc(
3201 tx,
3202 SDMA_MAP_NONE,
3203 NULL,
3204 dd->sdma_pad_phys,
3205 sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1)));
3206 _sdma_close_tx(dd, tx);
3207 return rval;
3208 }
3209
3210 /*
3211 * Add ahg to the sdma_txreq
3212 *
3213 * The logic will consume up to 3
3214 * descriptors at the beginning of
3215 * sdma_txreq.
3216 */
_sdma_txreq_ahgadd(struct sdma_txreq * tx,u8 num_ahg,u8 ahg_entry,u32 * ahg,u8 ahg_hlen)3217 void _sdma_txreq_ahgadd(
3218 struct sdma_txreq *tx,
3219 u8 num_ahg,
3220 u8 ahg_entry,
3221 u32 *ahg,
3222 u8 ahg_hlen)
3223 {
3224 u32 i, shift = 0, desc = 0;
3225 u8 mode;
3226
3227 WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4);
3228 /* compute mode */
3229 if (num_ahg == 1)
3230 mode = SDMA_AHG_APPLY_UPDATE1;
3231 else if (num_ahg <= 5)
3232 mode = SDMA_AHG_APPLY_UPDATE2;
3233 else
3234 mode = SDMA_AHG_APPLY_UPDATE3;
3235 tx->num_desc++;
3236 /* initialize to consumed descriptors to zero */
3237 switch (mode) {
3238 case SDMA_AHG_APPLY_UPDATE3:
3239 tx->num_desc++;
3240 tx->descs[2].qw[0] = 0;
3241 tx->descs[2].qw[1] = 0;
3242 fallthrough;
3243 case SDMA_AHG_APPLY_UPDATE2:
3244 tx->num_desc++;
3245 tx->descs[1].qw[0] = 0;
3246 tx->descs[1].qw[1] = 0;
3247 break;
3248 }
3249 ahg_hlen >>= 2;
3250 tx->descs[0].qw[1] |=
3251 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK)
3252 << SDMA_DESC1_HEADER_INDEX_SHIFT) |
3253 (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK)
3254 << SDMA_DESC1_HEADER_DWS_SHIFT) |
3255 (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK)
3256 << SDMA_DESC1_HEADER_MODE_SHIFT) |
3257 (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK)
3258 << SDMA_DESC1_HEADER_UPDATE1_SHIFT);
3259 for (i = 0; i < (num_ahg - 1); i++) {
3260 if (!shift && !(i & 2))
3261 desc++;
3262 tx->descs[desc].qw[!!(i & 2)] |=
3263 (((u64)ahg[i + 1])
3264 << shift);
3265 shift = (shift + 32) & 63;
3266 }
3267 }
3268
3269 /**
3270 * sdma_ahg_alloc - allocate an AHG entry
3271 * @sde: engine to allocate from
3272 *
3273 * Return:
3274 * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled,
3275 * -ENOSPC if an entry is not available
3276 */
sdma_ahg_alloc(struct sdma_engine * sde)3277 int sdma_ahg_alloc(struct sdma_engine *sde)
3278 {
3279 int nr;
3280 int oldbit;
3281
3282 if (!sde) {
3283 trace_hfi1_ahg_allocate(sde, -EINVAL);
3284 return -EINVAL;
3285 }
3286 while (1) {
3287 nr = ffz(READ_ONCE(sde->ahg_bits));
3288 if (nr > 31) {
3289 trace_hfi1_ahg_allocate(sde, -ENOSPC);
3290 return -ENOSPC;
3291 }
3292 oldbit = test_and_set_bit(nr, &sde->ahg_bits);
3293 if (!oldbit)
3294 break;
3295 cpu_relax();
3296 }
3297 trace_hfi1_ahg_allocate(sde, nr);
3298 return nr;
3299 }
3300
3301 /**
3302 * sdma_ahg_free - free an AHG entry
3303 * @sde: engine to return AHG entry
3304 * @ahg_index: index to free
3305 *
3306 * This routine frees the indicate AHG entry.
3307 */
sdma_ahg_free(struct sdma_engine * sde,int ahg_index)3308 void sdma_ahg_free(struct sdma_engine *sde, int ahg_index)
3309 {
3310 if (!sde)
3311 return;
3312 trace_hfi1_ahg_deallocate(sde, ahg_index);
3313 if (ahg_index < 0 || ahg_index > 31)
3314 return;
3315 clear_bit(ahg_index, &sde->ahg_bits);
3316 }
3317
3318 /*
3319 * SPC freeze handling for SDMA engines. Called when the driver knows
3320 * the SPC is going into a freeze but before the freeze is fully
3321 * settled. Generally an error interrupt.
3322 *
3323 * This event will pull the engine out of running so no more entries can be
3324 * added to the engine's queue.
3325 */
sdma_freeze_notify(struct hfi1_devdata * dd,int link_down)3326 void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down)
3327 {
3328 int i;
3329 enum sdma_events event = link_down ? sdma_event_e85_link_down :
3330 sdma_event_e80_hw_freeze;
3331
3332 /* set up the wait but do not wait here */
3333 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3334
3335 /* tell all engines to stop running and wait */
3336 for (i = 0; i < dd->num_sdma; i++)
3337 sdma_process_event(&dd->per_sdma[i], event);
3338
3339 /* sdma_freeze() will wait for all engines to have stopped */
3340 }
3341
3342 /*
3343 * SPC freeze handling for SDMA engines. Called when the driver knows
3344 * the SPC is fully frozen.
3345 */
sdma_freeze(struct hfi1_devdata * dd)3346 void sdma_freeze(struct hfi1_devdata *dd)
3347 {
3348 int i;
3349 int ret;
3350
3351 /*
3352 * Make sure all engines have moved out of the running state before
3353 * continuing.
3354 */
3355 ret = wait_event_interruptible(dd->sdma_unfreeze_wq,
3356 atomic_read(&dd->sdma_unfreeze_count) <=
3357 0);
3358 /* interrupted or count is negative, then unloading - just exit */
3359 if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0)
3360 return;
3361
3362 /* set up the count for the next wait */
3363 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3364
3365 /* tell all engines that the SPC is frozen, they can start cleaning */
3366 for (i = 0; i < dd->num_sdma; i++)
3367 sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen);
3368
3369 /*
3370 * Wait for everyone to finish software clean before exiting. The
3371 * software clean will read engine CSRs, so must be completed before
3372 * the next step, which will clear the engine CSRs.
3373 */
3374 (void)wait_event_interruptible(dd->sdma_unfreeze_wq,
3375 atomic_read(&dd->sdma_unfreeze_count) <= 0);
3376 /* no need to check results - done no matter what */
3377 }
3378
3379 /*
3380 * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen.
3381 *
3382 * The SPC freeze acts like a SDMA halt and a hardware clean combined. All
3383 * that is left is a software clean. We could do it after the SPC is fully
3384 * frozen, but then we'd have to add another state to wait for the unfreeze.
3385 * Instead, just defer the software clean until the unfreeze step.
3386 */
sdma_unfreeze(struct hfi1_devdata * dd)3387 void sdma_unfreeze(struct hfi1_devdata *dd)
3388 {
3389 int i;
3390
3391 /* tell all engines start freeze clean up */
3392 for (i = 0; i < dd->num_sdma; i++)
3393 sdma_process_event(&dd->per_sdma[i],
3394 sdma_event_e82_hw_unfreeze);
3395 }
3396
3397 /**
3398 * _sdma_engine_progress_schedule() - schedule progress on engine
3399 * @sde: sdma_engine to schedule progress
3400 *
3401 */
_sdma_engine_progress_schedule(struct sdma_engine * sde)3402 void _sdma_engine_progress_schedule(
3403 struct sdma_engine *sde)
3404 {
3405 trace_hfi1_sdma_engine_progress(sde, sde->progress_mask);
3406 /* assume we have selected a good cpu */
3407 write_csr(sde->dd,
3408 CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)),
3409 sde->progress_mask);
3410 }
3411