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Searched defs:shrn (Results 1 – 6 of 6) sorted by relevance

/third_party/ffmpeg/libavcodec/arm/
Dhpeldsp_neon.S299 shrn d5, q10, #2 define
309 shrn d7, q10, #2 define
324 shrn d5, q10, #2 define
332 shrn d7, q10, #2 define
347 .macro shrn rd, rn, rm macro
356 .macro shrn rd, rn, rm macro
/third_party/vixl/test/aarch64/
Dtest-trace-aarch64.cc1425 __ shrn(v5.V2S(), v1.V2D(), 28); in GenerateTestSequenceNEON() local
1426 __ shrn(v29.V4H(), v18.V4S(), 7); in GenerateTestSequenceNEON() local
1427 __ shrn(v17.V8B(), v29.V8H(), 2); in GenerateTestSequenceNEON() local
/third_party/node/deps/v8/src/codegen/arm64/
Dassembler-arm64.cc1739 void Assembler::shrn(const VRegister& vd, const VRegister& vn, int shift) { in shrn() function in v8::internal::Assembler
/third_party/vixl/src/aarch64/
Dassembler-aarch64.cc5151 void Assembler::shrn(const VRegister& vd, const VRegister& vn, int shift) { in shrn() function in vixl::aarch64::Assembler
Dlogic-aarch64.cc3178 LogicVRegister Simulator::shrn(VectorFormat vform, in shrn() function in vixl::aarch64::Simulator
/third_party/node/deps/v8/src/execution/arm64/
Dsimulator-logic-arm64.cc2108 LogicVRegister Simulator::shrn(VectorFormat vform, LogicVRegister dst, in shrn() function in v8::internal::Simulator