1 #include <linux/gfp.h>
2 #include <linux/initrd.h>
3 #include <linux/ioport.h>
4 #include <linux/swap.h>
5 #include <linux/memblock.h>
6 #include <linux/swapfile.h>
7 #include <linux/swapops.h>
8 #include <linux/kmemleak.h>
9 #include <linux/sched/task.h>
10
11 #include <asm/set_memory.h>
12 #include <asm/cpu_device_id.h>
13 #include <asm/e820/api.h>
14 #include <asm/init.h>
15 #include <asm/page.h>
16 #include <asm/page_types.h>
17 #include <asm/sections.h>
18 #include <asm/setup.h>
19 #include <asm/tlbflush.h>
20 #include <asm/tlb.h>
21 #include <asm/proto.h>
22 #include <asm/dma.h> /* for MAX_DMA_PFN */
23 #include <asm/microcode.h>
24 #include <asm/kaslr.h>
25 #include <asm/hypervisor.h>
26 #include <asm/cpufeature.h>
27 #include <asm/pti.h>
28 #include <asm/text-patching.h>
29 #include <asm/memtype.h>
30
31 /*
32 * We need to define the tracepoints somewhere, and tlb.c
33 * is only compied when SMP=y.
34 */
35 #define CREATE_TRACE_POINTS
36 #include <trace/events/tlb.h>
37
38 #include "mm_internal.h"
39
40 /*
41 * Tables translating between page_cache_type_t and pte encoding.
42 *
43 * The default values are defined statically as minimal supported mode;
44 * WC and WT fall back to UC-. pat_init() updates these values to support
45 * more cache modes, WC and WT, when it is safe to do so. See pat_init()
46 * for the details. Note, __early_ioremap() used during early boot-time
47 * takes pgprot_t (pte encoding) and does not use these tables.
48 *
49 * Index into __cachemode2pte_tbl[] is the cachemode.
50 *
51 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
52 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
53 */
54 static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
55 [_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
56 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
57 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
58 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD,
59 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
60 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
61 };
62
cachemode2protval(enum page_cache_mode pcm)63 unsigned long cachemode2protval(enum page_cache_mode pcm)
64 {
65 if (likely(pcm == 0))
66 return 0;
67 return __cachemode2pte_tbl[pcm];
68 }
69 EXPORT_SYMBOL(cachemode2protval);
70
71 static uint8_t __pte2cachemode_tbl[8] = {
72 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
73 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
74 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
75 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC,
76 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
77 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
78 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
79 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
80 };
81
82 /*
83 * Check that the write-protect PAT entry is set for write-protect.
84 * To do this without making assumptions how PAT has been set up (Xen has
85 * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache
86 * mode via the __cachemode2pte_tbl[] into protection bits (those protection
87 * bits will select a cache mode of WP or better), and then translate the
88 * protection bits back into the cache mode using __pte2cm_idx() and the
89 * __pte2cachemode_tbl[] array. This will return the really used cache mode.
90 */
x86_has_pat_wp(void)91 bool x86_has_pat_wp(void)
92 {
93 uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP];
94
95 return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP;
96 }
97
pgprot2cachemode(pgprot_t pgprot)98 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
99 {
100 unsigned long masked;
101
102 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
103 if (likely(masked == 0))
104 return 0;
105 return __pte2cachemode_tbl[__pte2cm_idx(masked)];
106 }
107
108 static unsigned long __initdata pgt_buf_start;
109 static unsigned long __initdata pgt_buf_end;
110 static unsigned long __initdata pgt_buf_top;
111
112 static unsigned long min_pfn_mapped;
113
114 static bool __initdata can_use_brk_pgt = true;
115
116 /*
117 * Pages returned are already directly mapped.
118 *
119 * Changing that is likely to break Xen, see commit:
120 *
121 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve
122 *
123 * for detailed information.
124 */
alloc_low_pages(unsigned int num)125 __ref void *alloc_low_pages(unsigned int num)
126 {
127 unsigned long pfn;
128 int i;
129
130 if (after_bootmem) {
131 unsigned int order;
132
133 order = get_order((unsigned long)num << PAGE_SHIFT);
134 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
135 }
136
137 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) {
138 unsigned long ret = 0;
139
140 if (min_pfn_mapped < max_pfn_mapped) {
141 ret = memblock_find_in_range(
142 min_pfn_mapped << PAGE_SHIFT,
143 max_pfn_mapped << PAGE_SHIFT,
144 PAGE_SIZE * num , PAGE_SIZE);
145 }
146 if (ret)
147 memblock_reserve(ret, PAGE_SIZE * num);
148 else if (can_use_brk_pgt)
149 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE));
150
151 if (!ret)
152 panic("alloc_low_pages: can not alloc memory");
153
154 pfn = ret >> PAGE_SHIFT;
155 } else {
156 pfn = pgt_buf_end;
157 pgt_buf_end += num;
158 }
159
160 for (i = 0; i < num; i++) {
161 void *adr;
162
163 adr = __va((pfn + i) << PAGE_SHIFT);
164 clear_page(adr);
165 }
166
167 return __va(pfn << PAGE_SHIFT);
168 }
169
170 /*
171 * By default need 3 4k for initial PMD_SIZE, 3 4k for 0-ISA_END_ADDRESS.
172 * With KASLR memory randomization, depending on the machine e820 memory
173 * and the PUD alignment. We may need twice more pages when KASLR memory
174 * randomization is enabled.
175 */
176 #ifndef CONFIG_RANDOMIZE_MEMORY
177 #define INIT_PGD_PAGE_COUNT 6
178 #else
179 #define INIT_PGD_PAGE_COUNT 12
180 #endif
181 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE)
182 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE);
early_alloc_pgt_buf(void)183 void __init early_alloc_pgt_buf(void)
184 {
185 unsigned long tables = INIT_PGT_BUF_SIZE;
186 phys_addr_t base;
187
188 base = __pa(extend_brk(tables, PAGE_SIZE));
189
190 pgt_buf_start = base >> PAGE_SHIFT;
191 pgt_buf_end = pgt_buf_start;
192 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT);
193 }
194
195 int after_bootmem;
196
197 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES);
198
199 struct map_range {
200 unsigned long start;
201 unsigned long end;
202 unsigned page_size_mask;
203 };
204
205 static int page_size_mask;
206
207 /*
208 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
209 * enable and PPro Global page enable), so that any CPU's that boot
210 * up after us can get the correct flags. Invoked on the boot CPU.
211 */
cr4_set_bits_and_update_boot(unsigned long mask)212 static inline void cr4_set_bits_and_update_boot(unsigned long mask)
213 {
214 mmu_cr4_features |= mask;
215 if (trampoline_cr4_features)
216 *trampoline_cr4_features = mmu_cr4_features;
217 cr4_set_bits(mask);
218 }
219
probe_page_size_mask(void)220 static void __init probe_page_size_mask(void)
221 {
222 /*
223 * For pagealloc debugging, identity mapping will use small pages.
224 * This will simplify cpa(), which otherwise needs to support splitting
225 * large pages into small in interrupt context, etc.
226 */
227 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled())
228 page_size_mask |= 1 << PG_LEVEL_2M;
229 else
230 direct_gbpages = 0;
231
232 /* Enable PSE if available */
233 if (boot_cpu_has(X86_FEATURE_PSE))
234 cr4_set_bits_and_update_boot(X86_CR4_PSE);
235
236 /* Enable PGE if available */
237 __supported_pte_mask &= ~_PAGE_GLOBAL;
238 if (boot_cpu_has(X86_FEATURE_PGE)) {
239 cr4_set_bits_and_update_boot(X86_CR4_PGE);
240 __supported_pte_mask |= _PAGE_GLOBAL;
241 }
242
243 /* By the default is everything supported: */
244 __default_kernel_pte_mask = __supported_pte_mask;
245 /* Except when with PTI where the kernel is mostly non-Global: */
246 if (cpu_feature_enabled(X86_FEATURE_PTI))
247 __default_kernel_pte_mask &= ~_PAGE_GLOBAL;
248
249 /* Enable 1 GB linear kernel mappings if available: */
250 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) {
251 printk(KERN_INFO "Using GB pages for direct mapping\n");
252 page_size_mask |= 1 << PG_LEVEL_1G;
253 } else {
254 direct_gbpages = 0;
255 }
256 }
257
258 #define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \
259 .family = 6, \
260 .model = _model, \
261 }
262 /*
263 * INVLPG may not properly flush Global entries
264 * on these CPUs when PCIDs are enabled.
265 */
266 static const struct x86_cpu_id invlpg_miss_ids[] = {
267 INTEL_MATCH(INTEL_FAM6_ALDERLAKE ),
268 INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ),
269 INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ),
270 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ),
271 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P),
272 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S),
273 {}
274 };
275
setup_pcid(void)276 static void setup_pcid(void)
277 {
278 if (!IS_ENABLED(CONFIG_X86_64))
279 return;
280
281 if (!boot_cpu_has(X86_FEATURE_PCID))
282 return;
283
284 if (x86_match_cpu(invlpg_miss_ids)) {
285 pr_info("Incomplete global flushes, disabling PCID");
286 setup_clear_cpu_cap(X86_FEATURE_PCID);
287 return;
288 }
289
290 if (boot_cpu_has(X86_FEATURE_PGE)) {
291 /*
292 * This can't be cr4_set_bits_and_update_boot() -- the
293 * trampoline code can't handle CR4.PCIDE and it wouldn't
294 * do any good anyway. Despite the name,
295 * cr4_set_bits_and_update_boot() doesn't actually cause
296 * the bits in question to remain set all the way through
297 * the secondary boot asm.
298 *
299 * Instead, we brute-force it and set CR4.PCIDE manually in
300 * start_secondary().
301 */
302 cr4_set_bits(X86_CR4_PCIDE);
303
304 /*
305 * INVPCID's single-context modes (2/3) only work if we set
306 * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable
307 * on systems that have X86_CR4_PCIDE clear, or that have
308 * no INVPCID support at all.
309 */
310 if (boot_cpu_has(X86_FEATURE_INVPCID))
311 setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE);
312 } else {
313 /*
314 * flush_tlb_all(), as currently implemented, won't work if
315 * PCID is on but PGE is not. Since that combination
316 * doesn't exist on real hardware, there's no reason to try
317 * to fully support it, but it's polite to avoid corrupting
318 * data if we're on an improperly configured VM.
319 */
320 setup_clear_cpu_cap(X86_FEATURE_PCID);
321 }
322 }
323
324 #ifdef CONFIG_X86_32
325 #define NR_RANGE_MR 3
326 #else /* CONFIG_X86_64 */
327 #define NR_RANGE_MR 5
328 #endif
329
save_mr(struct map_range * mr,int nr_range,unsigned long start_pfn,unsigned long end_pfn,unsigned long page_size_mask)330 static int __meminit save_mr(struct map_range *mr, int nr_range,
331 unsigned long start_pfn, unsigned long end_pfn,
332 unsigned long page_size_mask)
333 {
334 if (start_pfn < end_pfn) {
335 if (nr_range >= NR_RANGE_MR)
336 panic("run out of range for init_memory_mapping\n");
337 mr[nr_range].start = start_pfn<<PAGE_SHIFT;
338 mr[nr_range].end = end_pfn<<PAGE_SHIFT;
339 mr[nr_range].page_size_mask = page_size_mask;
340 nr_range++;
341 }
342
343 return nr_range;
344 }
345
346 /*
347 * adjust the page_size_mask for small range to go with
348 * big page size instead small one if nearby are ram too.
349 */
adjust_range_page_size_mask(struct map_range * mr,int nr_range)350 static void __ref adjust_range_page_size_mask(struct map_range *mr,
351 int nr_range)
352 {
353 int i;
354
355 for (i = 0; i < nr_range; i++) {
356 if ((page_size_mask & (1<<PG_LEVEL_2M)) &&
357 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) {
358 unsigned long start = round_down(mr[i].start, PMD_SIZE);
359 unsigned long end = round_up(mr[i].end, PMD_SIZE);
360
361 #ifdef CONFIG_X86_32
362 if ((end >> PAGE_SHIFT) > max_low_pfn)
363 continue;
364 #endif
365
366 if (memblock_is_region_memory(start, end - start))
367 mr[i].page_size_mask |= 1<<PG_LEVEL_2M;
368 }
369 if ((page_size_mask & (1<<PG_LEVEL_1G)) &&
370 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) {
371 unsigned long start = round_down(mr[i].start, PUD_SIZE);
372 unsigned long end = round_up(mr[i].end, PUD_SIZE);
373
374 if (memblock_is_region_memory(start, end - start))
375 mr[i].page_size_mask |= 1<<PG_LEVEL_1G;
376 }
377 }
378 }
379
page_size_string(struct map_range * mr)380 static const char *page_size_string(struct map_range *mr)
381 {
382 static const char str_1g[] = "1G";
383 static const char str_2m[] = "2M";
384 static const char str_4m[] = "4M";
385 static const char str_4k[] = "4k";
386
387 if (mr->page_size_mask & (1<<PG_LEVEL_1G))
388 return str_1g;
389 /*
390 * 32-bit without PAE has a 4M large page size.
391 * PG_LEVEL_2M is misnamed, but we can at least
392 * print out the right size in the string.
393 */
394 if (IS_ENABLED(CONFIG_X86_32) &&
395 !IS_ENABLED(CONFIG_X86_PAE) &&
396 mr->page_size_mask & (1<<PG_LEVEL_2M))
397 return str_4m;
398
399 if (mr->page_size_mask & (1<<PG_LEVEL_2M))
400 return str_2m;
401
402 return str_4k;
403 }
404
split_mem_range(struct map_range * mr,int nr_range,unsigned long start,unsigned long end)405 static int __meminit split_mem_range(struct map_range *mr, int nr_range,
406 unsigned long start,
407 unsigned long end)
408 {
409 unsigned long start_pfn, end_pfn, limit_pfn;
410 unsigned long pfn;
411 int i;
412
413 limit_pfn = PFN_DOWN(end);
414
415 /* head if not big page alignment ? */
416 pfn = start_pfn = PFN_DOWN(start);
417 #ifdef CONFIG_X86_32
418 /*
419 * Don't use a large page for the first 2/4MB of memory
420 * because there are often fixed size MTRRs in there
421 * and overlapping MTRRs into large pages can cause
422 * slowdowns.
423 */
424 if (pfn == 0)
425 end_pfn = PFN_DOWN(PMD_SIZE);
426 else
427 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
428 #else /* CONFIG_X86_64 */
429 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
430 #endif
431 if (end_pfn > limit_pfn)
432 end_pfn = limit_pfn;
433 if (start_pfn < end_pfn) {
434 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
435 pfn = end_pfn;
436 }
437
438 /* big page (2M) range */
439 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
440 #ifdef CONFIG_X86_32
441 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
442 #else /* CONFIG_X86_64 */
443 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
444 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE)))
445 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
446 #endif
447
448 if (start_pfn < end_pfn) {
449 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
450 page_size_mask & (1<<PG_LEVEL_2M));
451 pfn = end_pfn;
452 }
453
454 #ifdef CONFIG_X86_64
455 /* big page (1G) range */
456 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
457 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE));
458 if (start_pfn < end_pfn) {
459 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
460 page_size_mask &
461 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G)));
462 pfn = end_pfn;
463 }
464
465 /* tail is not big page (1G) alignment */
466 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
467 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
468 if (start_pfn < end_pfn) {
469 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
470 page_size_mask & (1<<PG_LEVEL_2M));
471 pfn = end_pfn;
472 }
473 #endif
474
475 /* tail is not big page (2M) alignment */
476 start_pfn = pfn;
477 end_pfn = limit_pfn;
478 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
479
480 if (!after_bootmem)
481 adjust_range_page_size_mask(mr, nr_range);
482
483 /* try to merge same page size and continuous */
484 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
485 unsigned long old_start;
486 if (mr[i].end != mr[i+1].start ||
487 mr[i].page_size_mask != mr[i+1].page_size_mask)
488 continue;
489 /* move it */
490 old_start = mr[i].start;
491 memmove(&mr[i], &mr[i+1],
492 (nr_range - 1 - i) * sizeof(struct map_range));
493 mr[i--].start = old_start;
494 nr_range--;
495 }
496
497 for (i = 0; i < nr_range; i++)
498 pr_debug(" [mem %#010lx-%#010lx] page %s\n",
499 mr[i].start, mr[i].end - 1,
500 page_size_string(&mr[i]));
501
502 return nr_range;
503 }
504
505 struct range pfn_mapped[E820_MAX_ENTRIES];
506 int nr_pfn_mapped;
507
add_pfn_range_mapped(unsigned long start_pfn,unsigned long end_pfn)508 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn)
509 {
510 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES,
511 nr_pfn_mapped, start_pfn, end_pfn);
512 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES);
513
514 max_pfn_mapped = max(max_pfn_mapped, end_pfn);
515
516 if (start_pfn < (1UL<<(32-PAGE_SHIFT)))
517 max_low_pfn_mapped = max(max_low_pfn_mapped,
518 min(end_pfn, 1UL<<(32-PAGE_SHIFT)));
519 }
520
pfn_range_is_mapped(unsigned long start_pfn,unsigned long end_pfn)521 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn)
522 {
523 int i;
524
525 for (i = 0; i < nr_pfn_mapped; i++)
526 if ((start_pfn >= pfn_mapped[i].start) &&
527 (end_pfn <= pfn_mapped[i].end))
528 return true;
529
530 return false;
531 }
532
533 /*
534 * Setup the direct mapping of the physical memory at PAGE_OFFSET.
535 * This runs before bootmem is initialized and gets pages directly from
536 * the physical memory. To access them they are temporarily mapped.
537 */
init_memory_mapping(unsigned long start,unsigned long end,pgprot_t prot)538 unsigned long __ref init_memory_mapping(unsigned long start,
539 unsigned long end, pgprot_t prot)
540 {
541 struct map_range mr[NR_RANGE_MR];
542 unsigned long ret = 0;
543 int nr_range, i;
544
545 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n",
546 start, end - 1);
547
548 memset(mr, 0, sizeof(mr));
549 nr_range = split_mem_range(mr, 0, start, end);
550
551 for (i = 0; i < nr_range; i++)
552 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end,
553 mr[i].page_size_mask,
554 prot);
555
556 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT);
557
558 return ret >> PAGE_SHIFT;
559 }
560
561 /*
562 * We need to iterate through the E820 memory map and create direct mappings
563 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply
564 * create direct mappings for all pfns from [0 to max_low_pfn) and
565 * [4GB to max_pfn) because of possible memory holes in high addresses
566 * that cannot be marked as UC by fixed/variable range MTRRs.
567 * Depending on the alignment of E820 ranges, this may possibly result
568 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables.
569 *
570 * init_mem_mapping() calls init_range_memory_mapping() with big range.
571 * That range would have hole in the middle or ends, and only ram parts
572 * will be mapped in init_range_memory_mapping().
573 */
init_range_memory_mapping(unsigned long r_start,unsigned long r_end)574 static unsigned long __init init_range_memory_mapping(
575 unsigned long r_start,
576 unsigned long r_end)
577 {
578 unsigned long start_pfn, end_pfn;
579 unsigned long mapped_ram_size = 0;
580 int i;
581
582 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
583 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end);
584 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end);
585 if (start >= end)
586 continue;
587
588 /*
589 * if it is overlapping with brk pgt, we need to
590 * alloc pgt buf from memblock instead.
591 */
592 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >=
593 min(end, (u64)pgt_buf_top<<PAGE_SHIFT);
594 init_memory_mapping(start, end, PAGE_KERNEL);
595 mapped_ram_size += end - start;
596 can_use_brk_pgt = true;
597 }
598
599 return mapped_ram_size;
600 }
601
get_new_step_size(unsigned long step_size)602 static unsigned long __init get_new_step_size(unsigned long step_size)
603 {
604 /*
605 * Initial mapped size is PMD_SIZE (2M).
606 * We can not set step_size to be PUD_SIZE (1G) yet.
607 * In worse case, when we cross the 1G boundary, and
608 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k)
609 * to map 1G range with PTE. Hence we use one less than the
610 * difference of page table level shifts.
611 *
612 * Don't need to worry about overflow in the top-down case, on 32bit,
613 * when step_size is 0, round_down() returns 0 for start, and that
614 * turns it into 0x100000000ULL.
615 * In the bottom-up case, round_up(x, 0) returns 0 though too, which
616 * needs to be taken into consideration by the code below.
617 */
618 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1);
619 }
620
621 /**
622 * memory_map_top_down - Map [map_start, map_end) top down
623 * @map_start: start address of the target memory range
624 * @map_end: end address of the target memory range
625 *
626 * This function will setup direct mapping for memory range
627 * [map_start, map_end) in top-down. That said, the page tables
628 * will be allocated at the end of the memory, and we map the
629 * memory in top-down.
630 */
memory_map_top_down(unsigned long map_start,unsigned long map_end)631 static void __init memory_map_top_down(unsigned long map_start,
632 unsigned long map_end)
633 {
634 unsigned long real_end, start, last_start;
635 unsigned long step_size;
636 unsigned long addr;
637 unsigned long mapped_ram_size = 0;
638
639 /* xen has big range in reserved near end of ram, skip it at first.*/
640 addr = memblock_find_in_range(map_start, map_end, PMD_SIZE, PMD_SIZE);
641 real_end = addr + PMD_SIZE;
642
643 /* step_size need to be small so pgt_buf from BRK could cover it */
644 step_size = PMD_SIZE;
645 max_pfn_mapped = 0; /* will get exact value next */
646 min_pfn_mapped = real_end >> PAGE_SHIFT;
647 last_start = start = real_end;
648
649 /*
650 * We start from the top (end of memory) and go to the bottom.
651 * The memblock_find_in_range() gets us a block of RAM from the
652 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
653 * for page table.
654 */
655 while (last_start > map_start) {
656 if (last_start > step_size) {
657 start = round_down(last_start - 1, step_size);
658 if (start < map_start)
659 start = map_start;
660 } else
661 start = map_start;
662 mapped_ram_size += init_range_memory_mapping(start,
663 last_start);
664 last_start = start;
665 min_pfn_mapped = last_start >> PAGE_SHIFT;
666 if (mapped_ram_size >= step_size)
667 step_size = get_new_step_size(step_size);
668 }
669
670 if (real_end < map_end)
671 init_range_memory_mapping(real_end, map_end);
672 }
673
674 /**
675 * memory_map_bottom_up - Map [map_start, map_end) bottom up
676 * @map_start: start address of the target memory range
677 * @map_end: end address of the target memory range
678 *
679 * This function will setup direct mapping for memory range
680 * [map_start, map_end) in bottom-up. Since we have limited the
681 * bottom-up allocation above the kernel, the page tables will
682 * be allocated just above the kernel and we map the memory
683 * in [map_start, map_end) in bottom-up.
684 */
memory_map_bottom_up(unsigned long map_start,unsigned long map_end)685 static void __init memory_map_bottom_up(unsigned long map_start,
686 unsigned long map_end)
687 {
688 unsigned long next, start;
689 unsigned long mapped_ram_size = 0;
690 /* step_size need to be small so pgt_buf from BRK could cover it */
691 unsigned long step_size = PMD_SIZE;
692
693 start = map_start;
694 min_pfn_mapped = start >> PAGE_SHIFT;
695
696 /*
697 * We start from the bottom (@map_start) and go to the top (@map_end).
698 * The memblock_find_in_range() gets us a block of RAM from the
699 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
700 * for page table.
701 */
702 while (start < map_end) {
703 if (step_size && map_end - start > step_size) {
704 next = round_up(start + 1, step_size);
705 if (next > map_end)
706 next = map_end;
707 } else {
708 next = map_end;
709 }
710
711 mapped_ram_size += init_range_memory_mapping(start, next);
712 start = next;
713
714 if (mapped_ram_size >= step_size)
715 step_size = get_new_step_size(step_size);
716 }
717 }
718
719 /*
720 * The real mode trampoline, which is required for bootstrapping CPUs
721 * occupies only a small area under the low 1MB. See reserve_real_mode()
722 * for details.
723 *
724 * If KASLR is disabled the first PGD entry of the direct mapping is copied
725 * to map the real mode trampoline.
726 *
727 * If KASLR is enabled, copy only the PUD which covers the low 1MB
728 * area. This limits the randomization granularity to 1GB for both 4-level
729 * and 5-level paging.
730 */
init_trampoline(void)731 static void __init init_trampoline(void)
732 {
733 #ifdef CONFIG_X86_64
734 if (!kaslr_memory_enabled())
735 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)];
736 else
737 init_trampoline_kaslr();
738 #endif
739 }
740
init_mem_mapping(void)741 void __init init_mem_mapping(void)
742 {
743 unsigned long end;
744
745 pti_check_boottime_disable();
746 probe_page_size_mask();
747 setup_pcid();
748
749 #ifdef CONFIG_X86_64
750 end = max_pfn << PAGE_SHIFT;
751 #else
752 end = max_low_pfn << PAGE_SHIFT;
753 #endif
754
755 /* the ISA range is always mapped regardless of memory holes */
756 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL);
757
758 /* Init the trampoline, possibly with KASLR memory offset */
759 init_trampoline();
760
761 /*
762 * If the allocation is in bottom-up direction, we setup direct mapping
763 * in bottom-up, otherwise we setup direct mapping in top-down.
764 */
765 if (memblock_bottom_up()) {
766 unsigned long kernel_end = __pa_symbol(_end);
767
768 /*
769 * we need two separate calls here. This is because we want to
770 * allocate page tables above the kernel. So we first map
771 * [kernel_end, end) to make memory above the kernel be mapped
772 * as soon as possible. And then use page tables allocated above
773 * the kernel to map [ISA_END_ADDRESS, kernel_end).
774 */
775 memory_map_bottom_up(kernel_end, end);
776 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end);
777 } else {
778 memory_map_top_down(ISA_END_ADDRESS, end);
779 }
780
781 #ifdef CONFIG_X86_64
782 if (max_pfn > max_low_pfn) {
783 /* can we preseve max_low_pfn ?*/
784 max_low_pfn = max_pfn;
785 }
786 #else
787 early_ioremap_page_table_range_init();
788 #endif
789
790 load_cr3(swapper_pg_dir);
791 __flush_tlb_all();
792
793 x86_init.hyper.init_mem_mapping();
794
795 early_memtest(0, max_pfn_mapped << PAGE_SHIFT);
796 }
797
798 /*
799 * Initialize an mm_struct to be used during poking and a pointer to be used
800 * during patching.
801 */
poking_init(void)802 void __init poking_init(void)
803 {
804 spinlock_t *ptl;
805 pte_t *ptep;
806
807 poking_mm = copy_init_mm();
808 BUG_ON(!poking_mm);
809
810 /*
811 * Randomize the poking address, but make sure that the following page
812 * will be mapped at the same PMD. We need 2 pages, so find space for 3,
813 * and adjust the address if the PMD ends after the first one.
814 */
815 poking_addr = TASK_UNMAPPED_BASE;
816 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
817 poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) %
818 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE);
819
820 if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0)
821 poking_addr += PAGE_SIZE;
822
823 /*
824 * We need to trigger the allocation of the page-tables that will be
825 * needed for poking now. Later, poking may be performed in an atomic
826 * section, which might cause allocation to fail.
827 */
828 ptep = get_locked_pte(poking_mm, poking_addr, &ptl);
829 BUG_ON(!ptep);
830 pte_unmap_unlock(ptep, ptl);
831 }
832
833 /*
834 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
835 * is valid. The argument is a physical page number.
836 *
837 * On x86, access has to be given to the first megabyte of RAM because that
838 * area traditionally contains BIOS code and data regions used by X, dosemu,
839 * and similar apps. Since they map the entire memory range, the whole range
840 * must be allowed (for mapping), but any areas that would otherwise be
841 * disallowed are flagged as being "zero filled" instead of rejected.
842 * Access has to be given to non-kernel-ram areas as well, these contain the
843 * PCI mmio resources as well as potential bios/acpi data regions.
844 */
devmem_is_allowed(unsigned long pagenr)845 int devmem_is_allowed(unsigned long pagenr)
846 {
847 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE,
848 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE)
849 != REGION_DISJOINT) {
850 /*
851 * For disallowed memory regions in the low 1MB range,
852 * request that the page be shown as all zeros.
853 */
854 if (pagenr < 256)
855 return 2;
856
857 return 0;
858 }
859
860 /*
861 * This must follow RAM test, since System RAM is considered a
862 * restricted resource under CONFIG_STRICT_IOMEM.
863 */
864 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) {
865 /* Low 1MB bypasses iomem restrictions. */
866 if (pagenr < 256)
867 return 1;
868
869 return 0;
870 }
871
872 return 1;
873 }
874
free_init_pages(const char * what,unsigned long begin,unsigned long end)875 void free_init_pages(const char *what, unsigned long begin, unsigned long end)
876 {
877 unsigned long begin_aligned, end_aligned;
878
879 /* Make sure boundaries are page aligned */
880 begin_aligned = PAGE_ALIGN(begin);
881 end_aligned = end & PAGE_MASK;
882
883 if (WARN_ON(begin_aligned != begin || end_aligned != end)) {
884 begin = begin_aligned;
885 end = end_aligned;
886 }
887
888 if (begin >= end)
889 return;
890
891 /*
892 * If debugging page accesses then do not free this memory but
893 * mark them not present - any buggy init-section access will
894 * create a kernel page fault:
895 */
896 if (debug_pagealloc_enabled()) {
897 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n",
898 begin, end - 1);
899 /*
900 * Inform kmemleak about the hole in the memory since the
901 * corresponding pages will be unmapped.
902 */
903 kmemleak_free_part((void *)begin, end - begin);
904 set_memory_np(begin, (end - begin) >> PAGE_SHIFT);
905 } else {
906 /*
907 * We just marked the kernel text read only above, now that
908 * we are going to free part of that, we need to make that
909 * writeable and non-executable first.
910 */
911 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT);
912 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT);
913
914 free_reserved_area((void *)begin, (void *)end,
915 POISON_FREE_INITMEM, what);
916 }
917 }
918
919 /*
920 * begin/end can be in the direct map or the "high kernel mapping"
921 * used for the kernel image only. free_init_pages() will do the
922 * right thing for either kind of address.
923 */
free_kernel_image_pages(const char * what,void * begin,void * end)924 void free_kernel_image_pages(const char *what, void *begin, void *end)
925 {
926 unsigned long begin_ul = (unsigned long)begin;
927 unsigned long end_ul = (unsigned long)end;
928 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT;
929
930 free_init_pages(what, begin_ul, end_ul);
931
932 /*
933 * PTI maps some of the kernel into userspace. For performance,
934 * this includes some kernel areas that do not contain secrets.
935 * Those areas might be adjacent to the parts of the kernel image
936 * being freed, which may contain secrets. Remove the "high kernel
937 * image mapping" for these freed areas, ensuring they are not even
938 * potentially vulnerable to Meltdown regardless of the specific
939 * optimizations PTI is currently using.
940 *
941 * The "noalias" prevents unmapping the direct map alias which is
942 * needed to access the freed pages.
943 *
944 * This is only valid for 64bit kernels. 32bit has only one mapping
945 * which can't be treated in this way for obvious reasons.
946 */
947 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI))
948 set_memory_np_noalias(begin_ul, len_pages);
949 }
950
free_initmem(void)951 void __ref free_initmem(void)
952 {
953 e820__reallocate_tables();
954
955 mem_encrypt_free_decrypted_mem();
956
957 free_kernel_image_pages("unused kernel image (initmem)",
958 &__init_begin, &__init_end);
959 }
960
961 #ifdef CONFIG_BLK_DEV_INITRD
free_initrd_mem(unsigned long start,unsigned long end)962 void __init free_initrd_mem(unsigned long start, unsigned long end)
963 {
964 /*
965 * end could be not aligned, and We can not align that,
966 * decompresser could be confused by aligned initrd_end
967 * We already reserve the end partial page before in
968 * - i386_start_kernel()
969 * - x86_64_start_kernel()
970 * - relocate_initrd()
971 * So here We can do PAGE_ALIGN() safely to get partial page to be freed
972 */
973 free_init_pages("initrd", start, PAGE_ALIGN(end));
974 }
975 #endif
976
977 /*
978 * Calculate the precise size of the DMA zone (first 16 MB of RAM),
979 * and pass it to the MM layer - to help it set zone watermarks more
980 * accurately.
981 *
982 * Done on 64-bit systems only for the time being, although 32-bit systems
983 * might benefit from this as well.
984 */
memblock_find_dma_reserve(void)985 void __init memblock_find_dma_reserve(void)
986 {
987 #ifdef CONFIG_X86_64
988 u64 nr_pages = 0, nr_free_pages = 0;
989 unsigned long start_pfn, end_pfn;
990 phys_addr_t start_addr, end_addr;
991 int i;
992 u64 u;
993
994 /*
995 * Iterate over all memory ranges (free and reserved ones alike),
996 * to calculate the total number of pages in the first 16 MB of RAM:
997 */
998 nr_pages = 0;
999 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
1000 start_pfn = min(start_pfn, MAX_DMA_PFN);
1001 end_pfn = min(end_pfn, MAX_DMA_PFN);
1002
1003 nr_pages += end_pfn - start_pfn;
1004 }
1005
1006 /*
1007 * Iterate over free memory ranges to calculate the number of free
1008 * pages in the DMA zone, while not counting potential partial
1009 * pages at the beginning or the end of the range:
1010 */
1011 nr_free_pages = 0;
1012 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) {
1013 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN);
1014 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN);
1015
1016 if (start_pfn < end_pfn)
1017 nr_free_pages += end_pfn - start_pfn;
1018 }
1019
1020 set_dma_reserve(nr_pages - nr_free_pages);
1021 #endif
1022 }
1023
zone_sizes_init(void)1024 void __init zone_sizes_init(void)
1025 {
1026 unsigned long max_zone_pfns[MAX_NR_ZONES];
1027
1028 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1029
1030 #ifdef CONFIG_ZONE_DMA
1031 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn);
1032 #endif
1033 #ifdef CONFIG_ZONE_DMA32
1034 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn);
1035 #endif
1036 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
1037 #ifdef CONFIG_HIGHMEM
1038 max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
1039 #endif
1040
1041 free_area_init(max_zone_pfns);
1042 }
1043
1044 __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = {
1045 .loaded_mm = &init_mm,
1046 .next_asid = 1,
1047 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */
1048 };
1049
update_cache_mode_entry(unsigned entry,enum page_cache_mode cache)1050 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache)
1051 {
1052 /* entry 0 MUST be WB (hardwired to speed up translations) */
1053 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB);
1054
1055 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry);
1056 __pte2cachemode_tbl[entry] = cache;
1057 }
1058
1059 #ifdef CONFIG_SWAP
max_swapfile_size(void)1060 unsigned long max_swapfile_size(void)
1061 {
1062 unsigned long pages;
1063
1064 pages = generic_max_swapfile_size();
1065
1066 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) {
1067 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */
1068 unsigned long long l1tf_limit = l1tf_pfn_limit();
1069 /*
1070 * We encode swap offsets also with 3 bits below those for pfn
1071 * which makes the usable limit higher.
1072 */
1073 #if CONFIG_PGTABLE_LEVELS > 2
1074 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT;
1075 #endif
1076 pages = min_t(unsigned long long, l1tf_limit, pages);
1077 }
1078 return pages;
1079 }
1080 #endif
1081