Searched defs:ushl (Results 1 – 4 of 4) sorted by relevance
| /third_party/ltp/tools/sparse/sparse-src/validation/backend/ |
| D | bitwise-ops.c | 6 static unsigned int ushl(unsigned int x, unsigned int y) in ushl() function
|
| /third_party/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2419 __ ushl(d31, d0, d16); in GenerateTestSequenceNEON() local
2420 __ ushl(v0.V16B(), v6.V16B(), v2.V16B()); in GenerateTestSequenceNEON() local
2421 __ ushl(v18.V2D(), v1.V2D(), v18.V2D()); in GenerateTestSequenceNEON() local
2422 __ ushl(v27.V2S(), v7.V2S(), v29.V2S()); in GenerateTestSequenceNEON() local
2423 __ ushl(v14.V4H(), v14.V4H(), v13.V4H()); in GenerateTestSequenceNEON() local
2424 __ ushl(v22.V4S(), v4.V4S(), v9.V4S()); in GenerateTestSequenceNEON() local
2425 __ ushl(v23.V8B(), v22.V8B(), v27.V8B()); in GenerateTestSequenceNEON() local
2426 __ ushl(v21.V8H(), v25.V8H(), v8.V8H()); in GenerateTestSequenceNEON() local
|
| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-logic-arm64.cc | 1603 LogicVRegister Simulator::ushl(VectorFormat vform, LogicVRegister dst, in ushl() function in v8::internal::Simulator
|
| /third_party/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 1942 LogicVRegister Simulator::ushl(VectorFormat vform, in ushl() function in vixl::aarch64::Simulator
|