1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 1994 Linus Torvalds
4 *
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
10 */
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
18 #include <linux/pgtable.h>
19 #include <linux/bpf.h>
20
21 #include <asm/spec-ctrl.h>
22 #include <asm/cmdline.h>
23 #include <asm/bugs.h>
24 #include <asm/processor.h>
25 #include <asm/processor-flags.h>
26 #include <asm/fpu/internal.h>
27 #include <asm/msr.h>
28 #include <asm/vmx.h>
29 #include <asm/paravirt.h>
30 #include <asm/alternative.h>
31 #include <asm/set_memory.h>
32 #include <asm/intel-family.h>
33 #include <asm/e820/api.h>
34 #include <asm/hypervisor.h>
35 #include <asm/tlbflush.h>
36
37 #include "cpu.h"
38
39 static void __init spectre_v1_select_mitigation(void);
40 static void __init spectre_v2_select_mitigation(void);
41 static void __init retbleed_select_mitigation(void);
42 static void __init spectre_v2_user_select_mitigation(void);
43 static void __init ssb_select_mitigation(void);
44 static void __init l1tf_select_mitigation(void);
45 static void __init mds_select_mitigation(void);
46 static void __init md_clear_update_mitigation(void);
47 static void __init md_clear_select_mitigation(void);
48 static void __init taa_select_mitigation(void);
49 static void __init mmio_select_mitigation(void);
50 static void __init srbds_select_mitigation(void);
51
52 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
53 u64 x86_spec_ctrl_base;
54 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
55
56 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
57 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
58 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
59
60 static DEFINE_MUTEX(spec_ctrl_mutex);
61
62 /* Update SPEC_CTRL MSR and its cached copy unconditionally */
update_spec_ctrl(u64 val)63 static void update_spec_ctrl(u64 val)
64 {
65 this_cpu_write(x86_spec_ctrl_current, val);
66 wrmsrl(MSR_IA32_SPEC_CTRL, val);
67 }
68
69 /*
70 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
71 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
72 */
update_spec_ctrl_cond(u64 val)73 void update_spec_ctrl_cond(u64 val)
74 {
75 if (this_cpu_read(x86_spec_ctrl_current) == val)
76 return;
77
78 this_cpu_write(x86_spec_ctrl_current, val);
79
80 /*
81 * When KERNEL_IBRS this MSR is written on return-to-user, unless
82 * forced the update can be delayed until that time.
83 */
84 if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
85 wrmsrl(MSR_IA32_SPEC_CTRL, val);
86 }
87
spec_ctrl_current(void)88 u64 spec_ctrl_current(void)
89 {
90 return this_cpu_read(x86_spec_ctrl_current);
91 }
92 EXPORT_SYMBOL_GPL(spec_ctrl_current);
93
94 /*
95 * AMD specific MSR info for Speculative Store Bypass control.
96 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
97 */
98 u64 __ro_after_init x86_amd_ls_cfg_base;
99 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
100
101 /* Control conditional STIBP in switch_to() */
102 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
103 /* Control conditional IBPB in switch_mm() */
104 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
105 /* Control unconditional IBPB in switch_mm() */
106 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
107
108 /* Control MDS CPU buffer clear before returning to user space */
109 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
110 EXPORT_SYMBOL_GPL(mds_user_clear);
111 /* Control MDS CPU buffer clear before idling (halt, mwait) */
112 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
113 EXPORT_SYMBOL_GPL(mds_idle_clear);
114
115 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
116 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
117 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
118
check_bugs(void)119 void __init check_bugs(void)
120 {
121 identify_boot_cpu();
122
123 /*
124 * identify_boot_cpu() initialized SMT support information, let the
125 * core code know.
126 */
127 cpu_smt_check_topology();
128
129 if (!IS_ENABLED(CONFIG_SMP)) {
130 pr_info("CPU: ");
131 print_cpu_info(&boot_cpu_data);
132 }
133
134 /*
135 * Read the SPEC_CTRL MSR to account for reserved bits which may
136 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
137 * init code as it is not enumerated and depends on the family.
138 */
139 if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
140 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
141
142 /*
143 * Previously running kernel (kexec), may have some controls
144 * turned ON. Clear them and let the mitigations setup below
145 * rediscover them based on configuration.
146 */
147 x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
148 }
149
150 /* Select the proper CPU mitigations before patching alternatives: */
151 spectre_v1_select_mitigation();
152 spectre_v2_select_mitigation();
153 /*
154 * retbleed_select_mitigation() relies on the state set by
155 * spectre_v2_select_mitigation(); specifically it wants to know about
156 * spectre_v2=ibrs.
157 */
158 retbleed_select_mitigation();
159 /*
160 * spectre_v2_user_select_mitigation() relies on the state set by
161 * retbleed_select_mitigation(); specifically the STIBP selection is
162 * forced for UNRET or IBPB.
163 */
164 spectre_v2_user_select_mitigation();
165 ssb_select_mitigation();
166 l1tf_select_mitigation();
167 md_clear_select_mitigation();
168 srbds_select_mitigation();
169
170 arch_smt_update();
171
172 #ifdef CONFIG_X86_32
173 /*
174 * Check whether we are able to run this kernel safely on SMP.
175 *
176 * - i386 is no longer supported.
177 * - In order to run on anything without a TSC, we need to be
178 * compiled for a i486.
179 */
180 if (boot_cpu_data.x86 < 4)
181 panic("Kernel requires i486+ for 'invlpg' and other features");
182
183 init_utsname()->machine[1] =
184 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
185 alternative_instructions();
186
187 fpu__init_check_bugs();
188 #else /* CONFIG_X86_64 */
189 alternative_instructions();
190
191 /*
192 * Make sure the first 2MB area is not mapped by huge pages
193 * There are typically fixed size MTRRs in there and overlapping
194 * MTRRs into large pages causes slow downs.
195 *
196 * Right now we don't do that with gbpages because there seems
197 * very little benefit for that case.
198 */
199 if (!direct_gbpages)
200 set_memory_4k((unsigned long)__va(0), 1);
201 #endif
202 }
203
204 /*
205 * NOTE: For VMX, this function is not called in the vmexit path.
206 * It uses vmx_spec_ctrl_restore_host() instead.
207 */
208 void
x86_virt_spec_ctrl(u64 guest_spec_ctrl,u64 guest_virt_spec_ctrl,bool setguest)209 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
210 {
211 u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
212 struct thread_info *ti = current_thread_info();
213
214 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
215 if (hostval != guestval) {
216 msrval = setguest ? guestval : hostval;
217 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
218 }
219 }
220
221 /*
222 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
223 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
224 */
225 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
226 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
227 return;
228
229 /*
230 * If the host has SSBD mitigation enabled, force it in the host's
231 * virtual MSR value. If its not permanently enabled, evaluate
232 * current's TIF_SSBD thread flag.
233 */
234 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
235 hostval = SPEC_CTRL_SSBD;
236 else
237 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
238
239 /* Sanitize the guest value */
240 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
241
242 if (hostval != guestval) {
243 unsigned long tif;
244
245 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
246 ssbd_spec_ctrl_to_tif(hostval);
247
248 speculation_ctrl_update(tif);
249 }
250 }
251 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
252
x86_amd_ssb_disable(void)253 static void x86_amd_ssb_disable(void)
254 {
255 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
256
257 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
258 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
259 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
260 wrmsrl(MSR_AMD64_LS_CFG, msrval);
261 }
262
263 #undef pr_fmt
264 #define pr_fmt(fmt) "MDS: " fmt
265
266 /* Default mitigation for MDS-affected CPUs */
267 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
268 static bool mds_nosmt __ro_after_init = false;
269
270 static const char * const mds_strings[] = {
271 [MDS_MITIGATION_OFF] = "Vulnerable",
272 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
273 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
274 };
275
mds_select_mitigation(void)276 static void __init mds_select_mitigation(void)
277 {
278 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
279 mds_mitigation = MDS_MITIGATION_OFF;
280 return;
281 }
282
283 if (mds_mitigation == MDS_MITIGATION_FULL) {
284 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
285 mds_mitigation = MDS_MITIGATION_VMWERV;
286
287 static_branch_enable(&mds_user_clear);
288
289 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
290 (mds_nosmt || cpu_mitigations_auto_nosmt()))
291 cpu_smt_disable(false);
292 }
293 }
294
mds_cmdline(char * str)295 static int __init mds_cmdline(char *str)
296 {
297 if (!boot_cpu_has_bug(X86_BUG_MDS))
298 return 0;
299
300 if (!str)
301 return -EINVAL;
302
303 if (!strcmp(str, "off"))
304 mds_mitigation = MDS_MITIGATION_OFF;
305 else if (!strcmp(str, "full"))
306 mds_mitigation = MDS_MITIGATION_FULL;
307 else if (!strcmp(str, "full,nosmt")) {
308 mds_mitigation = MDS_MITIGATION_FULL;
309 mds_nosmt = true;
310 }
311
312 return 0;
313 }
314 early_param("mds", mds_cmdline);
315
316 #undef pr_fmt
317 #define pr_fmt(fmt) "TAA: " fmt
318
319 enum taa_mitigations {
320 TAA_MITIGATION_OFF,
321 TAA_MITIGATION_UCODE_NEEDED,
322 TAA_MITIGATION_VERW,
323 TAA_MITIGATION_TSX_DISABLED,
324 };
325
326 /* Default mitigation for TAA-affected CPUs */
327 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
328 static bool taa_nosmt __ro_after_init;
329
330 static const char * const taa_strings[] = {
331 [TAA_MITIGATION_OFF] = "Vulnerable",
332 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
333 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
334 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
335 };
336
taa_select_mitigation(void)337 static void __init taa_select_mitigation(void)
338 {
339 u64 ia32_cap;
340
341 if (!boot_cpu_has_bug(X86_BUG_TAA)) {
342 taa_mitigation = TAA_MITIGATION_OFF;
343 return;
344 }
345
346 /* TSX previously disabled by tsx=off */
347 if (!boot_cpu_has(X86_FEATURE_RTM)) {
348 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
349 return;
350 }
351
352 if (cpu_mitigations_off()) {
353 taa_mitigation = TAA_MITIGATION_OFF;
354 return;
355 }
356
357 /*
358 * TAA mitigation via VERW is turned off if both
359 * tsx_async_abort=off and mds=off are specified.
360 */
361 if (taa_mitigation == TAA_MITIGATION_OFF &&
362 mds_mitigation == MDS_MITIGATION_OFF)
363 return;
364
365 if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
366 taa_mitigation = TAA_MITIGATION_VERW;
367 else
368 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
369
370 /*
371 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
372 * A microcode update fixes this behavior to clear CPU buffers. It also
373 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
374 * ARCH_CAP_TSX_CTRL_MSR bit.
375 *
376 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
377 * update is required.
378 */
379 ia32_cap = x86_read_arch_cap_msr();
380 if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
381 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
382 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
383
384 /*
385 * TSX is enabled, select alternate mitigation for TAA which is
386 * the same as MDS. Enable MDS static branch to clear CPU buffers.
387 *
388 * For guests that can't determine whether the correct microcode is
389 * present on host, enable the mitigation for UCODE_NEEDED as well.
390 */
391 static_branch_enable(&mds_user_clear);
392
393 if (taa_nosmt || cpu_mitigations_auto_nosmt())
394 cpu_smt_disable(false);
395 }
396
tsx_async_abort_parse_cmdline(char * str)397 static int __init tsx_async_abort_parse_cmdline(char *str)
398 {
399 if (!boot_cpu_has_bug(X86_BUG_TAA))
400 return 0;
401
402 if (!str)
403 return -EINVAL;
404
405 if (!strcmp(str, "off")) {
406 taa_mitigation = TAA_MITIGATION_OFF;
407 } else if (!strcmp(str, "full")) {
408 taa_mitigation = TAA_MITIGATION_VERW;
409 } else if (!strcmp(str, "full,nosmt")) {
410 taa_mitigation = TAA_MITIGATION_VERW;
411 taa_nosmt = true;
412 }
413
414 return 0;
415 }
416 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
417
418 #undef pr_fmt
419 #define pr_fmt(fmt) "MMIO Stale Data: " fmt
420
421 enum mmio_mitigations {
422 MMIO_MITIGATION_OFF,
423 MMIO_MITIGATION_UCODE_NEEDED,
424 MMIO_MITIGATION_VERW,
425 };
426
427 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
428 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
429 static bool mmio_nosmt __ro_after_init = false;
430
431 static const char * const mmio_strings[] = {
432 [MMIO_MITIGATION_OFF] = "Vulnerable",
433 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
434 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
435 };
436
mmio_select_mitigation(void)437 static void __init mmio_select_mitigation(void)
438 {
439 u64 ia32_cap;
440
441 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
442 boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
443 cpu_mitigations_off()) {
444 mmio_mitigation = MMIO_MITIGATION_OFF;
445 return;
446 }
447
448 if (mmio_mitigation == MMIO_MITIGATION_OFF)
449 return;
450
451 ia32_cap = x86_read_arch_cap_msr();
452
453 /*
454 * Enable CPU buffer clear mitigation for host and VMM, if also affected
455 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
456 */
457 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
458 boot_cpu_has(X86_FEATURE_RTM)))
459 static_branch_enable(&mds_user_clear);
460 else
461 static_branch_enable(&mmio_stale_data_clear);
462
463 /*
464 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
465 * be propagated to uncore buffers, clearing the Fill buffers on idle
466 * is required irrespective of SMT state.
467 */
468 if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
469 static_branch_enable(&mds_idle_clear);
470
471 /*
472 * Check if the system has the right microcode.
473 *
474 * CPU Fill buffer clear mitigation is enumerated by either an explicit
475 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
476 * affected systems.
477 */
478 if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
479 (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
480 boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
481 !(ia32_cap & ARCH_CAP_MDS_NO)))
482 mmio_mitigation = MMIO_MITIGATION_VERW;
483 else
484 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
485
486 if (mmio_nosmt || cpu_mitigations_auto_nosmt())
487 cpu_smt_disable(false);
488 }
489
mmio_stale_data_parse_cmdline(char * str)490 static int __init mmio_stale_data_parse_cmdline(char *str)
491 {
492 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
493 return 0;
494
495 if (!str)
496 return -EINVAL;
497
498 if (!strcmp(str, "off")) {
499 mmio_mitigation = MMIO_MITIGATION_OFF;
500 } else if (!strcmp(str, "full")) {
501 mmio_mitigation = MMIO_MITIGATION_VERW;
502 } else if (!strcmp(str, "full,nosmt")) {
503 mmio_mitigation = MMIO_MITIGATION_VERW;
504 mmio_nosmt = true;
505 }
506
507 return 0;
508 }
509 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
510
511 #undef pr_fmt
512 #define pr_fmt(fmt) "" fmt
513
md_clear_update_mitigation(void)514 static void __init md_clear_update_mitigation(void)
515 {
516 if (cpu_mitigations_off())
517 return;
518
519 if (!static_key_enabled(&mds_user_clear))
520 goto out;
521
522 /*
523 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
524 * mitigation, if necessary.
525 */
526 if (mds_mitigation == MDS_MITIGATION_OFF &&
527 boot_cpu_has_bug(X86_BUG_MDS)) {
528 mds_mitigation = MDS_MITIGATION_FULL;
529 mds_select_mitigation();
530 }
531 if (taa_mitigation == TAA_MITIGATION_OFF &&
532 boot_cpu_has_bug(X86_BUG_TAA)) {
533 taa_mitigation = TAA_MITIGATION_VERW;
534 taa_select_mitigation();
535 }
536 if (mmio_mitigation == MMIO_MITIGATION_OFF &&
537 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
538 mmio_mitigation = MMIO_MITIGATION_VERW;
539 mmio_select_mitigation();
540 }
541 out:
542 if (boot_cpu_has_bug(X86_BUG_MDS))
543 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
544 if (boot_cpu_has_bug(X86_BUG_TAA))
545 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
546 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
547 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
548 else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
549 pr_info("MMIO Stale Data: Unknown: No mitigations\n");
550 }
551
md_clear_select_mitigation(void)552 static void __init md_clear_select_mitigation(void)
553 {
554 mds_select_mitigation();
555 taa_select_mitigation();
556 mmio_select_mitigation();
557
558 /*
559 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
560 * and print their mitigation after MDS, TAA and MMIO Stale Data
561 * mitigation selection is done.
562 */
563 md_clear_update_mitigation();
564 }
565
566 #undef pr_fmt
567 #define pr_fmt(fmt) "SRBDS: " fmt
568
569 enum srbds_mitigations {
570 SRBDS_MITIGATION_OFF,
571 SRBDS_MITIGATION_UCODE_NEEDED,
572 SRBDS_MITIGATION_FULL,
573 SRBDS_MITIGATION_TSX_OFF,
574 SRBDS_MITIGATION_HYPERVISOR,
575 };
576
577 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
578
579 static const char * const srbds_strings[] = {
580 [SRBDS_MITIGATION_OFF] = "Vulnerable",
581 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
582 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
583 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
584 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
585 };
586
587 static bool srbds_off;
588
update_srbds_msr(void)589 void update_srbds_msr(void)
590 {
591 u64 mcu_ctrl;
592
593 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
594 return;
595
596 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
597 return;
598
599 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
600 return;
601
602 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
603
604 switch (srbds_mitigation) {
605 case SRBDS_MITIGATION_OFF:
606 case SRBDS_MITIGATION_TSX_OFF:
607 mcu_ctrl |= RNGDS_MITG_DIS;
608 break;
609 case SRBDS_MITIGATION_FULL:
610 mcu_ctrl &= ~RNGDS_MITG_DIS;
611 break;
612 default:
613 break;
614 }
615
616 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
617 }
618
srbds_select_mitigation(void)619 static void __init srbds_select_mitigation(void)
620 {
621 u64 ia32_cap;
622
623 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
624 return;
625
626 /*
627 * Check to see if this is one of the MDS_NO systems supporting TSX that
628 * are only exposed to SRBDS when TSX is enabled or when CPU is affected
629 * by Processor MMIO Stale Data vulnerability.
630 */
631 ia32_cap = x86_read_arch_cap_msr();
632 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
633 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
634 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
635 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
636 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
637 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
638 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
639 else if (cpu_mitigations_off() || srbds_off)
640 srbds_mitigation = SRBDS_MITIGATION_OFF;
641
642 update_srbds_msr();
643 pr_info("%s\n", srbds_strings[srbds_mitigation]);
644 }
645
srbds_parse_cmdline(char * str)646 static int __init srbds_parse_cmdline(char *str)
647 {
648 if (!str)
649 return -EINVAL;
650
651 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
652 return 0;
653
654 srbds_off = !strcmp(str, "off");
655 return 0;
656 }
657 early_param("srbds", srbds_parse_cmdline);
658
659 #undef pr_fmt
660 #define pr_fmt(fmt) "Spectre V1 : " fmt
661
662 enum spectre_v1_mitigation {
663 SPECTRE_V1_MITIGATION_NONE,
664 SPECTRE_V1_MITIGATION_AUTO,
665 };
666
667 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
668 SPECTRE_V1_MITIGATION_AUTO;
669
670 static const char * const spectre_v1_strings[] = {
671 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
672 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
673 };
674
675 /*
676 * Does SMAP provide full mitigation against speculative kernel access to
677 * userspace?
678 */
smap_works_speculatively(void)679 static bool smap_works_speculatively(void)
680 {
681 if (!boot_cpu_has(X86_FEATURE_SMAP))
682 return false;
683
684 /*
685 * On CPUs which are vulnerable to Meltdown, SMAP does not
686 * prevent speculative access to user data in the L1 cache.
687 * Consider SMAP to be non-functional as a mitigation on these
688 * CPUs.
689 */
690 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
691 return false;
692
693 return true;
694 }
695
spectre_v1_select_mitigation(void)696 static void __init spectre_v1_select_mitigation(void)
697 {
698 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
699 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
700 return;
701 }
702
703 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
704 /*
705 * With Spectre v1, a user can speculatively control either
706 * path of a conditional swapgs with a user-controlled GS
707 * value. The mitigation is to add lfences to both code paths.
708 *
709 * If FSGSBASE is enabled, the user can put a kernel address in
710 * GS, in which case SMAP provides no protection.
711 *
712 * If FSGSBASE is disabled, the user can only put a user space
713 * address in GS. That makes an attack harder, but still
714 * possible if there's no SMAP protection.
715 */
716 if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
717 !smap_works_speculatively()) {
718 /*
719 * Mitigation can be provided from SWAPGS itself or
720 * PTI as the CR3 write in the Meltdown mitigation
721 * is serializing.
722 *
723 * If neither is there, mitigate with an LFENCE to
724 * stop speculation through swapgs.
725 */
726 if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
727 !boot_cpu_has(X86_FEATURE_PTI))
728 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
729
730 /*
731 * Enable lfences in the kernel entry (non-swapgs)
732 * paths, to prevent user entry from speculatively
733 * skipping swapgs.
734 */
735 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
736 }
737 }
738
739 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
740 }
741
nospectre_v1_cmdline(char * str)742 static int __init nospectre_v1_cmdline(char *str)
743 {
744 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
745 return 0;
746 }
747 early_param("nospectre_v1", nospectre_v1_cmdline);
748
749 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
750 SPECTRE_V2_NONE;
751
752 #undef pr_fmt
753 #define pr_fmt(fmt) "RETBleed: " fmt
754
755 enum retbleed_mitigation {
756 RETBLEED_MITIGATION_NONE,
757 RETBLEED_MITIGATION_UNRET,
758 RETBLEED_MITIGATION_IBPB,
759 RETBLEED_MITIGATION_IBRS,
760 RETBLEED_MITIGATION_EIBRS,
761 };
762
763 enum retbleed_mitigation_cmd {
764 RETBLEED_CMD_OFF,
765 RETBLEED_CMD_AUTO,
766 RETBLEED_CMD_UNRET,
767 RETBLEED_CMD_IBPB,
768 };
769
770 const char * const retbleed_strings[] = {
771 [RETBLEED_MITIGATION_NONE] = "Vulnerable",
772 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk",
773 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB",
774 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS",
775 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS",
776 };
777
778 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
779 RETBLEED_MITIGATION_NONE;
780 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
781 RETBLEED_CMD_AUTO;
782
783 static int __ro_after_init retbleed_nosmt = false;
784
retbleed_parse_cmdline(char * str)785 static int __init retbleed_parse_cmdline(char *str)
786 {
787 if (!str)
788 return -EINVAL;
789
790 while (str) {
791 char *next = strchr(str, ',');
792 if (next) {
793 *next = 0;
794 next++;
795 }
796
797 if (!strcmp(str, "off")) {
798 retbleed_cmd = RETBLEED_CMD_OFF;
799 } else if (!strcmp(str, "auto")) {
800 retbleed_cmd = RETBLEED_CMD_AUTO;
801 } else if (!strcmp(str, "unret")) {
802 retbleed_cmd = RETBLEED_CMD_UNRET;
803 } else if (!strcmp(str, "ibpb")) {
804 retbleed_cmd = RETBLEED_CMD_IBPB;
805 } else if (!strcmp(str, "nosmt")) {
806 retbleed_nosmt = true;
807 } else {
808 pr_err("Ignoring unknown retbleed option (%s).", str);
809 }
810
811 str = next;
812 }
813
814 return 0;
815 }
816 early_param("retbleed", retbleed_parse_cmdline);
817
818 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
819 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
820
retbleed_select_mitigation(void)821 static void __init retbleed_select_mitigation(void)
822 {
823 bool mitigate_smt = false;
824
825 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
826 return;
827
828 switch (retbleed_cmd) {
829 case RETBLEED_CMD_OFF:
830 return;
831
832 case RETBLEED_CMD_UNRET:
833 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) {
834 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
835 } else {
836 pr_err("WARNING: kernel not compiled with CPU_UNRET_ENTRY.\n");
837 goto do_cmd_auto;
838 }
839 break;
840
841 case RETBLEED_CMD_IBPB:
842 if (!boot_cpu_has(X86_FEATURE_IBPB)) {
843 pr_err("WARNING: CPU does not support IBPB.\n");
844 goto do_cmd_auto;
845 } else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) {
846 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
847 } else {
848 pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n");
849 goto do_cmd_auto;
850 }
851 break;
852
853 do_cmd_auto:
854 case RETBLEED_CMD_AUTO:
855 default:
856 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
857 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
858 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY))
859 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
860 else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY) && boot_cpu_has(X86_FEATURE_IBPB))
861 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
862 }
863
864 /*
865 * The Intel mitigation (IBRS or eIBRS) was already selected in
866 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will
867 * be set accordingly below.
868 */
869
870 break;
871 }
872
873 switch (retbleed_mitigation) {
874 case RETBLEED_MITIGATION_UNRET:
875 setup_force_cpu_cap(X86_FEATURE_RETHUNK);
876 setup_force_cpu_cap(X86_FEATURE_UNRET);
877
878 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
879 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
880 pr_err(RETBLEED_UNTRAIN_MSG);
881
882 mitigate_smt = true;
883 break;
884
885 case RETBLEED_MITIGATION_IBPB:
886 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
887 mitigate_smt = true;
888 break;
889
890 default:
891 break;
892 }
893
894 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
895 (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
896 cpu_smt_disable(false);
897
898 /*
899 * Let IBRS trump all on Intel without affecting the effects of the
900 * retbleed= cmdline option.
901 */
902 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
903 switch (spectre_v2_enabled) {
904 case SPECTRE_V2_IBRS:
905 retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
906 break;
907 case SPECTRE_V2_EIBRS:
908 case SPECTRE_V2_EIBRS_RETPOLINE:
909 case SPECTRE_V2_EIBRS_LFENCE:
910 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
911 break;
912 default:
913 pr_err(RETBLEED_INTEL_MSG);
914 }
915 }
916
917 pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
918 }
919
920 #undef pr_fmt
921 #define pr_fmt(fmt) "Spectre V2 : " fmt
922
923 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
924 SPECTRE_V2_USER_NONE;
925 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
926 SPECTRE_V2_USER_NONE;
927
928 #ifdef CONFIG_RETPOLINE
929 static bool spectre_v2_bad_module;
930
retpoline_module_ok(bool has_retpoline)931 bool retpoline_module_ok(bool has_retpoline)
932 {
933 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
934 return true;
935
936 pr_err("System may be vulnerable to spectre v2\n");
937 spectre_v2_bad_module = true;
938 return false;
939 }
940
spectre_v2_module_string(void)941 static inline const char *spectre_v2_module_string(void)
942 {
943 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
944 }
945 #else
spectre_v2_module_string(void)946 static inline const char *spectre_v2_module_string(void) { return ""; }
947 #endif
948
949 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
950 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
951 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
952 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
953
954 #ifdef CONFIG_BPF_SYSCALL
unpriv_ebpf_notify(int new_state)955 void unpriv_ebpf_notify(int new_state)
956 {
957 if (new_state)
958 return;
959
960 /* Unprivileged eBPF is enabled */
961
962 switch (spectre_v2_enabled) {
963 case SPECTRE_V2_EIBRS:
964 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
965 break;
966 case SPECTRE_V2_EIBRS_LFENCE:
967 if (sched_smt_active())
968 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
969 break;
970 default:
971 break;
972 }
973 }
974 #endif
975
match_option(const char * arg,int arglen,const char * opt)976 static inline bool match_option(const char *arg, int arglen, const char *opt)
977 {
978 int len = strlen(opt);
979
980 return len == arglen && !strncmp(arg, opt, len);
981 }
982
983 /* The kernel command line selection for spectre v2 */
984 enum spectre_v2_mitigation_cmd {
985 SPECTRE_V2_CMD_NONE,
986 SPECTRE_V2_CMD_AUTO,
987 SPECTRE_V2_CMD_FORCE,
988 SPECTRE_V2_CMD_RETPOLINE,
989 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
990 SPECTRE_V2_CMD_RETPOLINE_LFENCE,
991 SPECTRE_V2_CMD_EIBRS,
992 SPECTRE_V2_CMD_EIBRS_RETPOLINE,
993 SPECTRE_V2_CMD_EIBRS_LFENCE,
994 SPECTRE_V2_CMD_IBRS,
995 };
996
997 enum spectre_v2_user_cmd {
998 SPECTRE_V2_USER_CMD_NONE,
999 SPECTRE_V2_USER_CMD_AUTO,
1000 SPECTRE_V2_USER_CMD_FORCE,
1001 SPECTRE_V2_USER_CMD_PRCTL,
1002 SPECTRE_V2_USER_CMD_PRCTL_IBPB,
1003 SPECTRE_V2_USER_CMD_SECCOMP,
1004 SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
1005 };
1006
1007 static const char * const spectre_v2_user_strings[] = {
1008 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
1009 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
1010 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
1011 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
1012 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
1013 };
1014
1015 static const struct {
1016 const char *option;
1017 enum spectre_v2_user_cmd cmd;
1018 bool secure;
1019 } v2_user_options[] __initconst = {
1020 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
1021 { "off", SPECTRE_V2_USER_CMD_NONE, false },
1022 { "on", SPECTRE_V2_USER_CMD_FORCE, true },
1023 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
1024 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
1025 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
1026 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
1027 };
1028
spec_v2_user_print_cond(const char * reason,bool secure)1029 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
1030 {
1031 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1032 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
1033 }
1034
1035 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
1036
1037 static enum spectre_v2_user_cmd __init
spectre_v2_parse_user_cmdline(void)1038 spectre_v2_parse_user_cmdline(void)
1039 {
1040 char arg[20];
1041 int ret, i;
1042
1043 switch (spectre_v2_cmd) {
1044 case SPECTRE_V2_CMD_NONE:
1045 return SPECTRE_V2_USER_CMD_NONE;
1046 case SPECTRE_V2_CMD_FORCE:
1047 return SPECTRE_V2_USER_CMD_FORCE;
1048 default:
1049 break;
1050 }
1051
1052 ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
1053 arg, sizeof(arg));
1054 if (ret < 0)
1055 return SPECTRE_V2_USER_CMD_AUTO;
1056
1057 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
1058 if (match_option(arg, ret, v2_user_options[i].option)) {
1059 spec_v2_user_print_cond(v2_user_options[i].option,
1060 v2_user_options[i].secure);
1061 return v2_user_options[i].cmd;
1062 }
1063 }
1064
1065 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
1066 return SPECTRE_V2_USER_CMD_AUTO;
1067 }
1068
spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)1069 static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
1070 {
1071 return mode == SPECTRE_V2_EIBRS ||
1072 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1073 mode == SPECTRE_V2_EIBRS_LFENCE;
1074 }
1075
spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)1076 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
1077 {
1078 return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS;
1079 }
1080
1081 static void __init
spectre_v2_user_select_mitigation(void)1082 spectre_v2_user_select_mitigation(void)
1083 {
1084 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1085 bool smt_possible = IS_ENABLED(CONFIG_SMP);
1086 enum spectre_v2_user_cmd cmd;
1087
1088 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1089 return;
1090
1091 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1092 cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1093 smt_possible = false;
1094
1095 cmd = spectre_v2_parse_user_cmdline();
1096 switch (cmd) {
1097 case SPECTRE_V2_USER_CMD_NONE:
1098 goto set_mode;
1099 case SPECTRE_V2_USER_CMD_FORCE:
1100 mode = SPECTRE_V2_USER_STRICT;
1101 break;
1102 case SPECTRE_V2_USER_CMD_PRCTL:
1103 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1104 mode = SPECTRE_V2_USER_PRCTL;
1105 break;
1106 case SPECTRE_V2_USER_CMD_AUTO:
1107 case SPECTRE_V2_USER_CMD_SECCOMP:
1108 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1109 if (IS_ENABLED(CONFIG_SECCOMP))
1110 mode = SPECTRE_V2_USER_SECCOMP;
1111 else
1112 mode = SPECTRE_V2_USER_PRCTL;
1113 break;
1114 }
1115
1116 /* Initialize Indirect Branch Prediction Barrier */
1117 if (boot_cpu_has(X86_FEATURE_IBPB)) {
1118 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1119
1120 spectre_v2_user_ibpb = mode;
1121 switch (cmd) {
1122 case SPECTRE_V2_USER_CMD_FORCE:
1123 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1124 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1125 static_branch_enable(&switch_mm_always_ibpb);
1126 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1127 break;
1128 case SPECTRE_V2_USER_CMD_PRCTL:
1129 case SPECTRE_V2_USER_CMD_AUTO:
1130 case SPECTRE_V2_USER_CMD_SECCOMP:
1131 static_branch_enable(&switch_mm_cond_ibpb);
1132 break;
1133 default:
1134 break;
1135 }
1136
1137 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1138 static_key_enabled(&switch_mm_always_ibpb) ?
1139 "always-on" : "conditional");
1140 }
1141
1142 /*
1143 * If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP
1144 * is not required.
1145 *
1146 * Enhanced IBRS also protects against cross-thread branch target
1147 * injection in user-mode as the IBRS bit remains always set which
1148 * implicitly enables cross-thread protections. However, in legacy IBRS
1149 * mode, the IBRS bit is set only on kernel entry and cleared on return
1150 * to userspace. This disables the implicit cross-thread protection,
1151 * so allow for STIBP to be selected in that case.
1152 */
1153 if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1154 !smt_possible ||
1155 spectre_v2_in_eibrs_mode(spectre_v2_enabled))
1156 return;
1157
1158 /*
1159 * At this point, an STIBP mode other than "off" has been set.
1160 * If STIBP support is not being forced, check if STIBP always-on
1161 * is preferred.
1162 */
1163 if (mode != SPECTRE_V2_USER_STRICT &&
1164 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1165 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1166
1167 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
1168 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
1169 if (mode != SPECTRE_V2_USER_STRICT &&
1170 mode != SPECTRE_V2_USER_STRICT_PREFERRED)
1171 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
1172 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1173 }
1174
1175 spectre_v2_user_stibp = mode;
1176
1177 set_mode:
1178 pr_info("%s\n", spectre_v2_user_strings[mode]);
1179 }
1180
1181 static const char * const spectre_v2_strings[] = {
1182 [SPECTRE_V2_NONE] = "Vulnerable",
1183 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines",
1184 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE",
1185 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS",
1186 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE",
1187 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines",
1188 [SPECTRE_V2_IBRS] = "Mitigation: IBRS",
1189 };
1190
1191 static const struct {
1192 const char *option;
1193 enum spectre_v2_mitigation_cmd cmd;
1194 bool secure;
1195 } mitigation_options[] __initconst = {
1196 { "off", SPECTRE_V2_CMD_NONE, false },
1197 { "on", SPECTRE_V2_CMD_FORCE, true },
1198 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
1199 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1200 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1201 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1202 { "eibrs", SPECTRE_V2_CMD_EIBRS, false },
1203 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false },
1204 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false },
1205 { "auto", SPECTRE_V2_CMD_AUTO, false },
1206 { "ibrs", SPECTRE_V2_CMD_IBRS, false },
1207 };
1208
spec_v2_print_cond(const char * reason,bool secure)1209 static void __init spec_v2_print_cond(const char *reason, bool secure)
1210 {
1211 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1212 pr_info("%s selected on command line.\n", reason);
1213 }
1214
spectre_v2_parse_cmdline(void)1215 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1216 {
1217 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1218 char arg[20];
1219 int ret, i;
1220
1221 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1222 cpu_mitigations_off())
1223 return SPECTRE_V2_CMD_NONE;
1224
1225 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1226 if (ret < 0)
1227 return SPECTRE_V2_CMD_AUTO;
1228
1229 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1230 if (!match_option(arg, ret, mitigation_options[i].option))
1231 continue;
1232 cmd = mitigation_options[i].cmd;
1233 break;
1234 }
1235
1236 if (i >= ARRAY_SIZE(mitigation_options)) {
1237 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1238 return SPECTRE_V2_CMD_AUTO;
1239 }
1240
1241 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1242 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1243 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1244 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1245 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1246 !IS_ENABLED(CONFIG_RETPOLINE)) {
1247 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1248 mitigation_options[i].option);
1249 return SPECTRE_V2_CMD_AUTO;
1250 }
1251
1252 if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1253 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1254 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1255 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1256 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1257 mitigation_options[i].option);
1258 return SPECTRE_V2_CMD_AUTO;
1259 }
1260
1261 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1262 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1263 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1264 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1265 mitigation_options[i].option);
1266 return SPECTRE_V2_CMD_AUTO;
1267 }
1268
1269 if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_CPU_IBRS_ENTRY)) {
1270 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1271 mitigation_options[i].option);
1272 return SPECTRE_V2_CMD_AUTO;
1273 }
1274
1275 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1276 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1277 mitigation_options[i].option);
1278 return SPECTRE_V2_CMD_AUTO;
1279 }
1280
1281 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1282 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1283 mitigation_options[i].option);
1284 return SPECTRE_V2_CMD_AUTO;
1285 }
1286
1287 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
1288 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1289 mitigation_options[i].option);
1290 return SPECTRE_V2_CMD_AUTO;
1291 }
1292
1293 spec_v2_print_cond(mitigation_options[i].option,
1294 mitigation_options[i].secure);
1295 return cmd;
1296 }
1297
spectre_v2_select_retpoline(void)1298 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1299 {
1300 if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1301 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1302 return SPECTRE_V2_NONE;
1303 }
1304
1305 return SPECTRE_V2_RETPOLINE;
1306 }
1307
1308 /* Disable in-kernel use of non-RSB RET predictors */
spec_ctrl_disable_kernel_rrsba(void)1309 static void __init spec_ctrl_disable_kernel_rrsba(void)
1310 {
1311 u64 ia32_cap;
1312
1313 if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1314 return;
1315
1316 ia32_cap = x86_read_arch_cap_msr();
1317
1318 if (ia32_cap & ARCH_CAP_RRSBA) {
1319 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1320 update_spec_ctrl(x86_spec_ctrl_base);
1321 }
1322 }
1323
spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)1324 static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
1325 {
1326 /*
1327 * Similar to context switches, there are two types of RSB attacks
1328 * after VM exit:
1329 *
1330 * 1) RSB underflow
1331 *
1332 * 2) Poisoned RSB entry
1333 *
1334 * When retpoline is enabled, both are mitigated by filling/clearing
1335 * the RSB.
1336 *
1337 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
1338 * prediction isolation protections, RSB still needs to be cleared
1339 * because of #2. Note that SMEP provides no protection here, unlike
1340 * user-space-poisoned RSB entries.
1341 *
1342 * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB
1343 * bug is present then a LITE version of RSB protection is required,
1344 * just a single call needs to retire before a RET is executed.
1345 */
1346 switch (mode) {
1347 case SPECTRE_V2_NONE:
1348 return;
1349
1350 case SPECTRE_V2_EIBRS_LFENCE:
1351 case SPECTRE_V2_EIBRS:
1352 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
1353 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE);
1354 pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");
1355 }
1356 return;
1357
1358 case SPECTRE_V2_EIBRS_RETPOLINE:
1359 case SPECTRE_V2_RETPOLINE:
1360 case SPECTRE_V2_LFENCE:
1361 case SPECTRE_V2_IBRS:
1362 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1363 pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n");
1364 return;
1365 }
1366
1367 pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit");
1368 dump_stack();
1369 }
1370
spectre_v2_select_mitigation(void)1371 static void __init spectre_v2_select_mitigation(void)
1372 {
1373 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1374 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1375
1376 /*
1377 * If the CPU is not affected and the command line mode is NONE or AUTO
1378 * then nothing to do.
1379 */
1380 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1381 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1382 return;
1383
1384 switch (cmd) {
1385 case SPECTRE_V2_CMD_NONE:
1386 return;
1387
1388 case SPECTRE_V2_CMD_FORCE:
1389 case SPECTRE_V2_CMD_AUTO:
1390 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1391 mode = SPECTRE_V2_EIBRS;
1392 break;
1393 }
1394
1395 if (IS_ENABLED(CONFIG_CPU_IBRS_ENTRY) &&
1396 boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1397 retbleed_cmd != RETBLEED_CMD_OFF &&
1398 boot_cpu_has(X86_FEATURE_IBRS) &&
1399 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1400 mode = SPECTRE_V2_IBRS;
1401 break;
1402 }
1403
1404 mode = spectre_v2_select_retpoline();
1405 break;
1406
1407 case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1408 pr_err(SPECTRE_V2_LFENCE_MSG);
1409 mode = SPECTRE_V2_LFENCE;
1410 break;
1411
1412 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1413 mode = SPECTRE_V2_RETPOLINE;
1414 break;
1415
1416 case SPECTRE_V2_CMD_RETPOLINE:
1417 mode = spectre_v2_select_retpoline();
1418 break;
1419
1420 case SPECTRE_V2_CMD_IBRS:
1421 mode = SPECTRE_V2_IBRS;
1422 break;
1423
1424 case SPECTRE_V2_CMD_EIBRS:
1425 mode = SPECTRE_V2_EIBRS;
1426 break;
1427
1428 case SPECTRE_V2_CMD_EIBRS_LFENCE:
1429 mode = SPECTRE_V2_EIBRS_LFENCE;
1430 break;
1431
1432 case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1433 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1434 break;
1435 }
1436
1437 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1438 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1439
1440 if (spectre_v2_in_ibrs_mode(mode)) {
1441 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1442 update_spec_ctrl(x86_spec_ctrl_base);
1443 }
1444
1445 switch (mode) {
1446 case SPECTRE_V2_NONE:
1447 case SPECTRE_V2_EIBRS:
1448 break;
1449
1450 case SPECTRE_V2_IBRS:
1451 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1452 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
1453 pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
1454 break;
1455
1456 case SPECTRE_V2_LFENCE:
1457 case SPECTRE_V2_EIBRS_LFENCE:
1458 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1459 fallthrough;
1460
1461 case SPECTRE_V2_RETPOLINE:
1462 case SPECTRE_V2_EIBRS_RETPOLINE:
1463 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1464 break;
1465 }
1466
1467 /*
1468 * Disable alternate RSB predictions in kernel when indirect CALLs and
1469 * JMPs gets protection against BHI and Intramode-BTI, but RET
1470 * prediction from a non-RSB predictor is still a risk.
1471 */
1472 if (mode == SPECTRE_V2_EIBRS_LFENCE ||
1473 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1474 mode == SPECTRE_V2_RETPOLINE)
1475 spec_ctrl_disable_kernel_rrsba();
1476
1477 spectre_v2_enabled = mode;
1478 pr_info("%s\n", spectre_v2_strings[mode]);
1479
1480 /*
1481 * If Spectre v2 protection has been enabled, fill the RSB during a
1482 * context switch. In general there are two types of RSB attacks
1483 * across context switches, for which the CALLs/RETs may be unbalanced.
1484 *
1485 * 1) RSB underflow
1486 *
1487 * Some Intel parts have "bottomless RSB". When the RSB is empty,
1488 * speculated return targets may come from the branch predictor,
1489 * which could have a user-poisoned BTB or BHB entry.
1490 *
1491 * AMD has it even worse: *all* returns are speculated from the BTB,
1492 * regardless of the state of the RSB.
1493 *
1494 * When IBRS or eIBRS is enabled, the "user -> kernel" attack
1495 * scenario is mitigated by the IBRS branch prediction isolation
1496 * properties, so the RSB buffer filling wouldn't be necessary to
1497 * protect against this type of attack.
1498 *
1499 * The "user -> user" attack scenario is mitigated by RSB filling.
1500 *
1501 * 2) Poisoned RSB entry
1502 *
1503 * If the 'next' in-kernel return stack is shorter than 'prev',
1504 * 'next' could be tricked into speculating with a user-poisoned RSB
1505 * entry.
1506 *
1507 * The "user -> kernel" attack scenario is mitigated by SMEP and
1508 * eIBRS.
1509 *
1510 * The "user -> user" scenario, also known as SpectreBHB, requires
1511 * RSB clearing.
1512 *
1513 * So to mitigate all cases, unconditionally fill RSB on context
1514 * switches.
1515 *
1516 * FIXME: Is this pointless for retbleed-affected AMD?
1517 */
1518 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1519 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1520
1521 spectre_v2_determine_rsb_fill_type_at_vmexit(mode);
1522
1523 /*
1524 * Retpoline protects the kernel, but doesn't protect firmware. IBRS
1525 * and Enhanced IBRS protect firmware too, so enable IBRS around
1526 * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
1527 * enabled.
1528 *
1529 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1530 * the user might select retpoline on the kernel command line and if
1531 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1532 * enable IBRS around firmware calls.
1533 */
1534 if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1535 boot_cpu_has(X86_FEATURE_IBPB) &&
1536 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1537 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) {
1538
1539 if (retbleed_cmd != RETBLEED_CMD_IBPB) {
1540 setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW);
1541 pr_info("Enabling Speculation Barrier for firmware calls\n");
1542 }
1543
1544 } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1545 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1546 pr_info("Enabling Restricted Speculation for firmware calls\n");
1547 }
1548
1549 /* Set up IBPB and STIBP depending on the general spectre V2 command */
1550 spectre_v2_cmd = cmd;
1551 }
1552
update_stibp_msr(void * __unused)1553 static void update_stibp_msr(void * __unused)
1554 {
1555 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
1556 update_spec_ctrl(val);
1557 }
1558
1559 /* Update x86_spec_ctrl_base in case SMT state changed. */
update_stibp_strict(void)1560 static void update_stibp_strict(void)
1561 {
1562 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1563
1564 if (sched_smt_active())
1565 mask |= SPEC_CTRL_STIBP;
1566
1567 if (mask == x86_spec_ctrl_base)
1568 return;
1569
1570 pr_info("Update user space SMT mitigation: STIBP %s\n",
1571 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1572 x86_spec_ctrl_base = mask;
1573 on_each_cpu(update_stibp_msr, NULL, 1);
1574 }
1575
1576 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
update_indir_branch_cond(void)1577 static void update_indir_branch_cond(void)
1578 {
1579 if (sched_smt_active())
1580 static_branch_enable(&switch_to_cond_stibp);
1581 else
1582 static_branch_disable(&switch_to_cond_stibp);
1583 }
1584
1585 #undef pr_fmt
1586 #define pr_fmt(fmt) fmt
1587
1588 /* Update the static key controlling the MDS CPU buffer clear in idle */
update_mds_branch_idle(void)1589 static void update_mds_branch_idle(void)
1590 {
1591 u64 ia32_cap = x86_read_arch_cap_msr();
1592
1593 /*
1594 * Enable the idle clearing if SMT is active on CPUs which are
1595 * affected only by MSBDS and not any other MDS variant.
1596 *
1597 * The other variants cannot be mitigated when SMT is enabled, so
1598 * clearing the buffers on idle just to prevent the Store Buffer
1599 * repartitioning leak would be a window dressing exercise.
1600 */
1601 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1602 return;
1603
1604 if (sched_smt_active()) {
1605 static_branch_enable(&mds_idle_clear);
1606 } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1607 (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1608 static_branch_disable(&mds_idle_clear);
1609 }
1610 }
1611
1612 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1613 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1614 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1615
cpu_bugs_smt_update(void)1616 void cpu_bugs_smt_update(void)
1617 {
1618 mutex_lock(&spec_ctrl_mutex);
1619
1620 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1621 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1622 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1623
1624 switch (spectre_v2_user_stibp) {
1625 case SPECTRE_V2_USER_NONE:
1626 break;
1627 case SPECTRE_V2_USER_STRICT:
1628 case SPECTRE_V2_USER_STRICT_PREFERRED:
1629 update_stibp_strict();
1630 break;
1631 case SPECTRE_V2_USER_PRCTL:
1632 case SPECTRE_V2_USER_SECCOMP:
1633 update_indir_branch_cond();
1634 break;
1635 }
1636
1637 switch (mds_mitigation) {
1638 case MDS_MITIGATION_FULL:
1639 case MDS_MITIGATION_VMWERV:
1640 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1641 pr_warn_once(MDS_MSG_SMT);
1642 update_mds_branch_idle();
1643 break;
1644 case MDS_MITIGATION_OFF:
1645 break;
1646 }
1647
1648 switch (taa_mitigation) {
1649 case TAA_MITIGATION_VERW:
1650 case TAA_MITIGATION_UCODE_NEEDED:
1651 if (sched_smt_active())
1652 pr_warn_once(TAA_MSG_SMT);
1653 break;
1654 case TAA_MITIGATION_TSX_DISABLED:
1655 case TAA_MITIGATION_OFF:
1656 break;
1657 }
1658
1659 switch (mmio_mitigation) {
1660 case MMIO_MITIGATION_VERW:
1661 case MMIO_MITIGATION_UCODE_NEEDED:
1662 if (sched_smt_active())
1663 pr_warn_once(MMIO_MSG_SMT);
1664 break;
1665 case MMIO_MITIGATION_OFF:
1666 break;
1667 }
1668
1669 mutex_unlock(&spec_ctrl_mutex);
1670 }
1671
1672 #undef pr_fmt
1673 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1674
1675 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1676
1677 /* The kernel command line selection */
1678 enum ssb_mitigation_cmd {
1679 SPEC_STORE_BYPASS_CMD_NONE,
1680 SPEC_STORE_BYPASS_CMD_AUTO,
1681 SPEC_STORE_BYPASS_CMD_ON,
1682 SPEC_STORE_BYPASS_CMD_PRCTL,
1683 SPEC_STORE_BYPASS_CMD_SECCOMP,
1684 };
1685
1686 static const char * const ssb_strings[] = {
1687 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1688 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1689 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
1690 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1691 };
1692
1693 static const struct {
1694 const char *option;
1695 enum ssb_mitigation_cmd cmd;
1696 } ssb_mitigation_options[] __initconst = {
1697 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
1698 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
1699 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
1700 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
1701 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1702 };
1703
ssb_parse_cmdline(void)1704 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1705 {
1706 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1707 char arg[20];
1708 int ret, i;
1709
1710 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1711 cpu_mitigations_off()) {
1712 return SPEC_STORE_BYPASS_CMD_NONE;
1713 } else {
1714 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1715 arg, sizeof(arg));
1716 if (ret < 0)
1717 return SPEC_STORE_BYPASS_CMD_AUTO;
1718
1719 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1720 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1721 continue;
1722
1723 cmd = ssb_mitigation_options[i].cmd;
1724 break;
1725 }
1726
1727 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1728 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1729 return SPEC_STORE_BYPASS_CMD_AUTO;
1730 }
1731 }
1732
1733 return cmd;
1734 }
1735
__ssb_select_mitigation(void)1736 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1737 {
1738 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1739 enum ssb_mitigation_cmd cmd;
1740
1741 if (!boot_cpu_has(X86_FEATURE_SSBD))
1742 return mode;
1743
1744 cmd = ssb_parse_cmdline();
1745 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1746 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1747 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1748 return mode;
1749
1750 switch (cmd) {
1751 case SPEC_STORE_BYPASS_CMD_AUTO:
1752 case SPEC_STORE_BYPASS_CMD_SECCOMP:
1753 /*
1754 * Choose prctl+seccomp as the default mode if seccomp is
1755 * enabled.
1756 */
1757 if (IS_ENABLED(CONFIG_SECCOMP))
1758 mode = SPEC_STORE_BYPASS_SECCOMP;
1759 else
1760 mode = SPEC_STORE_BYPASS_PRCTL;
1761 break;
1762 case SPEC_STORE_BYPASS_CMD_ON:
1763 mode = SPEC_STORE_BYPASS_DISABLE;
1764 break;
1765 case SPEC_STORE_BYPASS_CMD_PRCTL:
1766 mode = SPEC_STORE_BYPASS_PRCTL;
1767 break;
1768 case SPEC_STORE_BYPASS_CMD_NONE:
1769 break;
1770 }
1771
1772 /*
1773 * We have three CPU feature flags that are in play here:
1774 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1775 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1776 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1777 */
1778 if (mode == SPEC_STORE_BYPASS_DISABLE) {
1779 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1780 /*
1781 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1782 * use a completely different MSR and bit dependent on family.
1783 */
1784 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1785 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1786 x86_amd_ssb_disable();
1787 } else {
1788 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1789 update_spec_ctrl(x86_spec_ctrl_base);
1790 }
1791 }
1792
1793 return mode;
1794 }
1795
ssb_select_mitigation(void)1796 static void ssb_select_mitigation(void)
1797 {
1798 ssb_mode = __ssb_select_mitigation();
1799
1800 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1801 pr_info("%s\n", ssb_strings[ssb_mode]);
1802 }
1803
1804 #undef pr_fmt
1805 #define pr_fmt(fmt) "Speculation prctl: " fmt
1806
task_update_spec_tif(struct task_struct * tsk)1807 static void task_update_spec_tif(struct task_struct *tsk)
1808 {
1809 /* Force the update of the real TIF bits */
1810 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1811
1812 /*
1813 * Immediately update the speculation control MSRs for the current
1814 * task, but for a non-current task delay setting the CPU
1815 * mitigation until it is scheduled next.
1816 *
1817 * This can only happen for SECCOMP mitigation. For PRCTL it's
1818 * always the current task.
1819 */
1820 if (tsk == current)
1821 speculation_ctrl_update_current();
1822 }
1823
ssb_prctl_set(struct task_struct * task,unsigned long ctrl)1824 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1825 {
1826 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1827 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1828 return -ENXIO;
1829
1830 switch (ctrl) {
1831 case PR_SPEC_ENABLE:
1832 /* If speculation is force disabled, enable is not allowed */
1833 if (task_spec_ssb_force_disable(task))
1834 return -EPERM;
1835 task_clear_spec_ssb_disable(task);
1836 task_clear_spec_ssb_noexec(task);
1837 task_update_spec_tif(task);
1838 break;
1839 case PR_SPEC_DISABLE:
1840 task_set_spec_ssb_disable(task);
1841 task_clear_spec_ssb_noexec(task);
1842 task_update_spec_tif(task);
1843 break;
1844 case PR_SPEC_FORCE_DISABLE:
1845 task_set_spec_ssb_disable(task);
1846 task_set_spec_ssb_force_disable(task);
1847 task_clear_spec_ssb_noexec(task);
1848 task_update_spec_tif(task);
1849 break;
1850 case PR_SPEC_DISABLE_NOEXEC:
1851 if (task_spec_ssb_force_disable(task))
1852 return -EPERM;
1853 task_set_spec_ssb_disable(task);
1854 task_set_spec_ssb_noexec(task);
1855 task_update_spec_tif(task);
1856 break;
1857 default:
1858 return -ERANGE;
1859 }
1860 return 0;
1861 }
1862
is_spec_ib_user_controlled(void)1863 static bool is_spec_ib_user_controlled(void)
1864 {
1865 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1866 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1867 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1868 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1869 }
1870
ib_prctl_set(struct task_struct * task,unsigned long ctrl)1871 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1872 {
1873 switch (ctrl) {
1874 case PR_SPEC_ENABLE:
1875 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1876 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1877 return 0;
1878
1879 /*
1880 * With strict mode for both IBPB and STIBP, the instruction
1881 * code paths avoid checking this task flag and instead,
1882 * unconditionally run the instruction. However, STIBP and IBPB
1883 * are independent and either can be set to conditionally
1884 * enabled regardless of the mode of the other.
1885 *
1886 * If either is set to conditional, allow the task flag to be
1887 * updated, unless it was force-disabled by a previous prctl
1888 * call. Currently, this is possible on an AMD CPU which has the
1889 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1890 * kernel is booted with 'spectre_v2_user=seccomp', then
1891 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1892 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1893 */
1894 if (!is_spec_ib_user_controlled() ||
1895 task_spec_ib_force_disable(task))
1896 return -EPERM;
1897
1898 task_clear_spec_ib_disable(task);
1899 task_update_spec_tif(task);
1900 break;
1901 case PR_SPEC_DISABLE:
1902 case PR_SPEC_FORCE_DISABLE:
1903 /*
1904 * Indirect branch speculation is always allowed when
1905 * mitigation is force disabled.
1906 */
1907 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1908 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1909 return -EPERM;
1910
1911 if (!is_spec_ib_user_controlled())
1912 return 0;
1913
1914 task_set_spec_ib_disable(task);
1915 if (ctrl == PR_SPEC_FORCE_DISABLE)
1916 task_set_spec_ib_force_disable(task);
1917 task_update_spec_tif(task);
1918 if (task == current)
1919 indirect_branch_prediction_barrier();
1920 break;
1921 default:
1922 return -ERANGE;
1923 }
1924 return 0;
1925 }
1926
arch_prctl_spec_ctrl_set(struct task_struct * task,unsigned long which,unsigned long ctrl)1927 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1928 unsigned long ctrl)
1929 {
1930 switch (which) {
1931 case PR_SPEC_STORE_BYPASS:
1932 return ssb_prctl_set(task, ctrl);
1933 case PR_SPEC_INDIRECT_BRANCH:
1934 return ib_prctl_set(task, ctrl);
1935 default:
1936 return -ENODEV;
1937 }
1938 }
1939
1940 #ifdef CONFIG_SECCOMP
arch_seccomp_spec_mitigate(struct task_struct * task)1941 void arch_seccomp_spec_mitigate(struct task_struct *task)
1942 {
1943 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1944 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1945 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1946 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1947 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1948 }
1949 #endif
1950
ssb_prctl_get(struct task_struct * task)1951 static int ssb_prctl_get(struct task_struct *task)
1952 {
1953 switch (ssb_mode) {
1954 case SPEC_STORE_BYPASS_DISABLE:
1955 return PR_SPEC_DISABLE;
1956 case SPEC_STORE_BYPASS_SECCOMP:
1957 case SPEC_STORE_BYPASS_PRCTL:
1958 if (task_spec_ssb_force_disable(task))
1959 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1960 if (task_spec_ssb_noexec(task))
1961 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
1962 if (task_spec_ssb_disable(task))
1963 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1964 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1965 default:
1966 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1967 return PR_SPEC_ENABLE;
1968 return PR_SPEC_NOT_AFFECTED;
1969 }
1970 }
1971
ib_prctl_get(struct task_struct * task)1972 static int ib_prctl_get(struct task_struct *task)
1973 {
1974 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1975 return PR_SPEC_NOT_AFFECTED;
1976
1977 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1978 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1979 return PR_SPEC_ENABLE;
1980 else if (is_spec_ib_user_controlled()) {
1981 if (task_spec_ib_force_disable(task))
1982 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1983 if (task_spec_ib_disable(task))
1984 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1985 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1986 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1987 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1988 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1989 return PR_SPEC_DISABLE;
1990 else
1991 return PR_SPEC_NOT_AFFECTED;
1992 }
1993
arch_prctl_spec_ctrl_get(struct task_struct * task,unsigned long which)1994 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1995 {
1996 switch (which) {
1997 case PR_SPEC_STORE_BYPASS:
1998 return ssb_prctl_get(task);
1999 case PR_SPEC_INDIRECT_BRANCH:
2000 return ib_prctl_get(task);
2001 default:
2002 return -ENODEV;
2003 }
2004 }
2005
x86_spec_ctrl_setup_ap(void)2006 void x86_spec_ctrl_setup_ap(void)
2007 {
2008 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
2009 update_spec_ctrl(x86_spec_ctrl_base);
2010
2011 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
2012 x86_amd_ssb_disable();
2013 }
2014
2015 bool itlb_multihit_kvm_mitigation;
2016 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
2017
2018 #undef pr_fmt
2019 #define pr_fmt(fmt) "L1TF: " fmt
2020
2021 /* Default mitigation for L1TF-affected CPUs */
2022 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
2023 #if IS_ENABLED(CONFIG_KVM_INTEL)
2024 EXPORT_SYMBOL_GPL(l1tf_mitigation);
2025 #endif
2026 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
2027 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
2028
2029 /*
2030 * These CPUs all support 44bits physical address space internally in the
2031 * cache but CPUID can report a smaller number of physical address bits.
2032 *
2033 * The L1TF mitigation uses the top most address bit for the inversion of
2034 * non present PTEs. When the installed memory reaches into the top most
2035 * address bit due to memory holes, which has been observed on machines
2036 * which report 36bits physical address bits and have 32G RAM installed,
2037 * then the mitigation range check in l1tf_select_mitigation() triggers.
2038 * This is a false positive because the mitigation is still possible due to
2039 * the fact that the cache uses 44bit internally. Use the cache bits
2040 * instead of the reported physical bits and adjust them on the affected
2041 * machines to 44bit if the reported bits are less than 44.
2042 */
override_cache_bits(struct cpuinfo_x86 * c)2043 static void override_cache_bits(struct cpuinfo_x86 *c)
2044 {
2045 if (c->x86 != 6)
2046 return;
2047
2048 switch (c->x86_model) {
2049 case INTEL_FAM6_NEHALEM:
2050 case INTEL_FAM6_WESTMERE:
2051 case INTEL_FAM6_SANDYBRIDGE:
2052 case INTEL_FAM6_IVYBRIDGE:
2053 case INTEL_FAM6_HASWELL:
2054 case INTEL_FAM6_HASWELL_L:
2055 case INTEL_FAM6_HASWELL_G:
2056 case INTEL_FAM6_BROADWELL:
2057 case INTEL_FAM6_BROADWELL_G:
2058 case INTEL_FAM6_SKYLAKE_L:
2059 case INTEL_FAM6_SKYLAKE:
2060 case INTEL_FAM6_KABYLAKE_L:
2061 case INTEL_FAM6_KABYLAKE:
2062 if (c->x86_cache_bits < 44)
2063 c->x86_cache_bits = 44;
2064 break;
2065 }
2066 }
2067
l1tf_select_mitigation(void)2068 static void __init l1tf_select_mitigation(void)
2069 {
2070 u64 half_pa;
2071
2072 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2073 return;
2074
2075 if (cpu_mitigations_off())
2076 l1tf_mitigation = L1TF_MITIGATION_OFF;
2077 else if (cpu_mitigations_auto_nosmt())
2078 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2079
2080 override_cache_bits(&boot_cpu_data);
2081
2082 switch (l1tf_mitigation) {
2083 case L1TF_MITIGATION_OFF:
2084 case L1TF_MITIGATION_FLUSH_NOWARN:
2085 case L1TF_MITIGATION_FLUSH:
2086 break;
2087 case L1TF_MITIGATION_FLUSH_NOSMT:
2088 case L1TF_MITIGATION_FULL:
2089 cpu_smt_disable(false);
2090 break;
2091 case L1TF_MITIGATION_FULL_FORCE:
2092 cpu_smt_disable(true);
2093 break;
2094 }
2095
2096 #if CONFIG_PGTABLE_LEVELS == 2
2097 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
2098 return;
2099 #endif
2100
2101 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
2102 if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
2103 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
2104 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
2105 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
2106 half_pa);
2107 pr_info("However, doing so will make a part of your RAM unusable.\n");
2108 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
2109 return;
2110 }
2111
2112 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
2113 }
2114
l1tf_cmdline(char * str)2115 static int __init l1tf_cmdline(char *str)
2116 {
2117 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2118 return 0;
2119
2120 if (!str)
2121 return -EINVAL;
2122
2123 if (!strcmp(str, "off"))
2124 l1tf_mitigation = L1TF_MITIGATION_OFF;
2125 else if (!strcmp(str, "flush,nowarn"))
2126 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2127 else if (!strcmp(str, "flush"))
2128 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2129 else if (!strcmp(str, "flush,nosmt"))
2130 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2131 else if (!strcmp(str, "full"))
2132 l1tf_mitigation = L1TF_MITIGATION_FULL;
2133 else if (!strcmp(str, "full,force"))
2134 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2135
2136 return 0;
2137 }
2138 early_param("l1tf", l1tf_cmdline);
2139
2140 #undef pr_fmt
2141 #define pr_fmt(fmt) fmt
2142
2143 #ifdef CONFIG_SYSFS
2144
2145 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2146
2147 #if IS_ENABLED(CONFIG_KVM_INTEL)
2148 static const char * const l1tf_vmx_states[] = {
2149 [VMENTER_L1D_FLUSH_AUTO] = "auto",
2150 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
2151 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
2152 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
2153 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
2154 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
2155 };
2156
l1tf_show_state(char * buf)2157 static ssize_t l1tf_show_state(char *buf)
2158 {
2159 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2160 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2161
2162 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2163 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2164 sched_smt_active())) {
2165 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2166 l1tf_vmx_states[l1tf_vmx_mitigation]);
2167 }
2168
2169 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2170 l1tf_vmx_states[l1tf_vmx_mitigation],
2171 sched_smt_active() ? "vulnerable" : "disabled");
2172 }
2173
itlb_multihit_show_state(char * buf)2174 static ssize_t itlb_multihit_show_state(char *buf)
2175 {
2176 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2177 !boot_cpu_has(X86_FEATURE_VMX))
2178 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n");
2179 else if (!(cr4_read_shadow() & X86_CR4_VMXE))
2180 return sprintf(buf, "KVM: Mitigation: VMX disabled\n");
2181 else if (itlb_multihit_kvm_mitigation)
2182 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
2183 else
2184 return sprintf(buf, "KVM: Vulnerable\n");
2185 }
2186 #else
l1tf_show_state(char * buf)2187 static ssize_t l1tf_show_state(char *buf)
2188 {
2189 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2190 }
2191
itlb_multihit_show_state(char * buf)2192 static ssize_t itlb_multihit_show_state(char *buf)
2193 {
2194 return sprintf(buf, "Processor vulnerable\n");
2195 }
2196 #endif
2197
mds_show_state(char * buf)2198 static ssize_t mds_show_state(char *buf)
2199 {
2200 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2201 return sprintf(buf, "%s; SMT Host state unknown\n",
2202 mds_strings[mds_mitigation]);
2203 }
2204
2205 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2206 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2207 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2208 sched_smt_active() ? "mitigated" : "disabled"));
2209 }
2210
2211 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2212 sched_smt_active() ? "vulnerable" : "disabled");
2213 }
2214
tsx_async_abort_show_state(char * buf)2215 static ssize_t tsx_async_abort_show_state(char *buf)
2216 {
2217 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2218 (taa_mitigation == TAA_MITIGATION_OFF))
2219 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
2220
2221 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2222 return sprintf(buf, "%s; SMT Host state unknown\n",
2223 taa_strings[taa_mitigation]);
2224 }
2225
2226 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2227 sched_smt_active() ? "vulnerable" : "disabled");
2228 }
2229
mmio_stale_data_show_state(char * buf)2230 static ssize_t mmio_stale_data_show_state(char *buf)
2231 {
2232 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2233 return sysfs_emit(buf, "Unknown: No mitigations\n");
2234
2235 if (mmio_mitigation == MMIO_MITIGATION_OFF)
2236 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2237
2238 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2239 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2240 mmio_strings[mmio_mitigation]);
2241 }
2242
2243 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2244 sched_smt_active() ? "vulnerable" : "disabled");
2245 }
2246
stibp_state(void)2247 static char *stibp_state(void)
2248 {
2249 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
2250 return "";
2251
2252 switch (spectre_v2_user_stibp) {
2253 case SPECTRE_V2_USER_NONE:
2254 return ", STIBP: disabled";
2255 case SPECTRE_V2_USER_STRICT:
2256 return ", STIBP: forced";
2257 case SPECTRE_V2_USER_STRICT_PREFERRED:
2258 return ", STIBP: always-on";
2259 case SPECTRE_V2_USER_PRCTL:
2260 case SPECTRE_V2_USER_SECCOMP:
2261 if (static_key_enabled(&switch_to_cond_stibp))
2262 return ", STIBP: conditional";
2263 }
2264 return "";
2265 }
2266
ibpb_state(void)2267 static char *ibpb_state(void)
2268 {
2269 if (boot_cpu_has(X86_FEATURE_IBPB)) {
2270 if (static_key_enabled(&switch_mm_always_ibpb))
2271 return ", IBPB: always-on";
2272 if (static_key_enabled(&switch_mm_cond_ibpb))
2273 return ", IBPB: conditional";
2274 return ", IBPB: disabled";
2275 }
2276 return "";
2277 }
2278
pbrsb_eibrs_state(void)2279 static char *pbrsb_eibrs_state(void)
2280 {
2281 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
2282 if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) ||
2283 boot_cpu_has(X86_FEATURE_RSB_VMEXIT))
2284 return ", PBRSB-eIBRS: SW sequence";
2285 else
2286 return ", PBRSB-eIBRS: Vulnerable";
2287 } else {
2288 return ", PBRSB-eIBRS: Not affected";
2289 }
2290 }
2291
spectre_v2_show_state(char * buf)2292 static ssize_t spectre_v2_show_state(char *buf)
2293 {
2294 if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2295 return sprintf(buf, "Vulnerable: LFENCE\n");
2296
2297 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2298 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2299
2300 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2301 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2302 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2303
2304 return sprintf(buf, "%s%s%s%s%s%s%s\n",
2305 spectre_v2_strings[spectre_v2_enabled],
2306 ibpb_state(),
2307 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2308 stibp_state(),
2309 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2310 pbrsb_eibrs_state(),
2311 spectre_v2_module_string());
2312 }
2313
srbds_show_state(char * buf)2314 static ssize_t srbds_show_state(char *buf)
2315 {
2316 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
2317 }
2318
retbleed_show_state(char * buf)2319 static ssize_t retbleed_show_state(char *buf)
2320 {
2321 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
2322 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
2323 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
2324 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
2325 return sprintf(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n");
2326
2327 return sprintf(buf, "%s; SMT %s\n",
2328 retbleed_strings[retbleed_mitigation],
2329 !sched_smt_active() ? "disabled" :
2330 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2331 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
2332 "enabled with STIBP protection" : "vulnerable");
2333 }
2334
2335 return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2336 }
2337
cpu_show_common(struct device * dev,struct device_attribute * attr,char * buf,unsigned int bug)2338 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2339 char *buf, unsigned int bug)
2340 {
2341 if (!boot_cpu_has_bug(bug))
2342 return sprintf(buf, "Not affected\n");
2343
2344 switch (bug) {
2345 case X86_BUG_CPU_MELTDOWN:
2346 if (boot_cpu_has(X86_FEATURE_PTI))
2347 return sprintf(buf, "Mitigation: PTI\n");
2348
2349 if (hypervisor_is_type(X86_HYPER_XEN_PV))
2350 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
2351
2352 break;
2353
2354 case X86_BUG_SPECTRE_V1:
2355 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2356
2357 case X86_BUG_SPECTRE_V2:
2358 return spectre_v2_show_state(buf);
2359
2360 case X86_BUG_SPEC_STORE_BYPASS:
2361 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
2362
2363 case X86_BUG_L1TF:
2364 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2365 return l1tf_show_state(buf);
2366 break;
2367
2368 case X86_BUG_MDS:
2369 return mds_show_state(buf);
2370
2371 case X86_BUG_TAA:
2372 return tsx_async_abort_show_state(buf);
2373
2374 case X86_BUG_ITLB_MULTIHIT:
2375 return itlb_multihit_show_state(buf);
2376
2377 case X86_BUG_SRBDS:
2378 return srbds_show_state(buf);
2379
2380 case X86_BUG_MMIO_STALE_DATA:
2381 case X86_BUG_MMIO_UNKNOWN:
2382 return mmio_stale_data_show_state(buf);
2383
2384 case X86_BUG_RETBLEED:
2385 return retbleed_show_state(buf);
2386
2387 default:
2388 break;
2389 }
2390
2391 return sprintf(buf, "Vulnerable\n");
2392 }
2393
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)2394 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2395 {
2396 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2397 }
2398
cpu_show_spectre_v1(struct device * dev,struct device_attribute * attr,char * buf)2399 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2400 {
2401 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2402 }
2403
cpu_show_spectre_v2(struct device * dev,struct device_attribute * attr,char * buf)2404 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2405 {
2406 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2407 }
2408
cpu_show_spec_store_bypass(struct device * dev,struct device_attribute * attr,char * buf)2409 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2410 {
2411 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2412 }
2413
cpu_show_l1tf(struct device * dev,struct device_attribute * attr,char * buf)2414 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2415 {
2416 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2417 }
2418
cpu_show_mds(struct device * dev,struct device_attribute * attr,char * buf)2419 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2420 {
2421 return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2422 }
2423
cpu_show_tsx_async_abort(struct device * dev,struct device_attribute * attr,char * buf)2424 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2425 {
2426 return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2427 }
2428
cpu_show_itlb_multihit(struct device * dev,struct device_attribute * attr,char * buf)2429 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2430 {
2431 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2432 }
2433
cpu_show_srbds(struct device * dev,struct device_attribute * attr,char * buf)2434 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2435 {
2436 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2437 }
2438
cpu_show_mmio_stale_data(struct device * dev,struct device_attribute * attr,char * buf)2439 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2440 {
2441 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2442 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
2443 else
2444 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2445 }
2446
cpu_show_retbleed(struct device * dev,struct device_attribute * attr,char * buf)2447 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2448 {
2449 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);
2450 }
2451 #endif
2452