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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - enum:
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Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
37 clock-frequency:
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmt8127.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "mediatek,mt81xx-tz-smp";
22 cpu@0 {
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Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a7";
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Dmt8135.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8135-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/mt8135-resets.h>
12 #include "mt8135-pinfunc.h"
15 #address-cells = <2>;
16 #size-cells = <2>;
18 interrupt-parent = <&sysirq>;
20 cpu-map {
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Dmt7623.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
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Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
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/kernel/linux/linux-5.10/drivers/net/wireless/ti/wlcore/
Dwlcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
211 u8 *fw; member
257 /* Time-offset between host and chipset clocks */
260 /* Frames scheduled for transmission, not handled yet */
265 /* Frames received, not handled yet by mac80211 */
268 /* Frames sent, not returned yet to mac80211 */
279 /* FW Rx counter */
292 /* FW log buffer */
295 /* Number of valid bytes in the FW log buffer */
298 /* FW log end marker */
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/kernel/linux/linux-5.10/drivers/net/dsa/
Dlantiq_gswip.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
9 * The VLAN and bridge model the GSWIP hardware uses does not directly
16 * The hardware does not support VLAN filter on the port, but on the
19 * The CPU gets all the exception frames which do not match any forwarding
20 * rule and the CPU port is also added to all bridges. This makes it possible
46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
50 /* GSWIP MDIO Registers */
64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p))
94 /* GSWIP MII Registers */
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/kernel/linux/linux-5.10/Documentation/powerpc/
Dpci_iov_resource_on_powernv.rst35 that's not critical.
57 - For DMA we then provide an entire address space for each PE that can
59 Each window can be configured to be remapped via a "TCE table" (IOMMU
61 not described here.
63 - For MSIs, we have two windows in the address space (one at the top of
64 the 32-bit space and one much higher) which, via a combination of the
70 - Error messages just use the RTT.
75 from the CPU address space to the PCI address space. There is one M32
78 the CPU address space to the PCIe bus and must be naturally aligned
81 - The M32 window:
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/kernel/linux/linux-5.10/arch/powerpc/oprofile/
Dop_model_cell.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <asm/cell-pmu.h>
32 #include <asm/cell-regs.h>
66 * 2^32 - 1 - N.
68 #define NUM_INTERVAL_CYC 0xFFFFFFFF - 10
73 * at the beginning of cell_reg_setup; otherwise, it's read-only.
87 * ibm,cbe-perftools rtas parameters
90 u16 cpu; /* Processor to modify */ member
148 * will know that OProfile did not start and dmesg will tell them why.
149 * OProfile does not support returning errors on Stop. Not a huge issue
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/kernel/linux/linux-5.10/arch/arm/kernel/
Dvdso.c1 // SPDX-License-Identifier: GPL-2.0-only
53 unsigned long new_size = new_vma->vm_end - new_vma->vm_start; in vdso_mremap()
57 vdso_size = (vdso_total_pages - 1) << PAGE_SHIFT; in vdso_mremap()
60 return -EINVAL; in vdso_mremap()
62 current->mm->context.vdso = new_vma->vm_start; in vdso_mremap()
79 /* Cached result of boot-time check for whether the arch timer exists,
96 np = of_find_compatible_node(NULL, NULL, "arm,armv7-timer"); in cntvct_functional()
98 np = of_find_compatible_node(NULL, NULL, "arm,armv8-timer"); in cntvct_functional()
102 if (of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) in cntvct_functional()
121 sechdrs = (void *)ehdr + ehdr->e_shoff; in find_section()
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/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/pcie/
Dtrans.c8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
9 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
10 * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
31 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
32 * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
73 #include "iwl-drv.h"
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/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/
Diwl-trans.h8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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/kernel/linux/linux-5.10/drivers/scsi/lpfc/
Dlpfc_init.c4 * Copyright (C) 2017-2020 Broadcom. All Rights Reserved. The term *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
26 #include <linux/dma-mapping.h>
43 #include <linux/cpu.h>
103 * lpfc_config_port_prep - Perform lpfc initialization prior to config port
112 * 0 - success.
113 * -ERESTART - requests the SLI layer to reset the HBA and try again.
114 * Any other value - indicates an error.
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Dlpfc_sli4.h4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
6 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
45 /* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */
62 * when nonFIP mode is configured and there is no other default
84 ((fc_hdr)->fh_s_id[0] << 16 | \
85 (fc_hdr)->fh_s_id[1] << 8 | \
86 (fc_hdr)->fh_s_id[2])
89 ((fc_hdr)->fh_d_id[0] << 16 | \
90 (fc_hdr)->fh_d_id[1] << 8 | \
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/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb4vf/
Dt4vf_hw.c2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
65 return -EIO; in t4vf_wait_dev_ready()
69 * Get the reply to a mailbox command and store it in @rpl in big-endian order
70 * (since the firmware data structures are specified in a big-endian layout).
75 for ( ; size; size -= 8, mbox_data += 8) in get_mbox_rpl()
80 * t4vf_record_mbox - record a Firmware Mailbox Command/Reply in the log
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/kernel/linux/linux-5.10/drivers/clocksource/
Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/cpu.h>
99 writel_relaxed(val, timer->base + CNTP_CTL); in arch_timer_reg_write()
102 writel_relaxed(val, timer->base + CNTP_TVAL); in arch_timer_reg_write()
109 writel_relaxed(val, timer->base + CNTV_CTL); in arch_timer_reg_write()
112 writel_relaxed(val, timer->base + CNTV_TVAL); in arch_timer_reg_write()
130 val = readl_relaxed(timer->base + CNTP_CTL); in arch_timer_reg_read()
133 val = readl_relaxed(timer->base + CNTP_TVAL); in arch_timer_reg_read()
140 val = readl_relaxed(timer->base + CNTV_CTL); in arch_timer_reg_read()
143 val = readl_relaxed(timer->base + CNTV_TVAL); in arch_timer_reg_read()
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/kernel/linux/linux-5.10/arch/mips/
DMakefile11 # architecture-specific flags and dependencies. Remember to do have actions
16 $(Q)$(MAKE) $(build)=arch/mips/tools elf-entry
18 $(Q)$(MAKE) $(build)=arch/mips/tools loongson3-llsc-check
29 32bit-tool-archpref = mipsel
30 64bit-tool-archpref = mips64el
31 32bit-bfd = elf32-tradlittlemips
32 64bit-bfd = elf64-tradlittlemips
33 32bit-emul = elf32ltsmip
34 64bit-emul = elf64ltsmip
36 32bit-tool-archpref = mips
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/kernel/linux/linux-5.10/drivers/scsi/mpt3sas/
Dmpt3sas_base.h6 * Copyright (C) 2012-2014 LSI Corporation
7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
27 * exercise of rights under this Agreement, including but not limited to
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
77 #define MPT3SAS_AUTHOR "Avago Technologies <MPT-FusionLinux.pdl@avagotech.com>"
172 pr_err("%s: " fmt, (ioc)->name, ##__VA_ARGS__)
174 pr_notice("%s: " fmt, (ioc)->name, ##__VA_ARGS__)
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/kernel/linux/linux-5.10/drivers/net/ethernet/intel/i40e/
Di40e_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
27 static const char i40e_copyright[] = "Copyright (c) 2013 - 2019 Intel Corporation.";
53 /* i40e_pci_tbl - PCI Device ID Table
58 * Class, Class Mask, private data (not used) }
91 static int debug = -1;
95 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
110 if (ether_addr_equal(ha->addr, f->macaddr)) { in netdev_hw_addr_refcnt()
111 ha->refcount += delta; in netdev_hw_addr_refcnt()
112 if (ha->refcount <= 0) in netdev_hw_addr_refcnt()
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/kernel/linux/linux-5.10/drivers/platform/x86/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 x86 platforms, including vendor-specific laptop extension drivers.
13 This option alone does not add any kernel code.
23 This driver adds support for the ACPI-WMI (Windows Management
26 ACPI-WMI is a proprietary extension to ACPI to expose parts of the
27 ACPI firmware to userspace - this is done through various vendor
38 any ACPI-WMI devices.
45 Say Y here if you want to be able to read a firmware-embedded
50 be called wmi-bmof.
62 USB MCU such as the X51 and X51-R2.
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/kernel/linux/linux-5.10/drivers/tty/serial/
Ducc_uart.c1 // SPDX-License-Identifier: GPL-2.0
12 * If Soft-UART support is needed but not already present, then this driver
13 * will request and upload the "Soft-UART" microcode upon probe. The
29 #include <linux/dma-mapping.h>
43 * but Soft-UART is a hack and we want to keep everything related to it in
46 #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
49 * soft_uart is 1 if we need to use Soft-UART mode
62 * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE
63 * UART, we have major number 204 and minor numbers 46 - 49, which are the
70 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
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/kernel/linux/linux-5.10/drivers/staging/rtl8188eu/include/
Drtl8188e_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
13 #define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */
56 * Multi-Function GPIO Pin Control.
59 * Multi-Function GPIO Select.
63 * Multi-Function control source.
175 /* RTL8723 series ------------------------------ */
250 /* Format for offset 540h-542h:
261 * |<--Setup--|--Hold------------>|
262 * --------------|----------------------
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/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
Dhal_com_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
13 #define HAL_NAV_UPPER_UNIT 128 /* micro-second */
70 #define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
71 #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
72 #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */
198 /* RTL8723 series ------------------------------- */
296 /* Format for offset 540h-542h: */
303 /* |<--Setup--|--Hold------------>| */
304 /* --------------|---------------------- */
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